JP2002168920A - Testing device for ic - Google Patents

Abstract

PROBLEM TO BE SOLVED: To execute test in an even-numbered pin side in parallel even when a pin multiplexer is operated. SOLUTION: This IC testing device using a pin multiplexer function is provided with a selector means for inputting the first pattern data supplied to the first input pin of a tested IC and the second pattern data supplied to the second input pin applied with the pin multiplexer function to select one thereof, the first formatter means for outputting a test signal based on the first pattern data selected by the selector means to the first input pin through a driver and outputting the first expected value, and for outputting a test signal based on the second pattern data selected by the selector means to the first input pin through the driver and outputting the second expected value, the first comparison means for comparing an output of the fist output pin of the tested IC with the first and second expected values, and the first and second memory means for storing determination outputs from the first comparison means to correspond to the first and second pattern data.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to an improvement of an IC test apparatus using a pin multiplex function.

[0002]

2. Description of the Related Art A general system configuration of a function test of an IC test apparatus will be described with reference to an LSI function test apparatus of FIG. 1 denotes an IC under test (hereinafter referred to as DUT (Device Under Tes).
t)) 1a is an input pin, 1b is an output pin, and 1c is a power supply pin.

Reference numeral 2 denotes a central processing unit (CPU) connected to a network system, which edits, translates, and manages a test program describing test conditions and an execution order, and a test pattern program describing pattern data, and further transmits to a test apparatus. It performs data setting, execution of measurement, and processing of measurement data. 2a is its input / output device, and 2b is a mass storage device.

Reference numeral 3 denotes a timing signal generator controlled by communication with the CPU 2, a main clock signal for determining a clock cycle of a test operation, a driver timing signal for determining the rise and fall of input pattern data to be applied to the DUT, and a DUT. A comparison timing signal for instructing a comparison between the output data and the expected value data is generated.

A pattern generator 4 is also controlled by communication with the CPU 2, and generates a test pattern for a functional test (an input pattern to be added to the DUT and an expected value pattern for output data determination).

[0006] 5 is a waveform shaper (formatter),
The input pattern data output from the pattern generator 4 and the timing signal output from the timing signal generator 3 are combined to generate a waveform to be applied to the DUT.

[0007] A dotted block 7 is a pin electronics section, which comprises a driver 7a for applying a voltage required for a DUT test to a digital signal output from the waveform shaper, and an analog level comparator 7b for converting the DUT output to a digital signal.

Reference numeral 8 denotes a logical comparison controller, which compares the DUT output obtained through the analog level comparator 7b with expected value pattern data from the pattern generator 4 to judge pass / fail.

Reference numeral 9 denotes a failure analysis memory which receives a judgment signal from the logical comparison controller 8 and is controlled by communication with the CPU 2, and stores a failure state when a failure is found in the DUT in a functional test. The failure analysis memory is used for checking at the development stage or for failure analysis when a problem is found in the performance of the LSI.

The pin multiplex function will be described with reference to the conceptual diagram of FIG. Reference numeral 11 denotes a first line for supplying a test signal to the odd input pin of the DUT1, and reference numeral 12 denotes a second line for supplying a test signal to the even input pin of the DUT1, and only the test signal for the odd input pin of the first line is supplied to the DUT1. The second line 12 is supplied to the odd input pin 1a and the DUT1
Are not connected to the input pins, and are in a floating state.

A block 13 is a means for realizing a pin multiplex function.
This is realized by a switch 14 that short-circuits the first and second lines 12. By adopting such a configuration, the odd input pin 1a of the DUT 1 can use both the test signal of the first line 11 and the test signal of the second line 12 by multiplexing.

With such a pin multiplex function, a device that can express only one state in one test cycle can generate two states. Therefore, the test can be performed at twice the apparent speed, and comparison can be performed by applying two strobes in one test cycle. In normal pin multiplexing, the state of the odd-numbered pins is multiplexed into the odd-numbered pins in the first half of one test cycle (one rate), and the state of the even-numbered pins is multiplexed and output in the latter half.

FIGS. 6A to 6D show examples of a mode combination of the first half and the second half in one test cycle. FIG. 6A shows a continuous drive mode, and FIG. The comparator mode, (C) is the first half comparator and the second half drive mode, and (D) is the comparator continuous mode.

In the case where only the operation modes (B) and (C) are performed, a single pin can be realized without using the pin multiplex by using the technique of intra-rate I / O.
Also, in the operation (A), the conventional multi-pattern method is used, so that one operation can be performed without using pin multiplex.
It can also be achieved with pins.

However, in order to realize the operation mode (D), a pin multiplex method is indispensable. Also in the case of the operation modes (A) to (C), it is more effective to use the pin multiplex method.

The first reason is that, usually, the output state of the driver and the expected value of the comparator are expressed by 3 bits.
t, 8 pattern data is sufficient. Pattern data is information output from the pattern memory. The operation mode of FIG. 2 realized by pin multiplexing is 3bi
Since t and 8 patterns cannot be expressed, pattern data for two pins is required.

The second reason is that a normal comparison operation requires a memory (fail memory) for storing the result. The contents include a pattern address and the like as information at that time besides Pass / Fail. This is based on the premise that one piece of information is used at one test rate. If there is a possibility that two pieces of fail will occur at one test rate, the pin memory is used and two pins of fail memory are used. There is a need to.

As described above, although the pin multiplex function has an advantage, since the odd pins and the even pins are always pin multiplexed, there is a disadvantage that the number of usable pins is reduced by half. An object of the present invention is to provide an IC test apparatus that can avoid such disadvantages in an environment using a pin multiplex function.

[0018]

In order to achieve the above object, a feature of the present invention is that an IC test apparatus using a pin multiplex function is provided.
Selector means for inputting the first pattern data given to the first input pin of the IC under test and the second pattern data given to the second input pin to which the pin multiplex function is applied, and selecting one of them; A test signal based on the first pattern data selected in the step (a) is output to the first input pin via a driver, a first expected value is output, and a test signal based on the second pattern data selected by the selector is output. First formatter means for outputting to the first input pin and outputting a second expected value via a driver; and comparing the output of the first output pin of the IC under test with the first and second expected values. A first comparing means; and first and second memory means for storing the judgment output of the first comparing means in correspondence with the first pattern data and the second pattern data. To the point that there is.

A second aspect of the present invention is characterized in that scramble memory means for inputting the second pattern data and converting it into pattern data for a second input pin of the IC under test, and a test signal based on the output of the scramble memory means. Second formatter means for outputting to the second input pin via a driver and for outputting a third expected value;
A second comparing means for comparing the output of the second output pin with the third expected value, and a third memory means for storing the judgment output of the second comparing means.

A third feature of the present invention is that the first input pin and the first output pin are odd pins (even pins), and the second input pins and the second output pins are even pins (odd pins). At one point.

According to a fourth aspect of the present invention, the first input pin and the second output pin are adjacent pins.

According to a fifth aspect of the present invention, the first to third aspects are provided.
The memory means is characterized in that when the judgment results of the first and second comparing means are defective, the contents of the defect are recorded.

The invention according to claim 6 is characterized in that a second scramble memory means is added before the selector means.

[0024]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram showing a main part of an IC test apparatus to which the present invention is applied. First, a normal test operation not using the pin multiplex function will be described.

The selector 15 always selects the odd pin pattern data PDodd during normal operation. The formatter 16 creates a driver format DV and an expected value EP1 from the pattern data and the operation mode.

The driver format DV is the driver 1
7 is input to the odd input pin of DUT1. The odd-numbered pin output signal is compared with a reference by an analog comparator 18 and then input to a digital comparator 19, generated by a formatter 16 and compared with an expected value EP1 to generate a Pass / Fail determination output.

Pass / F from digital comparator 19
The ai information is stored in the memory 20 corresponding to the odd pin input. As described in FIG. 4, this information is used for failure analysis and the like in communication with a higher-level central processing unit as necessary.

Reference numeral 21 denotes a memory corresponding to an even-numbered pin at the time of a pin multiplexer, and is not used in a normal operation.

The operation of the odd input pin during the normal operation has been described above. The operation of the even input pin to which the pattern data PDeven is input is basically the same as the operation of the odd pin input. That is, the formatter 23 corresponds to the odd-numbered pin-side formatter 16, the driver 24 corresponds to 17, the analog comparator 25 corresponds to 18, the digital comparator 26 corresponds to 19, and the memory 27 corresponds to 20. .

The difference from the odd pin side is that the formatter 2
3 is that a scramble memory 22 is provided at the previous stage. The pattern data PDeven is input to the address of the scramble memory, and the data output is input to the formatter 23 as pattern data. In the normal operation, the address map of the scramble memory is written with information of input = output as shown in FIG.

The above is the operation during the normal operation. The operation when the pin multiplexer function is used will be described. First, on the odd pin side, the selector 15 selects the odd pin pattern data PDodd in the first half of one test rate, and selects the even pin pattern data PDeven in the second half.
By such a selection operation, the various operation modes shown in FIG. 6 become possible.

The operation of the formatter 16 and the digital comparator 19 in the first half and the second half of one test rate is basically the same as the normal operation. In the first half of one test rate, the formatter 16 outputs the odd pin pattern data PDod.
An expected value EP1 corresponding to d is generated. In the latter half, an expected value EP2 corresponding to the even-numbered pin pattern data PDeven is generated and output to the digital comparator 19, and the control signal S is output to the digital comparator 19.

In the operation mode of FIG. 6D, since two comparison results may be obtained at one test rate, a memory 21 for storing Pass / Fail information corresponding to an even pin input is prepared. ing. The formatter 16 can determine which of the odd pins or the even pins has been compared (or both),
The control signal S is sent to the digital comparator 19 to
The memories 20 and 21 for writing the fail information are selected.

Next, the operation of the even-numbered pin at the time of the pin multiplexer will be described. Basically, there is no difference from the normal operation, but the pattern data PDeven is naturally created for the test on the odd-numbered pin input side at the time of the pin multiplexer. Therefore, the scramble memory 22 is used to secure the degree of freedom of the pattern data.

FIG. 3 shows the scramble memory 22 in this case.
7 is a memory map showing an example of a relationship between input pattern data and output pattern data. By providing such a pattern conversion function, even at the time of the pin multiplexer, the even-numbered pin side receives the output pin signal and the formatter 2.
The normal test comparing the expected value EP3 from No. 3 can be executed in parallel.

Next, another embodiment of the present invention will be described. At the time of the pin multiplexer, the memory 21 provided on the odd-numbered pin side is omitted, and the memory 27 on the even-numbered pin side is substituted. By doing so, there is a restriction that the even-numbered pin side can be used only as a driver at the time of a pin multiplexer, but there is an effect that the circuit scale is significantly reduced.

Further, if the scrambling memory is arranged not in the preceding stage of the formatter 23 but in the preceding stage of the selector 15, there is a limitation on the pattern. However, the test operation of the even-numbered pin input is perfectly guaranteed during the operation of the pin multiplexer. You.

Normally, a pin using a pin multiplexer does not require much complicated operation, so this may be more effective. Therefore, although the circuit scale is slightly increased, the degree of freedom can be further increased by providing the third scramble memory in the preceding stage of the selector 15 in addition to the scramble memory 22 of FIG.

[0039]

As is apparent from the above description,
According to the present invention, by introducing the selector 15, the memory 21, and the scramble memory 22, an IC capable of executing tests on the even-numbered pins in parallel even during the operation of the pin multiplexer.
A test device can be easily realized.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a main part of an IC test apparatus to which the present invention is applied.

FIG. 2 is a memory map showing the contents of a scramble memory during normal operation.

FIG. 3 is a memory map showing the contents of a scramble memory during a pin multiplex operation.

FIG. 4 is a system configuration diagram of a general IC test apparatus.

FIG. 5 is a conceptual diagram of a pin multiplex function.

FIG. 6 is an explanatory diagram showing a mode example of a first half and a second half of a state combination in one test cycle during a pin multiplex operation;

[Explanation of symbols]

 Reference Signs List 1 IC under test (DUT) 15 Selector 16, 23 Formatter 17, 24 Driver 18, 25 Analog comparator 19, 26 Digital comparator 20, 21, 27 memory 22 Scramble memory

Claims (6)

[Claims] 1. An IC test apparatus using a pin multiplex function, wherein first pattern data given to a first input pin of an IC under test and second pattern given to a second input pin to which the pin multiplex function is applied. Selector means for inputting data and selecting one of them; outputting a test signal based on the first pattern data selected by the selector means to the first input pin via a driver and outputting a first expected value; A first formatter for outputting a test signal based on the second pattern data selected by the selector to the first input pin via a driver and outputting a second expected value; and a first formatter for the IC under test. First comparing means for comparing the output of an output pin with the first and second expected values; and determining the output of the first comparing means with the first pattern data and the first pattern data. And second patterns stored in correspondence with the second and third pattern data.
An IC test apparatus comprising: a memory unit. 2. The method according to claim 2, wherein the second pattern data is inputted and said I
A scramble memory means for converting the data into pattern data for a second input pin of C; outputting a test signal based on the output of the scramble memory means to the second input pin via a driver;
A second formatter for outputting an expected value; a second comparing unit for comparing an output of a second output pin of the IC under test with the third expected value; a second storing unit for storing a judgment output of the second comparing unit. The IC test apparatus according to claim 1, further comprising three memory means. 3. The device according to claim 1, wherein the first input pin and the first output pin are odd pins (even pins), and the second input pins and the second output pins are even pins (odd pins). Item 3. The IC test apparatus according to Item 1 or 2. 4. The IC test apparatus according to claim 1, wherein said first input pin and said second output pin are adjacent pins. 5. The first to third memory means comprises:
5. The IC according to claim 1, wherein the content of the defect is recorded when the result of the determination by the second comparing means is defective.
Testing equipment. 6. The IC test apparatus according to claim 5, wherein a second scramble memory means is added before the selector means.