JPH022970A - Method for testing logical integrated circuit - Google Patents

Abstract

PURPOSE:To shorten testing time by inserting many number of page cycles (cycles of page, read, modify and write) into one CAS cycle (cycle of read, modify and write). CONSTITUTION:A test-signal generating part 2 of an IC testing apparatus 1 supplies clock signals for load address strobes (RAS), write enable (WE) signals and column address strobes (CAS) into an IC under test 4. Detected signals DET are inputted into detecting and judging part 3 and tested. When the clock signals of the CAS have the operating times for page, read, modify and write modes at this time after the specifeid activating time, the effect for shortening the time can be obtained.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method for testing a logic integrated circuit, and more particularly to a method for testing a logic integrated circuit having a page mode function.

[Conventional technology]

With the recent increase in the scale of logic integrated circuits, the length of test time has become a problem.

- In the IC under test, a row address strobe (hereinafter referred to as RAS), a column address strobe (hereinafter referred to as CA)
The IC under test is tested by inputting three clock signals: S) and write enable (hereinafter referred to as γ), performing data write and read operations, and making a decision based on the detection signal.

Examples of long cycle time patterns in dynamic access memory include marching in the column direction.

FIG. 3 is a timing diagram of each clock signal ρ1 in one of the conventional logic integrated circuit testing methods.

Both RA'S and CAS clock signals are connected to the IC under test.
The maximum activation time trt required by 256K DRAM
As As, it has 10 μs.

There are five consecutive patterns described below as marching patterns for the test.

(a) O write (all bits scan at address +1') (b) O read - 1 write (all bits scan at address +1) (c) 1 read - 0 write (all bits scan at address '+1') (d) 0 read-1 write (all bits scanned at address 1'°) (e) 1 read-0 write (all bits scanned at address 1'°).

Here, if N is the number of memory cells, (a> then IN,
Since 2N is used for each of (b) to (e), it becomes 9XN.

For example, in the case of 256K DRAM, N is 262°144.

[Problem to be solved by the invention]

The conventional testing method for logic integrated circuits described above has a problem in that it requires a long cycle time marching that requires a long test time as RAS time, and a long total testing time.

That is, the test time TL is required to be 10 μs as t RAS, and if tRP is the RAS precharge time, it is expressed by equation (1).

TL =9XNX (10μs+tILp) −(1
) This test time TL is tn for 256K DRAM.
Substituting 100 ns as p into equation (1), we get equation (2)
Get the value of an expression.

Tc,=9x262,144X (10μs+100n
s)=23.8(s)-(2> An object of the present invention is to provide a method for testing a logic integrated circuit that requires a short test time.

[Means to solve the problem]

The method for testing a logic integrated circuit of the present invention involves inputting three clock signals, a row address strobe, a column address strobe, and a write enable, from a test signal generator to an integrated circuit under test, and detecting a detection signal output from the integrated circuit under test. In the logic integrated circuit testing method in which the clock signal of the column address strobe is input to a detection/judgment section for testing, the clock signal of the column address strobe is activated after a predetermined activation time.
It is configured to have a write mode operation time.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a timing diagram of each clock signal according to a first embodiment of the present invention, and FIG. 2 is a block diagram of an example of an IC testing apparatus using the present invention.

As shown in FIG. 1, the test signal generator 2 includes RAS, CA
Supply the S and WE clock signals to the C4 under test,
The detection signal DET is input to the detection/judgment section 3 and tested.

As shown in Figure 2, the maximum required activation time t for RAS and CAS is 10 μs for RAS/CA
After S read-modify-write cycle, 15
Page mode time τf'M of page read/modify/write cycle of page cycle PCl5
is added.

The present invention controls the number of cycles M of the page mode read/modify/write function of the IC4 under test using a short page cycle p c ts of the minimum standard time to read and write at high speed.

The test time Ts can be expressed by equation (3).

Ts=[5X(10μs + tip) XN/ (1
+M)) 10(5X190nsxN/(1+M))"-
Here, read-modify-write is performed within one cycle, and marching is performed at 9 times in order to read and invert data.
It has been shortened from N to 5N.

In addition, when the RAS access time tnAC is 150ns, the standard minimum value for the short base 3 read modify write cycle time is 190ns.
s is required.

Here, for the 256K DRAM, 15 is substituted as the page cycle number M into equation (3) to find the test time Ts of equation (4).

Ts =5X262,144/16X10. czs+5
X15X262, 144/16X190ns=0.82
seconds + 0.23 seconds = 1.0 seconds... (4) Therefore, the conventional 2
There is an effect of time reduction of 95.7%, which is 22.8 seconds compared to 3.8 seconds.

Here, if the number of page cycles M of the short page read mode modify write after t RAS during the maximum activation period to be guaranteed is 15 or more, the time reduction effect will be even greater.

Even if the number of page cycles M is 1, the test time Ts is 72%.
can be shortened.

〔Effect of the invention〕

As explained above, the present invention utilizes read/modify/write and page functions for marching with a long sile time, so that 15 page cycles (page・If a read-modify-write cycle is inserted, for example, in a 256DRAM, tRAs (RAS access time) will be reduced to 15
In the case of a standard of 0 ns, there is an effect that the total test time can be significantly shortened by about 70 to 96%.

Note that in this test pattern, each bit is t RAS = 1
It can be tested to guarantee 0 μS.

[Brief explanation of the drawing]

FIG. 1 is a timing diagram of each clock signal in the first embodiment of the present invention, FIG. 2 is a block diagram of an example of an IC testing device using the present invention, and FIG. 3 is a conventional logic integrated circuit testing method. FIG. 3 is a timing diagram of each clock signal in an example. DESCRIPTION OF SYMBOLS 1... IC test device, 2... Test signal generation part, 3.
...Detection/judgment section, 4...IC under test, CAS...
Column address strobe, DET...detection signal, P
Cl5...Page cycle, RAS...Row address strobe, WE,...Write enable, PM...
-Page mode time, tRAS...RAS time. Figure No. 3, No. 3 ZC21

Claims (1)

[Claims] In the method for testing a logic integrated circuit in which three clock signals, a row address strobe, a column address strobe, and a write enable, are input from a test signal generation section to a detection/judgment section, a detection signal output from the integrated circuit under test is tested. A method for testing a logic integrated circuit, wherein the clock signal of a column address strobe has a page read modify write mode operation time after a predetermined activation time.