JPS61292276A - Detecting device for frame synchronization - Google Patents

Abstract

PURPOSE:To quickly perform the detection of a frame synchronization by using the maximum detection window estimating function in which the detection window is the maximum at the initial time of a frame detecting operation and using the optimum estimating function after once a frame synchronizing signal is detected. CONSTITUTION:The counting of a clock pulse CP is started by a sector detecting signal apparatus SD and a search mode estimating function FC1, a synchronizing mode estimating function FC2 and a synchronization interpolating pulse PIF are outputted from a ROM5. A selector 6 outputs the function FC1 to an adding point 4 and when the frame synchronizing signal is not detected, the pulse PIF is outputted as a frame synchronization detecting pulse PFD through the selector 6 and an OR circuit 7. When the frame synchronizing signal is appeared at a data DT, a synchronization detecting pulse PSD is outputted from a synchronization detecting circuit 8 and with setting an FF10, the output of the estimating function FC1 from the selector 6 is interrupted. The pulse PSD is delayed by delay circuits 9 and 11 and after the resetting of the FF10 by a pulse PD2, the selector 6 outputs the estimating function FC2 to the adding point 4.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field] The present invention relates to a frame synchronization detection device that can reliably detect frame synchronization in a recording device having a data recording format in which data is recorded in a frame configuration.

[Prior Art] Devices using magnetic recording media such as magnetic tapes and magnetic disks are widely used as auxiliary storage devices in computer systems. There have been proposals to use optical recording media (for example, optical discs) that can be used as auxiliary storage devices.

For example, in the case of an optical disc, a laser spot with a diameter of 1
Two micrometer-sized bits (small holes) are placed on the recording track on the surface.
Data is recorded by forming them at a period (interval) of approximately μm, and the storage capacity is 1 per sheet with a diameter of approximately 30 cm.
It is approximately 011 to 1012 bits. Usually, one recording track is set in a spiral shape, or many recording tracks are set in concentric circles at predetermined intervals.

Now, since the access speed of auxiliary storage devices is generally much slower than that of main storage devices, data is recorded in blocks of a certain amount in consecutive areas.

At that time, to ensure that data can be read and written in a short time, predetermined blocks of data are organized into sectors,
Each sector is identified by assigning an address (sector address).

FIGS. 7(a) and 7(b) show an example of a data recording format on a track of an optical disc.

In FIG. 5A, the track TR includes a preformat area PF, a data area OF, and a gap GPI separating the preformat area PF and the data area DF.
A plurality of sectors SC are consecutively set apart from each other by a gap GP2.

Note that the preformat areas PF are formed in advance on the track TR at intervals of the total number of bits of the data area DF and the gap GP2.

In addition, as shown in FIG. 6(b), the preformat area PF contains a synchronization signal for matching circuit conditions, that is, a bit synchronization signal for synchronizing the bit clock of the data write/read circuit with the generation timing of recording data. A preamble consisting of a preamble BS, a sector synchronization signal SS consisting of a bit string (pattern) with sharp autocorrelation for detecting this preformat area PF, and a sector address SA for identifying a sector SC. As the bit synchronization signal BS, a PLL (P-hase) for extracting a bit clock and data based on a read signal from an optical pickup section is used.
A signal is used that allows the Locked Loop circuit to be properly locked. For example, a signal that changes the state of the read signal with a minimum inversion period (i.e.

The recording state on the optical disc is "rollolol...") in which the minimum pit length is repeated.

Further, the data area OF includes a plurality of pieces of data having a frame configuration with a frame synchronization signal FS attached thereto.

It consists of a preamble (bit synchronization signal BS) attached to the beginning of these data. Note that the preamble in the data area DF requires a smaller number of bits than the preamble in the preformat area PF, and the frame synchronization signal FS is composed of sharp autocorrelation bangs similar to the sector synchronization signal SS.

Note that the preamble BS, sector synchronization signal SS, sector address SA, gap GPI, GP2 of the preformat area PF, and the preamble BS and frame synchronization signal FS of the data area OF mentioned above are recorded on the optical disc in an unmodulated state. The frame data in the data area DF is recorded after being subjected to predetermined modulation.

Now, when recording data in such a recording format, first bit synchronization is achieved with the preamble of the preformat area PF, then the sector synchronization signal SS is detected, and the sector address SA is read out based on the detection timing.

If it rains the desired sector, the gap GPI
After writing the preamble in the data area DF, the frame data of the first frame is sent to the frame synchronization signal FS.
Then, the frame synchronization signal FS and frame data of each frame are sequentially recorded.

When reading data, read the sector address SA in the same manner as described above, and if it indicates the desired sector, re-establish pill synchronization with the preamble of the data area, and then detect the frame synchronization signal FS. Read frame data for each frame based on timing.

This read frame data is then converted into the original data before modulation by a predetermined demodulation process.

In this way, data is recorded and read by referring to the pre-format area recorded in advance.

Incidentally, although optical disks have a significantly high recording density as described above, they are considered to be quite susceptible to bit error rates, rotational fluctuations of the drive system, and the like.

On the other hand, since a systematic error correction code is usually added to each frame data before modulation, even if a data error occurs, it can be completely recovered to a certain extent and there is no major problem.

Also, considering the case where the frame synchronization signal FS cannot be detected due to a bit error or rotational fluctuation, if the immediately preceding frame synchronization signal FS is detected, an interpolation signal etc. is generated based on the detection timing. Although it is possible to generate frame synchronization timing in a pseudo manner by etc. becomes large, there is a possibility that this first frame synchronization signal FS cannot be detected.

When such a situation occurs, the subsequent frame synchronization signal FS
It may take a relatively long time to detect the
Frame synchronization cannot be detected for the data frames in between, resulting in the inconvenience that data in that portion cannot be detected.

Further, if a state in which a frame synchronization signal cannot be detected continues and pseudo frame synchronization detection using the interpolation signal described above continues, there is a possibility that the timing at which the actual frame synchronization signal is generated cannot be detected.

[Objective] The present invention has been made in order to solve the above-mentioned disadvantages of the conventional technology, and it is an object of the present invention to provide a frame synchronization detection device that is resistant to bit errors, rotational fluctuations of the drive system, etc. Further, even if a state in which a frame synchronization signal cannot be detected continues, a frame synchronization signal that is properly detected immediately after that can be reliably detected.

[Configuration] In the present invention, as a prediction function for detecting a frame synchronization signal, a maximum detection window prediction function with a maximum detection window is used at the initial stage of frame detection operation, and once a frame synchronization signal is detected, an optimal prediction function is used. By using this, frame synchronization can be detected quickly. In addition, since the output timing of the synchronization detection signal is the same when the frame synchronization signal is detected at a predetermined timing and when frame synchronization is detected using an interpolation signal, even if the frame synchronization signal cannot be detected continuously, , it is possible to reliably detect a frame synchronization signal that is properly generated immediately after that. Furthermore, if a frame synchronization signal is actually detected, output of the interpolation signal is prohibited to prevent unnecessary signals from being output.

Embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

First, the principle of the present invention will be explained.

In the present invention, as shown in FIG. 1, a frame synchronization signal FS is placed at the beginning of a bit synchronization signal BS having the same length as the data amount of one frame in the preamble PA of the data area OF.
After detecting frame synchronization in advance with this preamble PA,
By detecting the frame data area FFD, frame synchronization can be reliably detected in the frame data area FFD.

Further, the frame synchronization signal FS consists of a bit string with a sharp autocorrelation pattern, for example, 00110
0111100 (12 bits).

The frame synchronization detection is performed by the method shown in FIG.

That is, when a sector is detected, first, a search mode is entered in which the frame synchronization signal FS is detected using a search mode prediction function PCI having a very large detection window width for the frame synchronization signal FS.

In this search mode, the search mode prediction function PC
When the frame synchronization signal FS is detected by I, a synchronization detection pulse is output. In addition, if the frame synchronization signal FS cannot be detected, a synchronization interpolation pulse is output in place of the synchronization detection pulse at a timing synchronized with the predicted detection timing, and this process is continued until the frame synchronization signal FS is actually detected. repeat.

In this way, when frame synchronization is detected using the search mode prediction function PCI, the next step is to detect the synchronization mode prediction function F, which is the optimal prediction function for the frame synchronization signal FS.
A transition is made to the synchronization mode in which the frame synchronization signal FS is detected using C2.

In this synchronization mode, when the frame synchronization signal FS is detected by the synchronization mode prediction function FC2, a synchronization detection pulse is output, and when the frame synchronization signal FS cannot be detected, synchronization is performed at a timing synchronized with the predicted detection timing. Outputs a synchronous interpolation pulse instead of the detection pulse,
The above process is repeatedly executed until data reading of the sector is completed.

As the search mode prediction function PCI, for example.

As shown in Figure 3, r'1llllllllllll
This search mode prediction function PCI can detect the frame synchronization signal FS even if it deviates from the predicted position by 8 bits before or after the predicted position without causing a bit error. Note that if there is a bit error, the frame synchronization signal FS is not detected. That is,
There is no possibility of false detection.

In addition, the synchronous mode prediction function (that is, the optimal prediction function) Fe2 in this case is r1122 as shown in FIG.
32211J, such a synchronous mode prediction function F
In C2, if there is no bit error, the frame synchronization signal
If S can be detected and the frame synchronization signal FS is present at the predicted position, the frame synchronization signal FS can be detected even if a 2-bit bit error occurs.

Thus, in the first part of the preamble PA.

Since the frame synchronization signal FS is detected using the search mode prediction function PCI having a very wide detection window width, the frame synchronization signal FS can be detected quickly in a state where no bit error occurs. Also, once the frame synchronization signal F
After detecting S, the frame synchronization signal
Since S is detected, frame synchronization can be reliably detected.

FIG. 5 shows an apparatus according to one embodiment of the invention.

In the same figure, the read data DT separated from successive signals from the optical disk by a data separation circuit (not shown) is applied to the data input terminal of the serial/parallel converter 1. A clock pulse CP separated from is applied to the clock inputs of the serial/parallel converter 1 and the counter 2.

The serial/parallel converter 1 converts the input data DT into 12-bit parallel data PD12 having the same length as the frame synchronization signal FS, and converts the input data DT into 12-bit parallel data PD12.
12 to the ROM (read only memory) 3.

The ROM3 stores data BN that indicates the number of bits that match the 12-bit data pattern and the frame synchronization signal FS, and stores the input parallel data PD12.
The data BN corresponding to is output to the addition point 4.

In this way, the serial/parallel converter 1 and the ROM 3 compare the pattern of the continuous data DT of a predetermined number of bits with the pattern of the frame synchronization signal FS, and output data corresponding to the matched number of bits. is configured.

Further, the count value CDF of the counter 2 is added to a ROM 5 that generates a search mode prediction function PCI, a synchronous mode prediction function FC2, and a synchronous interpolation pulse PIF at predetermined timings in one frame period.
The search mode prediction function PCI (2 bit width) output from the selector 5 is input to the input terminals IA and 2A of the selector 6, and the synchronous mode prediction function FC2 is input to the input terminals IB and 2B of the selector 6.
The synchronous interpolation pulse PIF is applied to input terminals 3A and 3B of the selector 6, respectively.

In this way, the data DT
A prediction function generator is configured to generate a prediction function and a synchronous interpolation pulse for each frame in synchronization with the input of.

The selector 6 selects input terminals IB, 2B, and 3B when the select input terminal S is at logic level L, and selects the select input terminal S.
When the signal applied to the strobe input terminal ST is at the logic level H, the input terminals IA, 2A, and 3A are selected, and when the signal applied to the strobe input terminal ST is at the logic level L, the respective signals are output from the output terminals IY, 2Y, and 3Y. When the signal applied to the input terminal ST is at logic level H, signal output from the output terminals IY, 2Y, and 3Y is prohibited.

Search mode prediction function PCI and synchronous mode prediction function FC output from output terminals IY and 2Y of this selector 6
2 is added to the other input terminal of summing point 4, and also to output terminal 3
The synchronous interpolation pulse PIF output from Y is applied to one input terminal of the OR circuit 7.

Addition point 4 is data BN added from ROM 5 and search mode prediction function PCI added from selector 6.
Alternatively, the value of the synchronous mode prediction function FC2 is added and the addition result is output to the synchronous detection circuit 8.

The synchronization detection circuit 8 compares the output signal of the addition point 4 with a threshold value obtained by adding 1 to the length of the frame synchronization signal FS, that is, 13 in this case, and if the addition result is 13 or more, the output signal of the frame synchronization signal FS is Synchronous detection pulse PSD is detected.
This synchronization detection pulse PSD is applied to the clock input terminals of a 9-bit delay circuit 9 and a flip-flop 10.

The output pulse PDI of the delay circuit 9 is applied to the 3-bit delay circuit 11 and the other input terminal of the OR circuit 7.
The output pulse PD2 of the delay circuit 11 is applied to the clock input terminal of the flip-flop 12, and is also applied to one input terminal of the AND circuit 14 via the inverter 13.

The output of the flip-flop 10 is the strobe signal SST, and the output of the flip-flop 12 is the select signal SS.
The output signal of the OR circuit 7 is output as a frame synchronization detection signal PFD to the next stage signal demodulator, etc. circuit 1
It is added to one input terminal of 5.

The other input terminal of this OR circuit 15 is applied with a sector detection signal SD, which is output from the drive device of the optical disk device and which indicates that the target sector has been detected. It is added to the clear input terminal of 2.

Also, the sector end signal EO output from the signal demodulator
5 is a signal that is lowered to logic level L when demodulation of the data of the last frame of the sector is completed, and is applied to the clear input terminal (negative logic) of the flip-flop 12 and the other input terminal of the AND circuit 14. ing.

With the above configuration, when the optical disk is rotationally driven by the drive device of the optical disk device, the sector address SA of the target sector is detected.

This drive device outputs a sector detection signal SD at a predetermined timing. As a result, the counter 2 starts counting clock pulses CP from zero, so the ROM 5
search mode prediction function PCI at a predetermined timing from
Synchronous mode prediction function FC2 and synchronous interpolation pulse PIF
is output (see FIGS. 6(a), (c), and (b)).

Also, at this point, both flip-flops 10 and 12 are cleared, so the strobe signal SST and select signal SS are both at the logic level (see Figures 6(e) and (f)). Accordingly, the selector 6 selects the input terminals LA, 2A, 3A and outputs the search mode prediction function PCI to be added to the input terminals IA, 2A to the addition point 4 (see FIG. 6(f)).

Now, the first frame synchronization signal FS of the preamble PA is changed as shown in FIG. 6(g) due to a bit error or other reason.
If it is not detected as shown by the broken line A1 in , the synchronous interpolation pulse PIF output at the timing immediately after the output of the search mode prediction function PCI is completed is
It is output as a frame synchronization detection pulse PFD (see FIG. 6(1)) via the output terminal 3Y of the selector 6 (see FIG. 6(k)) and the OR circuit 7.

Further, this frame synchronization detection pulse PFD is applied to the reset input terminal of the counter 2 via the OR circuit 15,
At the rising timing, the counter 2 is cleared to zero, and the counting operation is repeated again from zero. As a result, the prediction function generation operation for the next cycle is executed.

For example, when the second frame synchronization signal FS appears in the data DT as shown as A2 in FIG. 6(g), the synchronization detection circuit 8 to synchronization detection pulse PSD
is output (see FIG. 6(h)), thereby setting the flip-flop 10 and outputting the strobe signal SST.
becomes a logic level H, and the signal output of the selector 6 is prohibited, so at this point, the output of the search mode prediction function PCI from the selector 6 to the addition point 4 is discontinued.

When this synchronization detection pulse PSD is delayed by 9 bits by the delay circuit 9 and outputted as a pulse PDI, this pulse PDI is outputted as a frame synchronization detection pulse PFD via the OR circuit 7, thereby.

As described above, counter 2 is cleared and the next cycle's prediction function generation operation is executed.

In addition, when the frame synchronization signal FS is detected in this way, when the synchronization interpolation pulse PIF is output at the above-mentioned timing, the selector 6 is in the output prohibited state, so in this case, the synchronization interpolation pulse PIF output is prohibited.

Then, when the pulse PDI is delayed by 3 bits by the delay circuit 11 and output as a pulse PD2 (see FIG. 6(j)), this pulse PD2 is outputted to the flip-flop 12.
is applied to the clock input terminal of inverter 1 at the same time.
3 is converted into a negative logic pulse and applied to the clear input terminal of the flip-flop 10 via the AND circuit 14, which resets the flip-flop 10 and sets the flip-flop 12 at the same time.As a result, At the same time as the output inhibited state of the selector 6 is released, the selector 6 is connected to the input terminals IB and 2B.

3B is selected, and the synchronous mode prediction function FC2 applied to the input terminals IB and 2B is output to the addition point 4.

In this way, once the frame synchronization signal FS is detected, the frame synchronization detection mode is shifted from the search mode to the synchronization mode.

In this synchronous mode as well, almost the same detection operation as in the search mode described above is performed.

That is, in this synchronization mode, if the frame synchronization signal FS cannot be detected as shown by the broken line A3 in FIG. 6(g), the synchronization interpolation pulse PIF output at the above timing is output as a frame synchronization detection pulse PFD.

Furthermore, when the frame synchronization signal FS is detected as shown by A4 in FIG. 6(g), the selector 6 is prohibited from outputting for 12 bits from that point, so the synchronization interpolation pulse PIF is Output is also prohibited.

Nine bits after the detection timing, pulse PCI is output as frame synchronization detection signal PFD.

In this way, each time the frame synchronization detection signal PFD is output, the prediction function generation operation is returned to the initial state and repeatedly executed.

Thereafter, when the reading of the frame data for the ■ sector is completed, the sector end signal EO3 falls, and the flip-flops 10.12 are cleared.

Return to initial state. .

By the way, in the embodiments described above, the timing at which the frame synchronization detection pulse PFD is output based on the synchronization interpolation pulse PIF that is output when the frame synchronization signal FS cannot be detected, and the predetermined timing, that is, the search mode prediction function PCI and synchronous mode prediction function FC2
The synchronization detection pulse PSD is delayed by 9 bits in order to match the timing at which the frame synchronization detection pulse PFD is output based on the synchronization detection pulse PSD that is output when the frame synchronization signal FS is detected at the center timing of the frame synchronization signal FS. The frame synchronization detection pulse PFD is output as the frame synchronization detection pulse PFD.

As a result, the output timing of the frame synchronization detection pulse PFD is the same when the frame synchronization signal FS is actually detected and when it is not detected, so when the frame synchronization signal FS is not detected continuously, The predicted position (predicted timing) of frame synchronization detection does not deviate significantly from the proper predicted position, and the frame synchronization signal FS can be captured within the detection range by the prediction function even immediately after such a state.

Furthermore, since the prediction function generation operation is repeatedly executed from the initial state, that is, the frame start state, depending on the output timing of the frame synchronization detection pulse PFD, if the frame synchronization signal FS is detected at a timing before the center of the prediction function. In this case, the generation operation of the prediction function returns to the initial state at a timing when 9 bits have passed since then, and therefore, the synchronous interpolation pulse PIF is not generated and output to the OR circuit 7.

On the other hand, if the frame synchronization signal FS is detected at a timing later than the center of the prediction function, the synchronization interpolation pulse PIF is generated before 9 bits have elapsed from that timing, so the synchronization also occurs in this case. In order to prevent the selector 6 from outputting the interpolated pulse PIF, the flip-flop 10 sets the selector 6 in an output inhibited state for 12 bits from the detection timing. The reason why this output inhibit state is set to 12 bits is to ensure that the synchronous interpolation pulse PIF can be masked.

In the above-described embodiment, the frame synchronization signal is composed of a 12-bit bit pattern, but this bit pattern is not limited to the above-mentioned one.

Further, the contents of the search mode prediction function and the synchronization mode prediction function described above may be appropriately selected to correspond to the contents of the frame synchronization signal. Further, the delay circuit 9,
The number of bits of 11 may also be set accordingly.

[Effects] As explained above, according to the present invention, frame synchronization is initially detected with a large detection window width, and once the synchronization detection is successful, frame synchronization is strictly performed with a small detection window width. Since detection is performed, an advantage is obtained that frame synchronization can be quickly achieved even if rotational fluctuations become large between the preformat area and the data area. In addition, since the output timing of the frame synchronization detection signal by the interpolation signal and the output timing of the frame synchronization detection signal when the frame synchronization signal is detected at a predetermined timing are matched, the state in which the frame synchronization signal cannot be detected is continuous. Even in such a case, it is possible to reliably detect a properly generated frame synchronization signal immediately after that, and therefore, it is possible to prevent out of synchronization once frame synchronization has been detected.

[Brief explanation of the drawing]

Fig. 1 is a signal arrangement diagram showing an example of a data recording format according to the present invention, Fig. 2 is a flowchart for explaining the invention in detail, and Fig. 3 is a signal arrangement diagram showing an example of a search mode prediction function. 4 is a signal arrangement diagram showing an example of a synchronous mode prediction function, and FIG. 5 is a block diagram showing an embodiment of the present invention. 6(a) to (1) are waveform diagrams for explaining the operation of the apparatus shown in FIG. 5, and FIG. 7(a) is a signal arrangement diagram showing an example of the recording format of an optical disc. (b) is a signal arrangement diagram showing an example of a recording format per sector. ■...Serial/parallel converter, 2...Counter. 3.5...ROM (read only memory), 4
...Additional points. 6...Selector, 7.15...OR circuit, 8...
・Synchronization detection circuit, 9, 11...delay circuit, 10.1
2...Flip-flop, 13...Inverter, 1
4...AND circuit. Agent Patent Attorney Crest 1) Makoto Toζノ' Figure 1 Figure 3 Figure 4r! lJ Figure 2

Claims (1)

[Claims] Following the preformatted area that marks the beginning of the sector,
A frame that detects a frame synchronization signal from data recorded on a recording medium in a recording format in which multiple data frames are arranged separated by a preamble and a frame synchronization signal with a sharp autocorrelation pattern to match circuit conditions. The synchronization detection device generates two prediction functions, a maximum detection window prediction function with the largest detection window width for detecting the frame synchronization signal, and an optimal prediction function corresponding to the frame synchronization signal, and detects the frame synchronization signal. prediction function generating means for generating an interpolation flag signal in response to prediction timing; selection means for selecting either the maximum detection window prediction function or the optimum prediction function; and data read from the recording medium and frame synchronization. matched filter means for detecting a matching state of signals; frame synchronization detection determining means for determining a detection state of the frame synchronization signal based on the output signal of the selection means and the output signal of the matched filter means; a first delay means for delaying the output of the detection determination means by a first number of delay bits; a second delay means for delaying the output of the first delay means by a second number of delay bits; and the frame synchronization. a first flip-flop set by the output of the detection/discrimination means and reset by the output of the second delay means; and a second flip-flop set by the output of the second delay means; The output signal of the delay means and the interpolation flag signal are outputted as a frame detection signal, and the output of the first flip-flop inhibits the signal output of the selection means, and the output of the second flip-flop inhibits the signal output of the selection means. A frame synchronization detection device, characterized in that the selection means selects the optimal prediction function.