JPH09106549A - Optical disk, device and method for recording/reproducing it - Google Patents

Abstract

PROBLEM TO BE SOLVED: To make possible precise access. SOLUTION: In the case that a track is wobbled by a prescribed carrier, and an address information is recorded, a clock synchronous mark (fine clock mark) with a frequency higher than the frequency of the carrier is multiplexed on the carrier to be recorded. The clock is generated based on the clock synchronous mark, and a position is detected.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an optical disc, an optical disc recording / reproducing apparatus and method, and more particularly to wobbling a pre-groove to record data at an accurate position on an optical disc on which address information is recorded. The present invention also relates to an optical disc, an optical disc recording / reproducing apparatus and a method capable of reproducing.

[0002]

2. Description of the Related Art In order to record data on a disc, it is necessary to record address information so that the data can be recorded at a predetermined position. This address information may be recorded by wobbling.

That is, a track for recording data is preliminarily formed as, for example, a pregroove, and the side wall of this pregroove is wobbled (meandered) in accordance with address information. In this way, the address can be read from the wobbling information, and the data can be recorded / reproduced at the desired position.

[0004]

However, since the wobbling information has a very low density with respect to the recording / reproducing information, the reference of the recording position of the sector becomes rough and the recording position of the sector shifts at every recording. Therefore, the front and rear sectors may interfere with each other. Further, it is necessary to absorb the jitter due to eccentricity, etc., and in order to prevent these, a considerable unrecorded buffer area is required, which is very disadvantageous in terms of data capacity. As a result, the system becomes very redundant, and it is difficult to perform high-density random recording / reproduction.

In order to record and reproduce data at random on a recordable optical disk, in addition to addresses such as track addresses and sector addresses,
PLL that generates a reference clock for recording and reproduction
It is necessary to form a VFO area or the like in which data for drawing in the circuit is recorded. Further, in the case of the method of recording the address and the like in the recorded data, a linking sector in which dummy data is recorded is required before the sector to be recorded for switching from the reproduction state to the recording state.

As described above, in order to be able to actually record data randomly on the optical disc,
Originally, an area in which these addresses and VFOs are recorded must be formed in addition to the area in which data is recorded, but the method proposed hitherto requires a long overhead and a substantial recording capacity of the optical disk is reduced. There was a problem to do.

Further, in a conventional CD-ROM or the like, "f
There is a synchronization signal "ram sync" at regular intervals, and the synchronization processing is performed in units of this synchronization signal. However, if the ROM disk and the RAM disk are made to have the same format by adding the header, the synchronization system will not continue in the recording sector unit due to the header, and there is a problem that the synchronization system processing becomes difficult.

The present invention has been made in view of the above circumstances, and is intended to enable data to be recorded at an accurate position on a disc for recording an address by wobbling.

[0009]

An optical disc according to claim 1 has a plurality of address frames for address information, a synchronization mark is arranged in each address frame, and a carrier frequency is the center of the address mark. It is characterized in that a plurality of synchronization mark areas set to the frequency are formed.

According to another aspect of the optical disc of the present invention, the address information has a plurality of address frames, and each address frame has a plurality of sync marks wobbling the track at a frequency higher than the wobbling frequency according to the address information. It is characterized by being formed.

In the optical disc according to the present invention, a track is divided into a plurality of clusters as a unit for recording or reproducing data, the cluster is divided into a data area and a link area between the data areas, and the data area and the link are formed. It is characterized in that the area is configured in units of data frames each divided by a synchronization signal.

An optical disk recording / reproducing apparatus according to a fifteenth aspect of the invention is a recording / reproducing means for recording / reproducing data on / from an optical disk, a detecting means for detecting a sync mark from a reproduction output of the recording / reproducing means, and a wobbling recording. A reading means for reading the address information, a synchronization mark detected by the detecting means, and a signal generating means for generating a start signal representing the start position of the cluster corresponding to the address information read by the reading means. It is characterized by

An optical disk recording / reproducing method according to a nineteenth aspect of the invention is to detect a sync mark from a reproduction output of the optical disk,
It is characterized in that the address information recorded by wobbling is read, and a start signal indicating the start position of the cluster is generated corresponding to the detected synchronization mark and the read address information.

In the optical disc according to claim 1,
The address information is composed of a plurality of address frames, a plurality of sync mark areas are formed in the address frame, the sync marks are arranged in the sync mark areas, and the carrier frequency is set to the center frequency thereof. It

In the optical disc of the fourth aspect,
The address information has a plurality of address frames, and a plurality of synchronization marks are formed in the address frame by wobbling the track at a frequency higher than the wobbling frequency according to the address information.

In the optical disc of the eighth aspect,
A track is divided into a plurality of clusters as a unit for recording or reproducing data, and the cluster is divided into a data area and a link area between the data areas, and the data area and the link area are each a data frame separated by a sync signal. Composed of units.

In the optical disk recording / reproducing apparatus according to the fifteenth aspect and the optical disk recording / reproducing method according to the nineteenth aspect, the sync mark is detected from the reproduction output of the optical disc. Further, the address information recorded by wobbling is read. A start signal representing the start position of the cluster is generated corresponding to the detected synchronization mark and the read address information.

[0018]

FIG. 1 shows an example of the configuration of an optical disk according to the present invention. As shown in the figure, a pre-groove 2 is spirally formed in advance on a disc (optical disc) 1 from the inner circumference to the outer circumference. of course,
The pre-groove 2 can also be formed concentrically.

As shown in a partially enlarged view of FIG. 1, the pregroove 2 has its left and right side walls wobbled in accordance with address information, and at a predetermined cycle corresponding to a wobbling signal. Meandering One track (one track) has a plurality of wobbling address frames, and each wobbling address frame has a structure as shown in FIG.

As shown in FIG. 2, the wobbling address frame is composed of 60 bits, and the first 4 bits are a synchronization signal (Sync) indicating the start of the wobbling address frame. The next 4 bits are a layer indicating which one of the plurality of recording layers it is.
It has been. The next 20 bits are used as a track address. Further, the next 4 bits are designed to represent a frame number. The remaining 14 bits are used as an error correction code (CRC), and an error detection code excluding a synchronization signal (Sync) and a clock synchronization mark area (Sync mark) described later is recorded. The next 12 bits are used as a clock synchronization mark area (however, actually, as will be described later with reference to FIG. 3, the clock synchronization mark area has a 5-bit cycle and is separately arranged). The last two bits (Reserved) are reserved for future use.

For example, eight wobbling address frames are formed per track, and the rotational angular velocity of the disk is constant (CAV (Constant Angular Velocit).
y)) is recorded.

FIG. 3 shows a clock synchronization mark area and a clock synchronization mark (Fine Clock Mark). Data of 60 bits is recorded in each wobbling address frame, and 1 bit is represented by 7 waves (carrier) of a signal of a predetermined frequency as shown in FIG. Will have 420 waves. Assuming that the optical disk 1 is rotated at 1200 rpm, the frequency of this carrier is 67.2 kHz.

As shown in FIG. 3, in the wobbling address frame shown in FIG. 2, each clock synchronization mark area is 1 with an interval of 4 bits of address information.
It is arranged bit by bit. That is, data is recorded with a cycle of 5 bits. Of the 5 bits, the first 1 bit is a bit for a clock synchronization mark (Fine Clock Mark), and the remaining 4 bits are substantial address data not including a fine clock mark.
The carrier frequency in the clock synchronization mark area is the center frequency of the frequency modulation range, and the carrier frequency in the address data area is a value corresponding to the address data. Therefore, 12 bits are included in one frame.
Fine clock marks and 48 bits (pieces) of address data are recorded, and 96 (= 12 × 8) fine clock marks are recorded in one rotation (one track). .

The address information is biphase-modulated and then frequency-modulated, and the pregroove is wobbled by this frequency-modulated wave. In the clock synchronization mark area, the wobbling frequency of the pre-groove is set to the center frequency of the modulation frequency of the address information.

The period (length) of the clock synchronization mark is the same as that of the CD and the like when the recording / reproducing data modulation method is EF.
In the case of M (Eight To Fourteen Modulation: (8-14) modulation), the length is 6 to 8T. A signal for one cycle (one wavelength) (a signal having a frequency higher than the carrier for wobbling) is superimposed on the carrier as a clock synchronization mark to wobble the track.

FIG. 4 shows a configuration example of a wobbling address generation circuit for generating a wobbling signal for wobbling the pregroove 2. Generation circuit 11
Produces a signal at a frequency of 44.1 kHz. This 4
The frequency of 4.1 kHz is the same frequency as the sampling clock of the audio data of MiniDisc (trademark).

The signal generated by the generating circuit 11 is supplied to the dividing circuit 12, is divided by the value 7, and then the frequency of 6300.
It is supplied to the biphase modulation circuit 13 as a biphase clock signal of Hz. Bi-phase modulation circuit 1
3 also has ADIP (ADd as address data
Less In Pre-groove data is provided.

The bi-phase modulation circuit 13 includes a divider 12
The bi-phase clock supplied from the circuit is bi-phase modulated with ADIP data supplied from a circuit (not shown),
The biphase signal is output to the FM modulation circuit 15.
The FM modulation circuit 15 also generates a signal generated by the generation circuit 11.
A carrier having a frequency of 22.05 kHz obtained by dividing the 4.1 kHz signal by a value of 2 by the divider 14 is input. The FM modulation circuit 15 frequency-modulates the carrier input from the divider 14 with the bi-phase signal input from the bi-phase modulation circuit 13, and outputs the resulting FM signal. The left and right sidewalls of the pre-groove 2 of the disc 1 are formed (wobbled) in correspondence with this FM signal. As described above, the carrier frequency in the clock synchronization mark area is 22.05 kHz.

FIG. 5 and FIG. 6 show the biphase modulation circuit 13
2 shows an example of a bi-phase signal output from. In this example, when the leading bit is a 0,
As shown in, the synchronization pattern is “111010.
00 "is used and the preceding bit is 1, the synchronization pattern is" 00010 "as shown in FIG.
111 ″ is used.

The data bits (Data Bits) are bi-phase modulated and converted into channel bits (Channel Bits). In the embodiment of FIGS. 5 and 6, the data bit “0” is “11” (when the previous bit is “0”) or “00” (when the previous bit is “1”). Converted, the data bit “1” becomes the channel bit “01” (when the previous bit is “1”) or “1”.
Converted to 0 "(when the previous bit is" 0 "). SY
NC is an irregular pattern that does not appear in modulation. “Wave Form” in FIG. 5 is a conversion of channel bits into a pattern of 1,0.

FIG. 7 shows a disk 1 having a pre-groove.
2 shows a configuration example of a recording device for manufacturing the. The wobbling signal generation circuit 21 has the configuration shown in FIG. 4 described above and outputs the FM signal to the synthesis circuit 22. The mark signal generation circuit 23 generates a clock synchronization mark signal at the timing of forming the clock synchronization mark and outputs it to the synthesis circuit 22. Synthesis circuit 22
The FM signal output from the wobbling signal generation circuit 21 and the clock synchronization mark signal output from the mark signal generation circuit 23 are combined and output to the recording circuit 24. The recording circuit 24 controls the optical head 25 in response to the signal supplied from the synthesizing circuit 22 to generate laser light for forming a pre-groove and a synchronization mark on the master 26. The spindle motor 27 rotates the master 26 at a predetermined speed.

That is, the wobbling signal generation circuit 21
The FM signal generated by is combined with the clock synchronization mark signal output from the mark signal generating circuit 23 in the combining circuit 22 and input to the recording circuit 24. Recording circuit 24
Controls the optical head 25 in response to a signal input from the synthesizing circuit 22 to generate laser light. Optical head 25
The generated laser light is applied to the master disk 26 rotated by the spindle motor 27 at a predetermined speed.

The master 26 is developed, a stamper is created from the master 26, and a large number of replica disks 1 are formed from the stamper. As a result, the disk 1 on which the pre-groove 2 having the above-described clock synchronization mark is formed can be obtained.

FIG. 8 shows an example of the structure of an optical disk recording / reproducing apparatus for recording or reproducing data on the disk 1 thus obtained. Spindle motor 3
1 is adapted to rotate the disk 1 at a predetermined speed. The optical head 32 irradiates the disk 1 with laser light, records data on the disk 1, and reproduces data from the reflected light. The recording / reproducing circuit 33 causes the memory 34 to temporarily record the recording data input from a device (not shown), and when the memory 34 stores one cluster of data as a recording unit, reads out this one cluster of data. The signal is output to the optical head 32 after being modulated by a predetermined method. Further, the recording / reproducing circuit 33 includes an optical head 32.
The input data is appropriately demodulated and output to a device (not shown).

The address generating / reading circuit 35 comprises a control circuit 3
An address (not an address recorded as wobbling information) to be recorded in the track (pre-groove 2) is generated in response to the control from 8 and is output to the recording / reproducing circuit 33. The recording / reproducing circuit 33 adds this address to recording data supplied from a device (not shown) and outputs the address to the optical head 32. Further, the optical head 32 separates the address data contained in the reproduced data reproduced from the track of the disk 1, and outputs the address data to the address generation / read circuit 35. Address generation / reading circuit 35
Outputs the read address to the control circuit 38.

Further, the mark detection circuit 36 includes the optical head 3
2 detects the component corresponding to the clock synchronization mark from the RF signal (wobbling signal) reproduced and output by the device 2. The frame address detection circuit 37 reads the address information included in the wobbling signal from the RF signal (wobbling signal) output from the optical head 32, detects the frame address, and supplies it to the cluster counter 46.

The mark period detection circuit 40 determines the periodicity of the detection pulse output when the mark detection circuit 36 detects the clock synchronization mark. That is, since the clock synchronization mark is generated in a constant cycle (every 5 bits), it is determined whether the detection pulse input from the mark detection circuit 36 is a detection pulse generated in this constant cycle.
If the detection pulse is generated in a constant cycle, a pulse synchronized with the detection pulse is generated, and the PLL circuit 41 in the subsequent stage
To the phase comparator 42. Further, the mark cycle detection circuit 40 generates a pseudo pulse at a predetermined timing so that the PLL circuit 41 at the subsequent stage is not locked to an incorrect phase when the detection pulse is not input at a constant cycle.

The PLL circuit 41 includes a phase comparator 42,
Low pass filter 43, voltage controlled oscillator (VCO) 4
4 and a frequency divider 45. Phase comparator 42
Is the input from the mark period detection circuit 40 and the frequency divider 45.
The phase with the input from is compared and the phase error is output. The low-pass filter 43 compensates the phase of the phase error signal output from the phase comparator 42 and outputs it to the VCO 44. The VCO 44 generates a clock having a phase corresponding to the output of the low pass filter 43 and outputs it to the frequency divider 45.
The frequency divider 45 frequency-divides the clock input from the VCO 44 by a predetermined value and outputs the frequency-divided result to the phase comparator 42.

The clock output from the VCO 44 is supplied to each circuit and also to the cluster counter 46. The cluster counter 46 counts the number of clocks output by the VCO 44 with the frame address in the wobbling signal supplied from the frame address detection circuit 37 as a reference, and the counted value is a predetermined value (for one cluster). When the value (corresponding to the length) is reached, a cluster start pulse is generated and output to the control circuit 38.

The sled motor 39 is controlled by the control circuit 38 to move the optical head 32 to a predetermined track position on the disk 1. In addition, the control circuit 38
Controls the spindle motor 31 to rotate the disk 1 at a predetermined speed.

Next, the operation will be described. Here, the operation during data recording will be described. Optical head 3
Reference numeral 2 irradiates the optical disk 1 with laser light and outputs an RF signal (wobbling signal) obtained from the reflected light. The frame address detection circuit 37 reads the frame number (FIG. 2) from this wobbling signal, outputs the read result to the control circuit 38, and also supplies it to the cluster counter 46. The wobbling signal output from the optical head 32 is also input to the mark detection circuit 36, where the clock synchronization mark is detected and supplied to the mark cycle detection circuit 40.

The mark period detection circuit 40 determines the periodicity of the clock synchronization mark (occurs at a rate of once every 5 bits as shown in FIG. 3), generates a predetermined pulse corresponding to the periodicity, and generates the PLL. Output to the circuit 41. PLL circuit 4
The output from 1 is supplied to the cluster counter 46.

The control circuit 38 can detect the position of the reference clock synchronization mark in one round of the track from the frame address supplied from the frame address detection circuit 37 and the structure of the wobbling address frame. Based on this, it becomes possible to access an arbitrary position on the track from the recording clock.

FIG. 9 shows the proposed high density CD-RO.
The example of the sector format of the data recorded in the track of M is shown. As shown in the figure, in each sector, 2 frames in the horizontal direction and 14 frames in the vertical direction,
28 frames are arranged as a whole, and 2 kilobytes (2
With a capacity of 048 bytes, one sector of data area is formed.

The first 2 bytes of one frame are FS
(Frame Sync: synchronization signal), and the following 85 bytes are used as a data area. 20 bytes of the data area at the head of the sector is used as an address area, and a sector address (sector number) and a track address (track number) are recorded therein. Predetermined data such as computer data and video data is recorded in an area following the address area of the data area.

A 4-byte EDC is arranged at the end of the data area of the sector. This is an error detection code for 2048-byte data.

At the right end of the two frames arranged in the horizontal direction, an 8-bit parity C1 and a 14-bit parity C are provided.
2 are arranged. These are error correction codes and are set for 170-byte data of two frames, respectively. C1 series is horizontal (horizontal) in the figure
Is set for two frames of data. On the other hand, the C2 sequence is coded in an interleaved manner with the C1 sequence. That is, it is set for 170 bytes (340 frames) of data from the upper left to the lower right (obliquely).

FIG. 10 shows a configuration example of an ECC block of a cluster. One cluster is composed of an integral multiple of a sector (8 sectors (= 28 frames = 16 kilobytes) in this embodiment). As shown in the figure, the C2 sequence of the error correction code is completed in one cluster.

FIG. 11 shows an example of the structure of the link area. The link area is formed between the clusters. The link area is composed of two frames, and one frame of data is 85 bytes as in the case of the data area. At the head of each frame, a 2-byte FS (Frame Sync: synchronization signal) is arranged.
A 1-byte postamble and a 2-byte postbuffer belong to the previous cluster, and the postamble contains data for adjusting the mark length of the last data and returning the signal polarity. It The post buffer is a buffer area for absorbing jitter due to eccentricity or the like.

From the next 2-byte prebuffer of the postbuffer, it belongs to the next cluster to be recorded. This pre-buffer is a buffer that absorbs the start position of the cluster. The next 16 bytes are AL
It is a PC (Automatic Laser Power Control), and is a recording power setting area in which data for setting the output during recording or reproduction of laser light to a predetermined value is recorded. The next 64 bytes are set as VFO, and the data for pulling in the PLL is recorded. That is, in the PLL circuit 41 shown in FIG. 8, the clock for executing the synchronous pull-in operation is recorded.

38 bytes V after the FS of the next frame
FO is set, and the data for pulling in the PLL circuit with respect to the recording data is recorded. Next to VFO is 4-bit Security Control.

Copy protection information is recorded in the security control. For example, when this copy protection information is recorded in the data area, it is treated as data, and can be freely read or rewritten from the host computer, and the protection function may not be fulfilled. On the other hand, when the copy protection information is recorded in the link area, since the information in the link area is not data, it cannot be accessed from the host computer and the copy protection information is very effective.

The next 8-byte address is
It consists of a 2-byte address mark (AM), a 4-byte track and cluster address (Address), and a 2-byte error detection code (CRC). As the above VFO and address, substantially the same data is recorded twice in order to increase the detection probability of the address. However, the VFO has a length of 38 bytes for the first time and 19 bytes for the second time. And
Finally, 2-byte Sync for data start synchronization is provided. A synchronization signal indicating the start position of the record data is recorded here.

As described above, in this embodiment, the clock synchronization mark area is set to the center frequency of the modulation frequency of the wobbling carrier of the wobbling address information, so that the clock synchronization is not affected and the detection of the wobbling address information is not affected. It is possible to easily detect the mark area and the clock synchronization mark. By forming a plurality of clock synchronization marks on one track, it is possible to accurately reproduce the recording clock from the cycle in which the clock synchronization marks are detected. As a result, the recording / reproducing sector position can be accurately determined, and jitter due to eccentricity or the like can be suppressed. As a result, high density random recording / reproducing is possible. Further, since it is not necessary to increase the buffer between the clusters, higher density recording / reproducing is possible.

Further, by constructing the overhead area in units of data frames, it becomes easy to secure the cycle regardless of the overhead, and recording / reproducing can be performed at random positions. CD-ROM
In a writable disc such as a disk, the format of the data area is made common to that of the high-density CD-ROM for reproduction only, and the frame structure of the link area is made the same as the frame structure of the data, thereby making the synchronization system common. Therefore, it is possible to make the read-only hardware and the optical disk device have the same configuration.

It is also possible to apply this link area to a ROM disk so that the ROM disk and the RAM disk have a common format. In that case, in the ROM disc, it is possible to record information in the post buffer, pre-buffer, and ALPC of the link area. For example, put a VFO and PLL from the previous cluster
Can be made to have continuity. Alternatively, it is possible to insert an address and increase the information probability of the address.

FIG. 12 shows another structural example (format) of the wobbling address frame. As shown in the figure, this wobbling address frame is 48
The first 4 bits are a synchronization signal (Sync) indicating the start of a wobbling address frame. The next 4 bits are a layer indicating which one of the plurality of recording layers. The next 20 bits are used as a track address (track number). The next 4 bits indicate the frame number of the address frame. The remaining 14 bits are used as an error detection code (CRC), and an error detection code for data excluding the synchronization signal (Sync) is recorded. The last two bits (Reserved) are reserved for future use. That is, in this embodiment, the clock synchronization mark area (sync mark area) in FIG. 2 is omitted.

This wobbling address frame is 1
For example, eight address frames per track (one rotation) are recorded on the CAV disk in which the rotational angular velocity of the disk is constant. Therefore, values 0 to 7 are recorded as the frame number of the address frame.

FIG. 13 shows an example of the construction of a wobbling signal generation circuit for generating a wobbling signal for wobbling the pregroove 2 in correspondence with the address frame of the format shown in FIG. The basic configuration is the same as in FIG. 4, but the frequency is different. That is, the generation circuit 11 is 115.2 kHz.
Generate a signal of frequency z. The signal generated by the generation circuit 11 is supplied to the division circuit 12, divided by a value of 7.5, and then supplied to the biphase modulation circuit 13 as a biphase clock signal having a frequency of 15.36 kHz. The bi-phase modulation circuit 13 also has an ADIP (Address I) of the frame format shown in FIG.
n Pre-groove) data is provided.

The bi-phase modulation circuit 13 includes a divider 12
The bi-phase clock supplied from the circuit is bi-phase modulated with ADIP data (address data) supplied from a circuit (not shown), and the bi-phase signal is FM-modulated by the FM modulation circuit 1.
It outputs to 5. The 115.2 kHz signal generated by the generation circuit 11 is also input to the FM modulation circuit 15 by the divider 1.
Frequency 57.6 kHz obtained by dividing value 2 by 4
Is entered. The FM modulation circuit 15 frequency-modulates the carrier input from the divider 14 with the bi-phase signal input from the bi-phase modulation circuit 13, and outputs the resulting frequency-modulated signal.
The left and right side walls of the pregroove 2 of the disk 1 are formed (wobbled) in accordance with the frequency modulation signal.

14 and 15 show examples of the bi-phase signal output from the bi-phase modulation circuit 13. In this embodiment, when the leading bit is 0,
As shown in FIG. 14, “11101000” is used as the synchronization pattern (SYNC), and when the preceding bit is 1, the synchronization pattern has a phase opposite to that shown in FIG. 14 as shown in FIG. "000101011"
Is used. SYNC is a unique pattern that does not appear in modulation and is out of the rule.

Among the data bits (Data Bits) of the address data (ADIP data), "0" is biphase-modulated and is "11" (when the previous channel bit is 0) or "00" (the previous channel). It is converted to Channel Bits (when the bit is 1). Also, “1” is converted to a channel bit of “10” (when the previous channel bit is 0) or “01” (when the previous channel bit is 1). Which of the two patterns is converted depends on the previous code. That is, “Wave For” in FIGS.
“M” (waveform) represents a pattern of 1 and 0 of channel bits, in which 1 is a high-level signal and 0 is a low-level signal, and one of two patterns is used so that this waveform is continuous. Is selected.

The FM modulation circuit 15 is shown in FIG. 14 or FIG.
Corresponding to the bi-phase signal as shown in, the divider 1
The carrier supplied from No. 4 is frequency-modulated as shown in FIG.

That is, when the channel bit data (biphase signal) is 0, the FM modulation circuit 15
In the period corresponding to half the length of one data bit, 3.5
Outputs the wave carrier. This 3.5 wave carrier is
It starts with a positive half wave or a negative half wave.

On the other hand, when the channel bit data (bi-phase signal) is 1, four wave carriers are output during the period corresponding to half the length of one data bit. These four-wave carriers are also carriers that start with a positive half-wave or carriers that start with a negative half-wave.

Therefore, when the channel data bit 00 is input to the FM modulation circuit 15 in correspondence with the data 0,
During the period corresponding to the length of the data bit, 7 waves (= 3.5
+3.5). When the channel data bit 11 is input, eight (= 4 + 4) frequency modulated waves are output. When channel data bit 10 or 01 is input corresponding to data 1, 7.5.
A frequency-modulated wave of a wave (= 4 + 3.5 = 3.5 + 4) is output.

57.6k input to the FM modulation circuit 15
The carrier of 7.5 Hz corresponds to 7.5 waves, and the FM modulation circuit 15 converts the carrier of 7.5 waves or ± 6.67% (= 0.5 / 7) in accordance with the data. .5) Generate seven or eight shifted frequency modulated waves.

As described above, the carrier starting from the positive half wave and the carrier starting from the negative half wave corresponding to the channel data 0 and the channel data 1, respectively, are selected to be continuous with the previous signal.

FIG. 17 shows an example of the frequency modulation wave output from the FM modulation circuit 15 in this way. In this example, the first data bit is 0 and its channel data bit is 00.
For the first channel data bit 0, a 3.5 wave carrier starting with a positive half wave from the starting point is selected.
As a result, the end point of the carrier ends with a positive half wave. Therefore, for the next channel data bit 0, 3.5 waves starting from the negative half wave are selected, and data bit 0
On the other hand, there are a total of 7 frequency-modulated waves.

This data bit 0 is followed by data bit 1 (channel bit 10). 2. of channel data bit 0 corresponding to the previous data bit 0;
Since five waves end with a negative half wave, data bit 1
Are selected as carriers of four waves of the first channel data bit 1 corresponding to the first half-wave. Since the four waves of channel data bit 1 end with a negative half wave, the four waves of the next channel data bit 0 are selected starting with the positive half wave.

Similarly, 7.5 waves, 8 waves, corresponding to data bit 1 (channel data bit 10), data bit 0 (channel data bit 11) and data bit 0 (channel data bit 00), Seven wave carriers are formed and output so as to be continuous at the boundary portion (start point and end point) of the data bit.

As shown in FIG. 17, in this embodiment, the channel bit length is ½ of the carrier wavelength in the case of 7-wave, 7.5-wave, or 8-wave carrier. It is supposed to be an integral multiple of. That is, the length of the channel bit is set to seven times the wavelength of half the wavelength of the seven carriers (frequency modulated waves), and
The length is set to eight times as long as の of the eight carriers (frequency modulated waves). And the length of the channel bit is
It is set to 7 times (when the channel bit is 0) or 8 times (when the channel bit is 1) half of the wavelength of the 7.5 wave carrier.

Further, in this embodiment, the boundary portion (end point or start point) of the bi-phase modulated channel bits is the zero cross point of the frequency modulated wave. As a result, the phase of the address data (channel bit data) matches the phase of the frequency-modulated wave, the boundary between the bits can be easily identified, and erroneous detection of the address data bits can be prevented. Accurate reproduction becomes easy.

Further, in this embodiment, the boundary portion (start point and end point) of the data bit corresponds to the edge (zero cross point) of the frequency modulated wave. As a result, it is possible to generate a clock with the edge of the frequency modulation wave as a reference. However, in this embodiment, as will be described later with reference to FIG. 18, the clock is generated based on the clock synchronization mark.

Such a disc 1 can also be manufactured by the recording apparatus having the configuration shown in FIG.

However, in the case of this embodiment, FIG.
As shown in (d) to (d), the channel bit data is 0.
0 (data 0), 11 (data 0), 10 (data 1)
Alternatively, when it is 01 (data 1), at the zero crossing point of the carrier at the center of each data (channel bit switching point), the modulation frequency (5
Clock sync marks with a frequency higher than 7.6 kHz) are synthesized. The clock synchronization mark is recorded for each data bit or for each predetermined number of data bits (for example, for every four data bits which is one bit smaller than that shown in FIG. 3 (at an interval of three data bits)). . As a result, as shown in FIG. 12, the clock synchronization mark area (12-bit sync mark area) shown in FIG. 2 becomes unnecessary.

As described above, by inserting the clock synchronization mark at the zero-cross point of the wobbling frequency modulation wave corresponding to the center of the address data bit (switching point of the channel data bit), the fluctuation in the amplitude of the clock synchronization mark is reduced. The detection becomes easy.

That is, in the FM modulation circuit 15, when the channel data bit is 0, frequency modulation is performed so as to shift the frequency by, for example, −5% from the center frequency, and when the channel data bit is 1, + 5% from the center frequency. When frequency modulation is performed so that it shifts,
The boundary between the data bit or the channel data bit and the zero cross point of the frequency modulation wave do not match, and the channel data bit (or data bit) is easily erroneously detected. Further, the insertion position of the clock synchronization mark is not always a zero cross point, but is superimposed on a point having a predetermined amplitude value of the frequency modulation wave. As a result, the level of the clock synchronization mark increases or decreases by the amplitude value, and it becomes difficult to detect the level. According to this embodiment, the clock synchronization mark is always arranged at the zero-cross position of the frequency-modulated wave, so that its detection (discrimination from the frequency-modulated wave) becomes easy.

FIG. 19 shows an example of the structure of an optical disk recording / reproducing apparatus for recording or reproducing data on the disk 1 thus obtained. The basic structure is the same as that shown in FIG. 8, but a ROM 47 is further added in this embodiment.

In the ROM 47, a table that defines the correspondence between the track numbers in the address frame (FIG. 12) and the zones that divide the data recording area of the disk 1,
A table defining the relationship between zones and the bands to which the zones correspond is stored as necessary.

That is, as shown in FIG. 20, the control circuit 38 divides the disk 1 into a plurality of zones (in this embodiment, m + 2 zones from the 0th zone to the m + 1th zone) to record data. Or play. Now, a data frame per track in the 0th zone (this data frame is different from the address frame described with reference to FIGS. 2 and 12 is different from the data frame described with reference to FIGS. 10 and 11). N is the number of blocks)
In the following first zone, the number of data frames per track is n + 8. Similarly, the number of data frames in the outermost zone is increased by 8 as compared with the adjacent inner zone, and n + 8 × (m + 1) data frames are added in the outermost m + 1th zone. Becomes a number.

From the radial position where the capacity of n + 8 frames is obtained with the same linear density as the innermost peripheral linear density of the 0th zone,
Switch to the zone. Similarly, in the m-th zone, n + 8 at the same linear density as the innermost peripheral linear density of the zero-th zone.
The zone from the radial position where the capacity of the × m frame is obtained is set as the m-th zone.

For example, the radius of the disk 1 having a diameter of 120 mm is a recording / reproducing area in the range of 24 mm to 58 mm,
Track pitch 0.87μm, linear density 0.39μ
Assuming m / bit, the recording / reproducing area is divided into 92 zones from the 0th zone to the 91st zone, as shown in FIG. In the 0th zone with a disc radius of 24 mm, there are 520 frames per track (one rotation), and as the zone is incremented by 1, 1
Eight frames are increased per track. The detailed parameters of each zone are shown in FIGS.

As will be described later, in this embodiment, one sector is composed of 24 frames (data frames), so the number of frames incremented for each zone (= 8) constitutes this one sector. Number of frames (=
24) It means that it is set to a smaller value. This makes it possible to form many zones in finer units, and to increase the capacity of the disk 1. This method is called Zone CLD (Zoned Constant Linea).
r Dencity).

22 to 25, the data in each column is the zone number, radius, number of frames per track, number of tracks per zone, number of recording / reproducing units (blocks) per zone (cluster). Number), the shortest linear density in the zone, the capacity of the zone, the first rotational speed of the zone, the minimum linear velocity of the zone at the first rotational speed, the maximum linear velocity of the zone at the first rotational speed. Speed, the second rotational speed of the zone, the minimum linear velocity of the zone at the second rotational speed, or the second
The respective maximum linear velocities of the zones at the rotation speeds of are shown. The first rotation speed represents the rotation speed of CAV per minute when the data transfer rate is 11.08 Mbps. The second rotation speed is 4 Zoned divided into 4 rotation bands when the bands are configured so that the change in linear velocity in each band is the same in each band.
Represents the number of revolutions per minute during CLD.

In this embodiment, the number of tracks in each zone is fixed at 424, and the number of tracks is one recording / reproducing unit frame number (ECC block (cluster) frame number) (see FIG. 30). And will be described later).

In this embodiment, the number of tracks in each zone is set to one time the number of data frames (424 frames) forming a recording / reproducing unit, but it can be set to an integral multiple. As a result, no extra data frames are generated, and an integer number of recording / reproducing units (blocks) are arranged in each zone, so that zoning efficiency can be improved. As a result, the zone CLV is larger than the zone CAV and smaller than the zone CLV.
Capacity can be obtained.

Further, by performing the zoning close to CLV in this way, the change of the clock frequency in the zone and the next zone becomes small, and the zone where the clock frequency changes even when the clock is reproduced by the reproducing device dedicated to the CLV. It becomes possible to extract the clock even between
Reproduction can be performed continuously between zones.

Next, the operation of the embodiment shown in FIG. 19 will be described. Here, the operation during data recording will be described. The optical head 32 irradiates the optical disc 1 with laser light,
RF signal (wobbling signal) obtained from the reflected light
Is output. The frame address detection circuit 37 receives the frame address (frame number) from the wobbling signal.
Is read and the read result is output to the control circuit 38 and also supplied to the cluster counter 46. The wobbling signal is also input to the mark detection circuit 36, where the clock synchronization mark is detected and the detection result is supplied to the mark period detection circuit 40.

The mark period detection circuit 40 determines the periodicity of the clock synchronization mark, generates a predetermined pulse corresponding to it, and outputs it to the PLL circuit 41. PLL circuit 41
Generates a clock (recording clock) synchronized with this pulse and supplies it to the cluster counter 46.

The control circuit 38 can detect the position of the reference clock synchronization mark in one track (one rotation) from the frame address (frame number) supplied from the frame address detection circuit 37. For example, it is possible to access an arbitrary position on a track (an arbitrary position during one rotation) based on the count value of a recording clock with reference to a clock synchronization mark detected first at a frame (address frame) of frame number 0. It becomes possible.

As described above, when an arbitrary position on the track is accessed, it is further determined which zone the access point belongs to and the VCO 44 is caused to generate a clock having a frequency corresponding to the zone. There is a need. Therefore, the control circuit 38 further executes a clock switching process as shown in the flowchart of FIG.

That is, first, in step S1,
The control circuit 38 reads the track number from the frame address of the access point output by the frame address detection circuit 37. Then, in step S2, the zone corresponding to the track number read in step S1 is
Read from a table stored in the ROM 47. As described above, the table of the ROM 47 stores in advance which zone, for example, the 0th zone to the 91st zone, the track of each number belongs to.

Therefore, in step S3, it is determined whether or not the track number just read is a new zone different from the zone that has been accessed until then. If it is determined that the zone is a new zone, the process proceeds to step S4, where the control circuit 38 controls the frequency divider 45 to set the frequency division ratio corresponding to the new zone. As a result, the recording clock having a different frequency for each zone
It will be output from O44.

If it is determined in step S3 that the current zone is not a new zone, the process of step S4 is skipped. That is,
The frequency division ratio of the frequency divider 45 is not changed and is kept as it is.

Next, the format of recording data will be described. In this embodiment, one cluster is 32k
It is composed of bytes, and data is recorded in units of this cluster. This cluster is structured as follows.

That is, 2 kbytes (2048 bytes)
Data is extracted as data for one sector, and 16 bytes of overhead is added to this data as shown in FIG. This overhead includes a sector address (an address generated or read by the address generating / reading circuit 35 in FIG. 19) and an error detection code for error detection.

This total of 2064 (= 2048 + 16)
As shown in FIG. 28, the byte data is 12 × 172
(= 2064) bytes of data. Then, 16 pieces of data for one sector are collected and 192 (= 12
X16) x 172 bytes of data. This 192
A 10-byte inner code (PI) and a 16-byte outer code (PO) are added to the × 172-byte data as parity for each byte in the horizontal and vertical directions.

Further, in this way, 208 (= 192
Out of the data blocked into +16) × 182 (= 172 + 10) bytes, the 16 × 182-byte outer code (PO) is divided into 16 1 × 182-byte data, and as shown in FIG. They are added one by one under the 16 sector data of numbers 0 to 15 of 12 × 182 bytes and are interleaved. And 13 (= 1
Data of (2 + 1) × 182 bytes is data of one sector.

Further, the 208 × 182-byte data shown in FIG. 29 is vertically divided into two, as shown in FIG. 30, and one frame becomes 91-byte data.
The data is two frames. And this 208 × 2
2 × 4 frame link data (link area data) is added to the beginning of the frame data (more precisely, as described later with reference to FIG. 31, a part of the data for 8 frames is Recorded at the beginning of the cluster, the rest at the end of the cluster). At the beginning of the 91-byte frame data, a 2-byte frame synchronization signal (FS) is further added. As a result, as shown in FIG. 30, one frame of data becomes data of 93 bytes in total, and becomes data of a block of 212 (= 208 + 4) × (93 × 2) bytes (424 frames) in total. This is data for one cluster (block as a unit of recording). The size of the real data portion excluding the overhead portion is 32 kbytes (= 2048 × 16/1024)
k bytes).

That is, in this embodiment, one cluster is composed of 16 sectors and one sector is composed of 24 frames.

Since such data is recorded on the disc 1 in units of clusters, link areas are arranged between the clusters as shown in FIG.

As shown in FIG. 31, the link area (Link
ing Frame) consists of 8 data frames and is inserted between 32 kbyte data blocks. Each cluster is a link area before slice / PLL data or frame synchronization signals SY1 to SY7, which is a link area in front of a data block of 32 kbytes, a data block of 32 kbytes, and a link area behind a data block of 32 kbytes. It consists of a postamble and a postguard.

Slice is data for setting a time constant for binarizing the reproduction data, and PLL is
This is data for reproducing a clock. The frame synchronization signals (frame syncs) SY1 to SY7 are added by selecting any one of the states 1 to 4 as described later with reference to FIG.

Data for adjusting the mark length of the last data and returning the signal polarity is recorded in the postamble. The post guard is an area that absorbs recording jitter generated according to the eccentricity of the disc, the recording sensitivity of the disc, and the like. Further, even when the data recording start position is changed as described later, the post guard prevents the data from interfering with the link area to be recorded next. Note that the postguard is recorded when there is no jitter, and when the DPS (Data Position Shift) described later is 0 bytes, it is overlapped with the next data by 8 bytes.

The synchronizing signal (sync) is 4-byte data and is a signal for synchronizing. The last 4 bytes of the link area are reserved for future use.

Each cluster has a start point (Star
Recording of information is started from t Point), and the recording is ended when the start point exceeds 8 bytes (overlap). Further, at the time of recording, the recording / reproducing circuit 33
Randomly selects any value from 0 to 64 bytes as the DPS, and changes the recording positions of the link area data and the 32 kbyte block data in accordance with the selected DPS value.

As shown enlarged in FIG. 31, for example, D
When 0 bytes are selected as PS, 14 bytes of link data are added before the first frame synchronization signal SY2 in the forward link area, and after the last frame synchronization signal SY7 in the backward link area. , 85 bytes of link data are added.

When 32 bytes are selected as the DPS, the first frame synchronization signal S in the front link area is selected.
Before Y2, link data of 46 bytes is added,
After the last frame synchronization signal SY7 in the rear link area, link data of 53 bytes is added.

Further, when 64 bytes are selected as the DPS, the first frame synchronization signal S in the front link area is selected.
Before Y2, 78 bytes of link data are added,
After the last frame synchronization signal SY7 in the rear link area, link data of 21 bytes is added.

As described above, the recording position of the link data and the 32 kbyte data block changes depending on the value of the DPS selected by the recording / reproducing circuit 33.
Therefore, for example, when recording information on a phase change disc or the like, it is possible to prevent the same data (for example, a frame synchronization signal) from being repeatedly recorded on the same portion of the disc. In this case, since the start point is fixed, the recording timing can be generated in the same manner as in the related art.

FIG. 32 shows respective frames when the disc is a ROM disc (playback-only disc) or a RAM disc (rewritable disc),
The structure of a frame synchronization signal is shown. In the ROM disk, one sector is composed of 13 row data, that is, 26 frames, and frame synchronization signals SY0 to SY7 are added to the beginning of each frame.

In the case of a RAM disk, after 13 rows of data, that is, 26 frames of data,
A link area of 8 frames is added, and subsequently,
26 frames of data are added. In addition, RAM
Frame sync signal in the data area of the disc and ROM
The structure (arrangement) of the frame synchronization signals in the data area of the disc is the same. Further, the frame sync signal of the link area of the RAM disk has the same configuration (arrangement) as the last part of the frame sync signal of the data area. That is, SY1 to SY4 and SY7 of the link area have the same pattern as the 10th to 13th rows of the data area. With such a configuration, it is possible to reproduce the RAM disk even in the reproduction device dedicated to the ROM disk.

That is, in the reproducing apparatus dedicated to the ROM disk, the eight frame synchronization signals SY1, SY7, stored in the 10th to 13th rows of the data block are stored.
When SY2, SY7, SY3, SY7, SY4, and SY7 are detected, it is recognized that the next data is the head of the data block. Therefore, these eight frame synchronization signals are stored in the link area. By storing the data, the head of the data area following the link area can be recognized by the playback device.

FIG. 33 shows an example of the frame synchronization signals SY0 to SY7 shown in FIG. The frame synchronization signal is 2-byte data. In this embodiment, since the data after conversion into channel bit data is shown, the data length of each frame synchronization signal is 32 bytes.
Bits (4 bytes). For example, SY0 has four types of state 1 to state 4, and when added to 91-byte frame data (see FIG. 20), data of a state that minimizes the DSV (Digital Sum Value). Is selected and added as a frame synchronization signal.

FIG. 34 shows another structural example of the recording / reproducing apparatus. In this embodiment, the track address detection circuit 48 detects the track address (track number) from the wobbling signal output from the optical head 32 and outputs it to the control circuit 38.

Further, the address generating / reading circuit 35 is
The frame sync signal FS (frame sync) in the data is detected, and the detection result is output to the frame sync (FS) counter 49. The FS counter 49 counts the FS detection pulses output from the address generating / reading circuit 35 and outputs the count value to the control circuit 38. The detection signal of the mark detection circuit 36 is also supplied to the control circuit 38.

The other structure is the same as that shown in FIG.

When the control circuit 38 acquires the point to be accessed by the sector number, it performs the process of replacing the sector number with the track number and the data frame number on the track. That is, in the ROM 47, for example, as shown in FIG. 35, the sector number, zone number, ECC
A table representing a correspondence relationship with a block number, the number of frames per zone, a track number, the number of frames per track, etc. is stored. The control circuit 38 refers to this table to read the track number corresponding to the designated sector number and the number of data frames in the track. Then, the control circuit 38 reads the track number from the output of the track address detection circuit 48.

That is, the track address detection circuit 48
Detects the track address (track number) from the wobbling signal output from the optical head 32. As described with reference to FIG. 12, the track address (track number) is recorded in the 48-bit wobbling address frame. Track address detection circuit 48
Detects this track number and outputs it to the control circuit 38.

When the track address detecting circuit 48 detects a desired track number, the control circuit 38 next detects the reference position of the track.

That is, as shown in FIG. 36, on the disc 1, track numbers are recorded as wobbling information, and a clock synchronization mark is recorded in an address frame of each track at a 4-bit cycle. The control circuit 38 is inserted into the first bit of the 48 bits of the first address frame (the track of track number 0 in the embodiment of FIG. 36) of a predetermined track (address frame of track number 0). The existing clock synchronization mark is detected as the reference clock synchronization mark.

Further, the control circuit 38 resets the count value of the FS counter 49 when one reference clock synchronization mark is detected for one track.
After that, the FS counter 49 counts the frame synchronization signal when it is detected. When the count value of the FS counter 49 reaches the value corresponding to the sector number to be searched, that sector is detected as the sector to be searched.

Then, when the recording of a predetermined sector is started, the control circuit 38 sets the recording start position of the recording of the sector to (0 to 2) ± 4 bytes from the zero cross timing of the reference clock synchronization mark. It is controlled to be within the range. This makes it possible to access tracks and data frames.

The length (number of bytes) of each area in the above embodiment is one example, and a predetermined value can be set as appropriate.

[0126]

As described above, according to the optical disc of the first aspect, a plurality of synchronization mark areas in which the carrier frequency is set to the center frequency are formed in each address frame, and synchronization is performed there. Since the marks are arranged, it is possible to reliably detect the synchronization mark without being influenced by the carrier. Then, it becomes possible to record or reproduce data at an accurate position with reference to the synchronization mark.

According to the optical disc of the fourth aspect, since a plurality of synchronization marks are formed in the address frame at a frequency higher than the wobbling frequency according to the address information, any position can be accessed with high accuracy. It becomes possible.

According to the optical disc of the eighth aspect, the data area and the link area are configured in the unit of data frame separated by the sync signal.
It is possible to secure stable synchronization regardless of overhead.

According to the optical disc recording / reproducing apparatus of the fifteenth aspect and the optical disc recording / reproducing method of the nineteenth aspect, a start signal indicating the start position of the cluster is generated corresponding to the synchronization mark and the address information. Therefore, the position of the cluster can be determined with high accuracy, and random recording and reproduction can be performed with high accuracy.

[Brief description of the drawings]

FIG. 1 is a diagram illustrating a state where an optical disk of the present invention is wobbled.

FIG. 2 is a diagram showing a configuration example of a wobbling address frame.

FIG. 3 is a diagram showing a clock synchronization mark area and a clock synchronization mark.

FIG. 4 is a diagram showing a configuration example of a wobbling address generation circuit.

5 is a diagram showing an example of a biphase signal output from a biphase modulation circuit 13 in FIG.

6 is a diagram showing another example of a biphase signal output from the biphase modulation circuit 13 of FIG.

FIG. 7 is a block diagram showing a configuration example of a recording device for manufacturing a disc 1 having a pre-groove.

FIG. 8 is a block diagram showing a configuration example of an optical disc recording / reproducing apparatus of the present invention.

FIG. 9 is a diagram showing an example of a sector format of a proposed high density CD-ROM.

FIG. 10 is a diagram showing a configuration example of an ECC block of a cluster.

FIG. 11 is a diagram showing a configuration example of a link area.

FIG. 12 is a diagram showing another configuration example of a wobbling address frame.

FIG. 13 is a diagram showing another configuration example of the wobbling signal generation circuit.

14 is a diagram showing an example of a bi-phase signal output from the bi-phase modulation circuit 13 of FIG.

15 is a diagram showing another example of a biphase signal output from the biphase modulation circuit 13 of FIG.

16 is a diagram illustrating frequency modulation performed by the FM modulation circuit 15 of FIG.

17 is a diagram showing a frequency-modulated wave output from the FM modulator circuit 15 of FIG.

18 is a diagram for explaining the operation of the synthesizing circuit 22 of FIG.

FIG. 19 is a block diagram showing another configuration example of the optical disc recording / reproducing apparatus of the present invention.

FIG. 20 is a diagram illustrating zones in a disc.

FIG. 21 is a diagram illustrating a specific example of zones in a disc.

FIG. 22 is a diagram illustrating parameters of each zone.

FIG. 23 is a diagram illustrating parameters of each zone.

FIG. 24 is a diagram illustrating parameters of each zone.

FIG. 25 is a diagram illustrating parameters of each zone.

FIG. 26 is a flowchart illustrating a clock switching process in the embodiment of FIG.

FIG. 27 is a diagram illustrating a format of data for one sector.

[Fig. 28] Fig. 28 is a diagram illustrating the configuration of 32 kbytes of data.

29 is a diagram illustrating a state in which the outer code in FIG. 28 is interleaved.

[Fig. 30] Fig. 30 is a diagram for describing a data structure of a 32-kbyte block.

FIG. 31 is a diagram showing a configuration example of a link area.

[Fig. 32] Fig. 32 is a diagram illustrating a synchronization signal of a ROM disk and a RAM disk.

FIG. 33 is a diagram explaining a pattern of a synchronization signal.

FIG. 34 is a block diagram showing still another configuration example of the optical disc recording / reproducing apparatus of the present invention.

35 is a diagram showing an example of a table stored in a ROM 47 in FIG.

FIG. 36 is a diagram for explaining the operation of the embodiment in FIG. 34.

[Explanation of symbols]

1 optical disk, 2 pre-groove, 11 generation circuit, 12, 14 divider, 13 bi-phase modulation circuit, 15 FM modulation circuit, 21 wobbling signal generation circuit, 22 synthesis circuit, 23 mark signal generation circuit, 24 recording circuit, 25 Optical head, 26
Master, 27 spindle motor, 31 spindle motor, 32 optical head, 33 recording / reproducing circuit, 3
4 memories, 35 address generation and reading circuit, 36 mark detection circuit, 37 frame address detection circuit,
38 control circuit, 39 thread motor, 40 mark period detection circuit, 41 PLL circuit, 42 phase comparator, 43 LPF, 44 VCO, 45 frequency divider, 46 cluster counter, 47 ROM, 48
Track address detection circuit, 49 FS counter

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Yoichiro Sako 6-735 Kitashinagawa, Shinagawa-ku, Tokyo Sony Corporation

Claims (21)

[Claims] 1. An optical disc in which a track for recording data is formed in advance and the track is wobbled with a signal obtained by frequency-modulating a carrier having a predetermined frequency corresponding to the address information. A plurality of address frames are provided, and a synchronization mark is arranged in each of the address frames, and a plurality of synchronization mark areas in which the frequency of the carrier is set to the center frequency thereof are formed. Optical disc. 2. The address information includes at least data corresponding to a sync signal, data corresponding to a track address, data corresponding to an address frame address, and data corresponding to a code for error detection. The optical disc according to claim 1, wherein the optical disc is recorded. 3. The optical disc according to claim 1, wherein the length of the synchronization mark area is at least one bit of the address information as a unit. 4. An optical disc in which a track for recording data is formed in advance and the track is wobbled with a signal obtained by frequency-modulating a carrier of a predetermined frequency corresponding to the address information. A plurality of address frames, each of the address frames has a plurality of synchronization marks,
An optical disc formed by wobbling the track at a frequency higher than the wobbling frequency according to the address information. 5. The address information includes at least data corresponding to a sync signal, data corresponding to a track address, data corresponding to an address frame address, and data corresponding to a code for error detection. The optical disc according to claim 4, wherein the optical disc is read. 6. The optical disc according to claim 4, wherein the sync mark is formed in a plurality of sync mark areas provided in the address frame. 7. The optical disc according to claim 4, wherein the length of the synchronization mark area is at least one bit of the address information as a unit. 8. An optical disc for irradiating light to record data on a track and reproducing the data recorded on the track, wherein the track is divided into a plurality of clusters as a unit for recording or reproducing the data. An optical disc, wherein the cluster is divided into a data area and a link area between the data areas, and the data area and the link area are each configured by a data frame divided by a synchronization signal. 9. In the data area, at least a section where data is recorded, a section where data for error correction is recorded, and a section where data for error detection are recorded are formed. The optical disc according to claim 8, which is characterized in that. 10. The optical disk according to claim 8, wherein the section in which error correction data is recorded is composed of blocks of two systems. 11. The optical disc according to claim 8, wherein the cluster is composed of a plurality of sectors, and the data length of the cluster is an integral multiple of the length of the sector. 12. The optical disc according to claim 8, wherein at least a section in which data corresponding to security information is recorded is formed in the link area. 13. The link area includes at least one data frame, and the link area includes at least a section for absorbing jitter and a section for absorbing a start position of the cluster. , A section in which the sync signal pull-in data is recorded, a section in which data indicating an address position is recorded, a section in which the track and cluster addresses are recorded, and an section in which error detection data is recorded The optical disc according to claim 8, wherein a section in which data corresponding to security information is recorded is formed. 14. The optical disk according to claim 13, wherein predetermined data is recorded in the section for absorbing the jitter of the link area and the section for absorbing the start position of the cluster. . 15. A track for recording data is formed in advance, the track is wobbled corresponding to address information, and the address information has a plurality of address frames, and each address frame has a plurality of address frames. , An optical disc recording / reproducing apparatus for recording / reproducing data on / from an optical disc in which a plurality of synchronization marks are arranged, and data is recorded in clusters on the track. Recording / reproducing means for recording or reproducing, detecting means for detecting the synchronization mark from the reproduction output of the recording / reproducing means, reading means for reading the address information recorded by the wobbling, and detecting means for detecting the synchronizing information. Before being read by the synchronization mark and the reading means In response to address information, the optical disk recording and reproducing apparatus characterized by comprising a signal generating means for generating a start signal indicating the start position of the cluster. 16. A clock generation unit that generates a clock corresponding to the synchronization mark detected by the detection unit, and the clock generated by the clock generation unit based on the address information read by the reading unit. 16. The optical disc recording / reproducing apparatus according to claim 15, further comprising a counting unit that counts clocks. 17. The control means further comprises a control means for locating the sync mark detected first in one turn of the track among the sync marks detected by the detection means as a reference position in one turn of the track. The optical disc recording / reproducing apparatus according to claim 15. 18. The optical disk recording according to claim 15, wherein the cluster is composed of a plurality of data frames, and further comprises a control unit for controlling access in units of the tracks and the data frames. Playback device. 19. A track for recording data is formed in advance, said track is wobbled in correspondence with address information, said address information has a plurality of address frames, and each said address frame comprises: In an optical disc recording / reproducing method for recording or reproducing data on or from an optical disc in which a plurality of synchronization marks are arranged and data is recorded in clusters as clusters, the synchronization marks are reproduced from the optical disc. Detecting and reading the address information recorded by the wobbling, and generating a start signal indicating a start position of the cluster in correspondence with the detected synchronization mark and the read address information. Optical disc recording and reproducing method. 20. The optical disc according to claim 19, wherein among the detected synchronization marks, the synchronization mark detected first in one turn of the track is set as a reference position of one turn of the track. Recording and playback method. 21. The optical disc recording / reproducing method according to claim 19, wherein the cluster is composed of a plurality of data frames, and access control is performed in units of the track and the data frame.