JP4193800B2 - disk - Google Patents

Description

  The present invention relates to a disk, and more particularly to a disk that facilitates address detection and can record or reproduce data at a higher density.

  In order to record data on the disc, it is necessary to record address information in advance so that the data can be recorded at a predetermined position. This address information may be recorded by wobbling the pregroove with a frequency-modulated wave that is frequency-modulated with the address information.

  This is done in MD (Mini Disc) (trademark), CDR (Compact Disc capable of recording) (CD), and the like.

  That is, in these discs, data recording tracks are formed in advance as pregrooves, and the side walls of the pregrooves are wobbled (meandered) in accordance with address information. In this way, the address can be read from the wobbling information (address information), and the data can be recorded at a desired position.

  By the way, conventionally, since the phase of the wobbling information (address data) and the frequency modulation wave does not exactly match, it is difficult to identify the boundary between the bits of the address data, and the address data may be erroneously detected. .

  Also, since wobbling information has a very low density with respect to recording / reproducing information, if data is recorded in a predetermined sector with reference to this wobbling information, the recording position of the sector shifts at every recording. As a result, it may interfere with the preceding and following sectors. Also, in order to absorb jitter due to eccentricity or the like, it is necessary to form a buffer area in which data is not substantially recorded between sectors. This buffer area must be enlarged. As a result, the area in which data cannot be recorded substantially increases, and as a result, the recording capacity of the disc decreases. As a result, there is a problem that the system becomes very redundant and it is difficult to perform random recording and reproduction at high density.

  Therefore, in order to increase the capacity of the disk as much as possible, it is conceivable to use a CLV (Constant Linear Velocity) disk with a constant linear velocity instead of a CAV (Constant Angular Velocity) disk with a constant angular velocity. However, the CLV disk is difficult to access quickly compared to the CAV disk.

  Therefore, a zone CAV disk is known as an intermediate disk between the CAV disk and the CLV disk. In this zone CAV disc, the data recording area of the disc is divided into a plurality of zones. The disk is rotated so that the angular velocity is constant, but in each zone, the zone on the outer peripheral side has more sectors per track (one rotation) than the zone on the inner peripheral side. Has been made. As a result, the recording density can be improved as compared with the CAV disk, and quicker access is possible than in the case of the CLV disk.

  However, with the recent increase in data density, there is a tendency to increase the amount of codes for correcting data errors. As a result, the above-described zone CAV disk also has a problem that it is difficult to ensure a sufficient capacity.

  The present invention has been made in view of such a situation, and makes it easy to detect a clock and to record and reproduce data at a higher density.

In the disk of the present invention, data bits representing address information have a first carrier having a wavelength of 3.5 in a predetermined period, and four wavelengths having a half wavelength greater than that of the first carrier in the predetermined period. And a second carrier .

Each of the first and second carriers can have a carrier starting from a positive half wave and a carrier starting from a negative half wave, and the phase of the frequency-modulated wave is at the boundary with the immediately preceding data bit. To match, when the previous data bit ends with a positive half-wave, the carrier starting from the negative half-wave is selected, and when the previous data bit ends with a negative half-wave, the positive half-wave Carriers starting from can be selected.

In the disc of the present invention, data bits representing address information have a first carrier having a wavelength of 3.5 wavelengths in a predetermined period, and four wavelengths having a half wavelength greater than that of the first carrier in the predetermined period. And a second carrier .

  According to the present invention, since the phase of the address data (channel bit data) and the frequency modulated wave coincide with each other, the boundary between the bits can be easily identified (the frequency modulated wave can be easily detected), and the address data bit can be erroneously detected. Detection can be prevented, and as a result, accurate reproduction of address information is facilitated, and a clock can be accurately generated with reference to the edge of the frequency modulation wave.

  FIG. 1 shows a configuration example of an optical disc to which the disc of the present invention is applied. As shown in the figure, a pregroove 2 is formed in advance in a spiral shape on the disk (optical disk) 1 from the inner periphery to the outer periphery. Of course, the pregroove 2 can also be formed concentrically.

  Further, as shown in FIG. 1 in which a part of the pregroove 2 is enlarged, the left and right side walls are wobbled corresponding to the address information and meandering corresponding to the frequency modulation wave. One track has a plurality of wobbling address frames.

  FIG. 2 shows the configuration (format) of the wobbling address frame. As shown in the figure, the wobbling address frame is composed of 48 bits, and the first 4 bits are a synchronization signal (Sync) indicating the start of the wobbling address frame. The next 4 bits are a layer (Layer) that indicates which of a plurality of recording layers. The next 20 bits are used as a track address (track number). Further, the next 4 bits represent the frame number of the address frame. The subsequent 14 bits are used as an error correction code (CRC), and an error correction code excluding the synchronization signal (Sync) is recorded. The last 2 bits (Reserved) are reserved for the future.

  The wobbling address frame is recorded in a CAV disk shape in which the disk rotation angular velocity is constant, for example, for 8 frames per track (1 rotation). Therefore, for example, values of 0 to 7 are recorded as the frame numbers in FIG.

  FIG. 3 shows a configuration example of a wobbling signal generation circuit that generates a wobbling signal for wobbling the pregroove 2 corresponding to the address frame having the format shown in FIG. The generation circuit 11 generates a signal having a frequency of 115.2 kHz. The signal generated by the generation circuit 11 is supplied to the division circuit 12, divided by the value 7.5, and then supplied to the biphase modulation circuit 13 as a biphase clock signal having a frequency of 15.36 kHz. The bi-phase modulation circuit 13 is also supplied with ADIP (Address In Pre-groove) data in the frame format shown in FIG.

  The biphase modulation circuit 13 biphase modulates the biphase clock supplied from the divider 12 with ADIP data (address data) supplied from a circuit (not shown), and outputs the biphase signal to the FM modulation circuit 15. is doing. The FM modulation circuit 15 also receives a carrier having a frequency of 57.6 kHz obtained by dividing the 115.2 kHz signal generated by the generation circuit 11 by the value 2 by the divider 14. The FM modulation circuit 15 modulates the frequency of the carrier input from the divider 14 with the biphase signal input from the biphase modulation circuit 13 and outputs a frequency modulation signal obtained as a result. The left and right side walls of the pregroove 2 of the disk 1 are formed (wobbed) corresponding to this frequency modulation signal.

  4 and 5 show examples of the biphase signal output from the biphase modulation circuit 13. In this embodiment, when the preceding bit is 0, as shown in FIG. 4, “11101000” is used as the synchronization pattern (SYNC), and when the preceding bit is 1, the synchronization pattern is As shown in FIG. 5, “00010111” having a phase opposite to that shown in FIG. 4 is used. SYNC is a unique pattern that does not appear in modulation.

  Of the data bits (Data Bits) of the address data (ADIP data), “0” is bi-phase modulated and is “11” (when the previous channel bit is 0) or “00” (the previous channel bit is 1). ) Is converted into channel bits. Also, “1” is converted into a channel bit of “10” (when the previous channel bit is 0) or “01” (when the previous channel bit is 1). Which of the two patterns is converted depends on the previous code. That is, the “Wave Form” (waveform) in FIGS. 4 and 5 represents a channel bit pattern of 1 and 0 as a high level signal of 1 and a low level signal of 0, but this waveform is continuous. Thus, one of the two patterns is selected.

  The FM modulation circuit 15 frequency-modulates the carrier supplied from the divider 14 as shown in FIG. 6 in response to the biphase signal as shown in FIG. 4 or FIG.

  That is, when the channel bit data (biphase signal) is 0, the FM modulation circuit 15 outputs 3.5-wave carriers in a period corresponding to half the length of one data bit. The 3.5-wave carrier starts from a positive half wave or a negative half wave.

  On the other hand, when the channel bit data (biphase signal) is 1, four-wave carriers are output in a period corresponding to half the length of one data bit. These four wave carriers are also carriers starting from a positive half wave or carriers starting from a negative half wave.

  Accordingly, when the channel data bit 00 is input corresponding to the data 0, the FM modulation circuit 15 generates 7 (= 3.5 + 3.5) frequency modulation waves in the period corresponding to the length of the data bit. When channel data bit 11 is input, 8 frequency (= 4 + 4) frequency modulation waves are output. When channel data bits 10 or 01 are input corresponding to data 1, 7.5 frequency (= 4 + 3.5 = 3.5 + 4) frequency modulation waves are output.

  The carrier of 57.6 kHz inputted to the FM modulation circuit 15 corresponds to 7.5 waves, and the FM modulation circuit 15 corresponds to the data of this 7.5 waves, or ± 6 Generate 7 or 8 frequency modulated waves shifted by .67% (= 0.5 / 7.5).

  As described above, the carrier starting from the positive half wave and the carrier starting from the negative half wave corresponding to channel data 0 and channel data 1 are selected to be continuous with the previous signal.

  FIG. 7 shows an example of the frequency modulation wave output from the FM modulation circuit 15 in this way. In this example, the first data bit is 0 and the channel data bit is 00. For the first channel data bit 0, a 3.5-wave carrier starting with a positive half wave from the start point is selected. As a result, the end point of the carrier ends with a positive half wave. Therefore, 3.5 waves starting from the negative half wave are selected for the next channel data bit 0, and a total of 7 frequency-modulated waves are selected for data bit 0.

  This data bit 0 is followed by data bit 1 (channel bit 10). Since the 3.5 wave of channel data bit 0 corresponding to the previous data bit 0 ends in the negative half wave, the carrier of the four waves of the first channel data bit 1 corresponding to data bit 1 is Those starting with a positive half-wave are selected. Since the four waves of channel data bit 1 end with a negative half wave, the next four waves of channel data bit 0 are selected starting from the positive half wave.

  In the same manner, 7.5 waves, 8 waves, and 7 waves corresponding to data bit 1 (channel data bit 10), data bit 0 (channel data bit 11), and data bit 0 (channel data bit 00). Carriers are formed and output so as to be continuous at the boundary portion (start point and end point) of data bits.

As shown in FIG. 7, in this embodiment, the length of the channel bit is an integral multiple of 1/2 of the wavelength of the carrier in any of the 7-wave, 7.5-wave, and 8-wave carriers. It is said that the length. That is, the length of the channel bit is 7 times the wavelength of 7-wave carrier (frequency-modulated wave) and 8 times the half of 8-wave carrier (frequency-modulated wave). It is said that the length. The length of the channel bit is 7 times the wavelength of the 3.5 wave of the 7.5 wave carrier composed of 3.5 waves and 4 waves (when the channel bit is 0). Or 8 times the wavelength of 4 waves (when the channel bit is 1).

  Further, in this embodiment, the boundary portion (end point or start point) of the channel bits subjected to biphase modulation is the zero cross point of the frequency modulated wave. As a result, the phase of the address data (channel bit data) and the frequency modulation wave coincide with each other, the boundary between the bits can be easily identified, and the erroneous detection of the address data bits can be prevented. Accurate reproduction is facilitated.

  In this embodiment, the boundary portion (start point and end point) of the data bit corresponds to the edge (zero cross point) of the frequency modulation wave. As a result, the clock can be generated with reference to the edge of the frequency modulation wave. However, in this embodiment, as will be described later with reference to FIG. 9, the clock is generated based on the clock synchronization mark.

  FIG. 8 shows a configuration example of a recording apparatus (disk forming apparatus) for manufacturing the disk 1 having pregrooves. The wobbling signal generation circuit 21 has the configuration shown in FIG. 3 described above, and supplies the frequency modulation signal output from the FM modulation circuit 15 to the synthesis circuit 22. The mark signal generation circuit 23 generates a clock synchronization mark signal at a predetermined timing and outputs it to the synthesis circuit 22. The synthesizing circuit 22 synthesizes the frequency modulation signal output from the wobbling signal generation circuit 21 and the clock synchronization mark signal output from the mark signal generation circuit 23 and outputs the synthesized signal to the recording circuit 24.

  When the clock synchronization mark signal is supplied, the synthesis circuit 22 synthesizes the clock synchronization mark (Fine Clock Mark) with the carrier supplied from the wobbling signal generation circuit 21 as shown in FIG. When the recording / playback data modulation is EFM (Eight To Fourteen Modulation: (8-14) modulation) + such as DVD, the length of the clock synchronization mark is 6 to 14T (T is the length of the bit cell). It is assumed.

  That is, as shown in FIGS. 9A to 9D, when the channel bit data is 00 (data 0), 11 (data 0), 10 (data 1) or 01 (data 1), the respective data A clock synchronization mark having a frequency higher than the modulation frequency (57.6 kHz) of the address information is synthesized at the zero cross point of the carrier at the center of the channel (channel bit switching point). The clock synchronization mark is recorded for each data bit or a predetermined number of data bits.

  In this way, by inserting the clock synchronization mark at the zero crossing point of the wobbling frequency modulation wave corresponding to the center of the address data bit (channel data bit switching point), the fluctuation in the amplitude of the clock synchronization mark is reduced, and the detection thereof is reduced. It becomes easy.

  That is, in the FM modulation circuit 15, when the channel data bit is 0, frequency modulation is performed such that the frequency is shifted by -5% from the center frequency, and when the channel data bit is 1, the frequency is shifted by + 5% from the center frequency. When frequency modulation is performed, the boundary between the data bits or channel data bits and the zero cross point of the frequency modulation wave do not match, and channel data bits (or data bits) are easily detected erroneously. The insertion position of the clock synchronization mark is not necessarily a zero cross point, but is superimposed on a point having a predetermined amplitude value of the frequency modulated wave. As a result, the level of the clock synchronization mark increases or decreases by the amount of the amplitude value, making it difficult to detect. According to the present embodiment, the clock synchronization mark is always arranged at the zero-cross position of the frequency modulation wave, so that it can be easily detected (identified from the frequency modulation wave).

  The recording circuit 24 controls the optical head 25 in response to the signal supplied from the combining circuit 22 and generates laser light for forming a pregroove (including a clock synchronization mark) on the master 26. The spindle motor 27 rotates the master 26 at a constant angular velocity (CAV).

  That is, the frequency modulation signal generated by the wobbling signal generation circuit 21 is combined with the clock synchronization mark signal output from the mark signal generation circuit 23 in the combining circuit 22 and input to the recording circuit 24. The recording circuit 24 controls the optical head 25 in response to the signal input from the synthesis circuit 22 and generates laser light. Laser light generated from the optical head 25 is applied to the master 26 rotated at a constant angular velocity by the spindle motor 27.

  The master 26 is developed, a stamper is created from the master 26, and the disk 1 as a large number of replicas is formed from the stamper. As a result, the disk 1 on which the pregroove 2 having the clock synchronization mark described above is formed is obtained.

  FIG. 10 shows a configuration example of an optical disc recording / reproducing apparatus for recording / reproducing data on / from the disc 1 thus obtained. The spindle motor 31 rotates the disk 1 at a constant angular velocity. The optical head 32 irradiates the disk 1 with laser light, records data on the disk 1, and reproduces data from the reflected light. The recording / reproducing circuit 33 temporarily records recording data input from a device (not shown) in the memory 34, and the memory 34 stores data for one cluster (or data for one sector) as a recording unit. At this time, the data for one cluster is read out, modulated by a predetermined method, etc., and output to the optical head 32. The recording / reproducing circuit 33 appropriately demodulates the data input from the optical head 32 and outputs it to a device (not shown).

  The address generating / reading circuit 35 generates a data address (sector address) (FIG. 13) to be recorded in the track (pre-groove 2) in response to the control from the control circuit 38, and outputs it to the recording / reproducing circuit 33. . The recording / reproducing circuit 33 adds this address to recording data supplied from a device (not shown), and outputs it to the optical head 32. Further, when the address data is included in the reproduction data reproduced from the track of the disk 1 by the optical head 32, the recording / reproducing circuit 33 separates the address data and outputs it to the address generating / reading circuit 35. The address generation / read circuit 35 outputs the read address to the control circuit 38.

  The mark detection circuit 36 detects a component corresponding to the clock synchronization mark from the RF signal reproduced and output by the optical head 32. The frame address detection circuit 37 reads address information (track number and frame number in FIG. 2) included in the wobbling signal from the RF signal output from the optical head 32 and supplies it to the cluster counter 46 and the control circuit 38. Yes.

  The mark period detection circuit 40 determines the periodicity of detection pulses output when the mark detection circuit 36 detects a clock synchronization mark. That is, since the clock synchronization mark is generated at a constant cycle, it is determined whether or not the detection pulse input from the mark detection circuit 36 is a detection pulse generated at this fixed cycle, and is generated at a fixed cycle. If it is a detection pulse, a pulse synchronized with the detection pulse is generated and output to the phase comparator 42 of the PLL circuit 41 at the subsequent stage. Further, the mark period detection circuit 40 generates a pseudo pulse at a predetermined timing so that the PLL circuit 41 at the subsequent stage does not lock to an incorrect phase when the detection pulse is not input at a constant period.

  The PLL circuit 41 includes a low-pass filter (LPF) 43, a voltage controlled oscillator (VCO) 44, and a frequency divider 45 in addition to the phase comparator 42. The phase comparator 42 compares the phases of the input from the mark period detection circuit 40 and the input from the frequency divider 45 and outputs the phase error. The low pass filter 43 smoothes the phase error signal output from the phase comparator 42 and outputs it to the VCO 44. The VCO 44 generates a clock having a phase corresponding to the output of the low pass filter 43 and outputs it to the frequency divider 45. The frequency divider 45 divides the clock input from the VCO 44 by a predetermined value (value specified by the control circuit 38), and outputs the frequency division result to the phase comparator 42.

  The clock output from the VCO 44 is supplied to each circuit and is also supplied to the cluster counter 46. The cluster counter 46 counts the number of clocks output from the VCO 44 based on the frame address supplied from the frame address detection circuit 37, and the count value corresponds to a predetermined value (corresponding to the length of one cluster). A cluster start pulse is generated and output to the control circuit 38.

  The sled motor 39 is controlled by the control circuit 38 to move the optical head 32 to a predetermined track position of the disk 1. The control circuit 38 controls the spindle motor 31 to rotate the disk 1 at a constant angular velocity (CAV).

  The ROM 47 stores a table that defines the correspondence between the track number (FIG. 2) in the address frame and the zones that divide the data recording area of the disk 1.

  That is, the control circuit 38 records or reproduces data by dividing the disk 1 into a plurality of zones (m + 2 zones from the 0th zone to the (m + 1) th zone in this embodiment) as shown in FIG. Now, when the number of data frames per track in the 0th zone (this data frame is a unit of a block of data unlike the address frame described with reference to FIG. 2) is n, In the first zone, the number of data frames per track is n + 16. Hereinafter, similarly, the number of data frames in the outer peripheral zone increases by 16 as compared with the adjacent inner peripheral zone, and n + 16 × (m + 1) data frames in the outermost m + 1 zone. Number.

  The first zone is switched from a radial position where a capacity of n + 16 frames is obtained with the same linear density as the innermost circumference linear density of the zeroth zone. Similarly, the m-th zone is the m-th zone from the radial position where a capacity of n + 16 × m frames can be obtained with the same linear density as the innermost circumferential line density of the zeroth zone.

  For example, if the radius of the disk 1 is in the range of 24 mm to 58 mm as the recording / reproducing area, the track pitch is 0.87 μm, and the linear density is 0.38 μm / bit, the recording / reproducing area is divided into 48 zones. In the 0th zone having a disc radius of 24 mm, there are 528 frames per track, and as the zone is incremented by 1, 16 frames are increased per track.

  As will be described later, in this embodiment, since one sector is composed of 24 frames (data frames), the number of frames incremented for each zone (= 16) is the number of frames constituting this one sector. That is, it is set to a value smaller than (= 24). As a result, many zones can be formed in finer units, and the capacity of the disk 1 can be increased.

Next, the operation of the embodiment will be described with reference to a block diagram showing a configuration example of an optical disk recording / reproducing apparatus in which a recording / reproducing apparatus for recording or reproducing data is applied to the disk 1 of the present invention shown in FIG . Here, the operation at the time of data recording will be described. The optical head 32 irradiates the optical disc 1 with laser light and outputs an RF signal obtained from the reflected light. The frame address detection circuit 37 reads wobbling information (address information) from this RF signal and outputs the read result to the control circuit 38 and also supplies it to the cluster counter 46. The wobbling information is also input to the mark detection circuit 36, where a clock synchronization mark is detected and supplied to the mark period detection circuit 40.

  The mark period detection circuit 40 determines the periodicity of the clock synchronization mark, generates a predetermined pulse corresponding thereto, and outputs it to the PLL circuit 41. The PLL circuit 41 generates a clock (recording clock) synchronized with this pulse and supplies it to the cluster counter 46.

  The control circuit 38 can detect the position of the reference clock synchronization mark in one track (one rotation) from the frame address (frame number) supplied from the frame address detection circuit 37. For example, an arbitrary position on the track can be accessed from the count value of the recording clock with reference to the clock synchronization mark detected at the beginning of the frame of frame number 0 (address frame).

  As described above, when an arbitrary position on the track is accessed, it is necessary to determine which zone the access point belongs to and generate a clock having a frequency corresponding to the zone in the VCO 44. . Therefore, the control circuit 38 further executes a clock switching process as shown in the flowchart of FIG.

  That is, first in step S 1, the control circuit 38 reads the track number from the frame address of the access point output by the frame address detection circuit 37. In step S 2, the zone corresponding to the track number read in step S 1 is read from the table stored in the ROM 47. As described above, in the table of the ROM 47, it is stored in advance which zone the numbered track belongs to from the 0th zone to the (m + 1) th zone.

  Accordingly, in step S3, it is determined whether or not the track number just read is a new zone different from the zone accessed so far. If it is determined that the zone is a new zone, the process proceeds to step S4, and the control circuit 38 controls the frequency divider 45 to set a frequency division ratio corresponding to the new zone. As a result, a recording clock having a different frequency for each zone is output from the VCO 44.

  If it is determined in step S3 that the current zone is not a new zone, the process in step S4 is skipped. That is, the frequency division ratio of the frequency divider 45 is not changed and is left as it is.

  Next, the format of the recording data will be described. In this embodiment, as described above, data is recorded in units of one cluster (32 kbytes). This cluster is configured as follows.

  That is, 2 kbytes (2048 bytes) of data is extracted as one sector of data, and 16 bytes of overhead is added thereto as shown in FIG. This overhead includes a sector address (an address generated or read by the address generation / read circuit 35 in FIG. 10), an error detection code for error detection, and the like.

  The total of 2064 (= 2048 + 16) bytes of data is 12 × 172 (= 2064) bytes of data as shown in FIG. Then, 16 pieces of data corresponding to one sector are collected to obtain 192 (= 12 × 16) × 172 bytes of data. A 10-byte inner code (PI) and a 16-byte outer code (PO) are added to the 192 × 172 bytes of data as parity for each byte in the horizontal and vertical directions.

  Further, of the data blocked in this way into 208 (= 192 + 16) × 182 (= 172 + 10) bytes, the 16 × 182 byte outer code (PO) is divided into 16 1 × 182 byte data. Then, as shown in FIG. 15, one by one is added under the 16 sector data of number 0 to number 15 of 12 × 182 bytes and interleaved. Then, 13 (= 12 + 1) × 182 bytes of data is used as one sector of data.

  Further, the 208 × 182 byte data shown in FIG. 15 is divided into two in the vertical direction as shown in FIG. 16, and one frame becomes 91 byte data, and 208 × 2 frame data. A 2-byte frame synchronization signal (FS) is further added to the head of the 91-byte frame data. As a result, as shown in FIG. 16, the data of one frame becomes a total of 93 bytes of data, and a total of 208 × (93 × 2) bytes of block data. This is data for one cluster. The size of the actual data part excluding the overhead part is 32 kbytes (= 2048 × 16/1024 kbytes).

  That is, in this embodiment, one cluster is composed of 16 sectors, and one sector is composed of 24 frames.

  Such data is recorded in the disk 1 in units of clusters. At this time, the control circuit 38 arranges link areas between the clusters as shown in FIG.

  As shown in FIG. 17, the link area is composed of four frames (data frames), and the data of one frame is 93 bytes as in the case of the data area (in the cluster). A 2-byte frame synchronization signal (FS) (Frame Sync) is arranged at the head of each frame.

  The link area is recorded by adding 86 bytes and 3 frames of data before a 32 kbyte data block (cluster). Of the 86 bytes of data, the first 20 bytes are used as a prebuffer and ALPC (Automatic Laser Power Control). The pre-buffer is a buffer that absorbs the deviation of the start position of the cluster due to jitter, and the ALPC is for setting recording power in which data for setting the output at the time of recording or reproduction of laser light to a predetermined value is recorded. It is an area.

  In the next 66 bytes, Slice / PLL is arranged. Slice is data for setting a time constant for binarizing reproduction data, and PLL is data for reproducing a clock.

  Slice / PLL is arranged in the following two frames, respectively. In the last one frame, the slice / PLL is arranged in the first 83 bytes, the synchronization signal (Sync) is arranged in the next 4 bytes, and the last 4 bytes are reserved for future use (Reserve). It is said.

  Further, after the 32 kbyte (cluster) data block, a 2-byte frame synchronization signal, a 1-byte postamble, and an 8-byte postbuffer are formed. In the postamble, the data for returning the signal polarity is recorded by adjusting the mark length of the last data. The post buffer is a buffer area for absorbing jitter due to eccentricity or the like. In the ideal state where there is no jitter, 4 bytes of the 8-byte post buffer overlap, and the pre-buffer and ALPC of the next cluster are recorded.

  It is also possible to apply this link area to a ROM disk so that the ROM disk and the RAM disk have a common format. In that case, in the ROM disk, information can be recorded in the post buffer, pre-buffer, and ALPC in the link area. For example, it is possible to insert an address and increase the information probability of the address.

  As described above, according to the disk of the present invention, the number of data frames per revolution of the outer peripheral zone is larger by an integer K smaller than the integer F than the number of data frames per revolution of the inner zone. Since the value is set, the zone CAV can be realized in units of data frames smaller than the sector, and the capacity can be further increased.

  Note that the length (number of bytes) of each area in the above embodiment is an example, and a predetermined value can be set as appropriate.

  The present invention can also be applied when data is recorded or reproduced on a disk other than the optical disk.

It is a figure explaining the state by which the disk of this invention was wobbled. It is a figure which shows the structural example of a wobbling address frame. It is a figure which shows the structural example of a wobbling signal generation circuit. It is a figure which shows the example of the biphase signal which the biphase modulation circuit of FIG. 3 outputs. It is a figure which shows the other example of the biphase signal which the biphase modulation circuit of FIG. 3 outputs. It is a figure explaining the frequency modulation which FM modulation circuit 15 of FIG. 3 performs. It is a figure which shows the frequency modulation wave which the FM modulation circuit 15 of FIG. 3 outputs. It is a figure which shows the structural example of the recording device for manufacturing the disk 1 which has a pre-groove. It is a figure explaining operation | movement of the synthetic | combination circuit 22 of FIG. It is a block diagram which shows the structural example of the optical disk recording / reproducing apparatus which applied the recording / reproducing apparatus which records or reproduces | regenerates data with respect to the disc 1 of this invention. It is a figure explaining the zone in a disc. It is a flowchart explaining the clock switching process in the Example of FIG. It is a figure explaining the format of the data for 1 sector. It is a figure explaining the structure of 32 kbytes data. It is a figure explaining the state which interleaved the outer code | symbol of FIG. It is a figure explaining the structure of the data of a block of 32k bytes. It is a figure which shows the structural example of a link area.

Explanation of symbols

  1 optical disk, 2 pregroove, 11 generation circuit, 12, 14 divider, 13 biphase modulation circuit, 15 FM modulation circuit, 21 wobbling signal generation circuit, 22 synthesis circuit, 23 mark signal generation circuit, 24 recording circuit, 25 Optical head, 26 master disk, 27 spindle motor, 31 spindle motor, 32 optical head, 33 recording / reproducing circuit, 34 memory, 35 address generation reading circuit, 36 mark detection circuit, 37 frame address detection circuit, 38 control circuit, 39 thread motor , 40 mark period detection circuit, 41 PLL circuit, 42 phase comparator, 43 LPF, 44 VCO, 45 frequency divider, 46 cluster counter, 47 ROM

Claims (2)

A pre-groove disc wobbled by a frequency-modulated wave that has been frequency-modulated by address information,
The data bits representing the address information include a first carrier having 3.5 wavelengths in a predetermined period, and a second carrier having four wavelengths, which is half a wavelength greater than the first carrier, in the predetermined period. disc characterized in that it comprises a. The first and second carriers have a carrier starting from a positive half wave and a carrier starting from a negative half wave, respectively, so that the phase of the frequency-modulated wave matches at the boundary with the immediately preceding data bit. When the immediately preceding data bit ends with a positive half wave, the carrier starting from the negative half wave is selected, and when the immediately preceding data bit ends with a negative half wave, the carrier starting from the positive half wave is selected. The disk according to claim 1, wherein the disk is selected.

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