JP2005018986A - Optical disk, optical disk recording device, and optical disk recording method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To record data at an accurate position at a high speed, in a disk in which an address is recorded by wobbling. <P>SOLUTION: A track of the optical disk is divided into a plurality of clusters for recording data, in which a link area is formed between the clusters. The cluster and the link area are constituted by the unit of a frame, where one frame is formed of 85 bytes. One cluster is composed of 28 frames, or 16 K bytes. The link area is composed of two frames. In both of the cluster and the link area, an FS (Frame Sync: synchronization signal) of two bytes is placed at the head of each frame. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to an optical disc, an optical disc recording apparatus, and an optical disc recording method, and in particular, by wobbling a pre-groove, data can be recorded at an accurate position at high speed on an optical disc on which address information is recorded. The present invention relates to an optical disc, an optical disc recording apparatus, and an optical disc recording method.

  In order to record data on a disc, it is necessary to record address information so that the data can be recorded at a predetermined position. This address information may be recorded by wobbling.

  That is, a track for recording data is formed in advance as a pregroove, for example, and the side wall of the pregroove is wobbled (meandered) in accordance with the address information. In this way, the address can be read from the wobbling information, and data can be recorded and reproduced at a desired position.

  However, since the wobbling information has a very low density with respect to the recording / reproducing information, the reference of the recording position of the sector becomes rough, and the recording position of the sector shifts at every recording. For this reason, front and back sectors may interfere. In addition, it is necessary to absorb jitter due to eccentricity and the like, and in order to prevent these, a considerable unrecorded buffer area is required, which causes a problem that is very disadvantageous in terms of data capacity. As a result, the system becomes very redundant and there is a problem that it is difficult to perform high-density random recording / reproduction.

  In addition, in order to record and reproduce data randomly on a recordable optical disk, a PLL circuit that generates a reference clock for recording and reproduction in addition to an address such as a track address and a sector address It is necessary to form a VFO area in which data for drawing in is recorded. Further, in the case of the recording method including the address and the like in the recording data, a linking sector in which dummy data for switching from the previous reproduction state to the recording state is recorded is required before the recording sector.

  As described above, in order to be able to actually record data on the optical disc at random, an area in which these addresses and VFO are recorded must be formed in addition to the area in which data is originally recorded. However, the conventionally proposed method has a problem that the overhead becomes long and the substantial recording capacity of the optical disk is reduced.

  Further, in a conventional CD-ROM or the like, there is a synchronization signal called “frame sync” every predetermined period, and synchronous processing is performed in units of this synchronization signal. However, if the ROM disk and the RAM disk have the same format in the form of a header, the synchronization system is not continued in units of recording sectors due to the header, and there is a problem that the synchronization system processing becomes difficult.

  The present invention has been made in view of such a situation, and makes it possible to record data at an accurate position at high speed on a disk on which addresses are recorded by wobbling.

  The optical disk according to claim 1 is an optical disk having a pregroove in which tracks for recording data are formed in advance and formed in a spiral shape or a concentric shape, and the pregroove includes a plurality of wobbling frames, and the wobbling frame The predetermined number of bits in the first first area is wobbled so as to represent the synchronization signal, and the predetermined number of bits in the second area after the first area is one of the plurality of recording layers. The predetermined number of bits in the third area after the second area is an address indicating which of the plurality of recording units is included in the recording layer. It is characterized by corresponding wobbling.

  The optical disk recording apparatus according to claim 5, wherein a track for recording data is formed in advance and has a pregroove formed in a spiral shape or a concentric circle, and the pregroove includes a plurality of wobbling frames, The predetermined number of bits in the first first area are wobbled so as to represent the synchronization signal, and the predetermined number of bits in the second area after the first area are any of the plurality of recording layers. A predetermined number of bits in the third area after the second area corresponds to an address indicating which of the plurality of recording units is included in the recording layer. An optical disk recording apparatus that records data on an optical disk that is wobbled and records first data on the optical disk The recording / reproducing means for reproducing the second data necessary for recording from the optical disc and recording the first data on the optical disc, and the control means for controlling the recording / reproducing means. The address data including information indicating which of the plurality of recording layers is the recording position of the data being reproduced and output is separated from the data of the data, and the control means records the data based on the address data. Controlling the recording of the first data on the optical disk by the reproducing means.

  The optical disk recording method according to claim 6, wherein a track for recording data is formed in advance, has a pregroove formed in a spiral shape or a concentric circle, and the pregroove includes a plurality of wobbling frames, The predetermined number of bits in the first first area are wobbled so as to represent the synchronization signal, and the predetermined number of bits in the second area after the first area are any of the plurality of recording layers. A predetermined number of bits in the third area after the second area corresponds to an address indicating which of the plurality of recording units is included in the recording layer. An optical disc recording method of an optical disc recording apparatus for recording data on an optical disc wobbled by The second data necessary for recording the data is reproduced from the optical disc, and from the reproduced second data, information indicating which of the plurality of recording layers is the data recording position , And the recording of the first data onto the optical disk is controlled based on the separated address data.

  In the optical disk according to claim 1, the pregroove includes a plurality of wobbling frames, and in the wobbling frame, a predetermined number of bits in the first first area are wobbled to represent a synchronization signal, and the first The predetermined number of bits in the second area after the second area is wobbled to indicate which layer of the plurality of recording layers, and the predetermined number in the third area after the second area These bits are wobbled in correspondence with an address indicating which of a plurality of recording units included in the recording layer.

  In the optical disk recording device according to claim 5 and the optical disk recording method according to claim 6, the second data necessary for recording the first data on the optical disk is reproduced from the optical disk and reproduced. From the second data, address data including information indicating which of the plurality of recording layers is the recording position of the data is separated, and based on the separated address data, the first data Recording on the optical disc is controlled.

  As described above, according to the optical disk of the first aspect, from the address indicating which one of the plurality of recording layers is one of the plurality of recording units included in the recording layer. Since this is expressed by wobbling in the previous area, it is possible to perform a focus jump at high speed without reading up to an address indicating which one of a plurality of recording units included in the recording layer.

  According to the optical disc recording apparatus according to claim 5 and the optical disc recording method according to claim 6, which layer of the plurality of recording layers is determined among the plurality of recording units included in the recording layer. Second data necessary for recording the first data on the optical disk represented by wobbling in the area before the address indicating which one is recorded is reproduced from the optical disk, and the reproduced second data The address data including information indicating which one of the plurality of recording layers is the data recording position is separated from the data of the first data, and the first data optical disk is separated based on the separated address data. Since it is possible to control recording, it is possible to perform focus adjustment at high speed without reading up to an address indicating which of a plurality of recording units included in the recording layer. It is possible to perform up.

  FIG. 1 shows a configuration example of an optical disk according to the present invention. As shown in the figure, a pregroove 2 is formed in advance in a spiral shape on the disk (optical disk) 1 from the inner periphery to the outer periphery. Of course, the pregroove 2 can also be formed concentrically.

  In addition, as shown in FIG. 1, a part of the pregroove 2 is enlarged, and the left and right side walls are wobbled corresponding to the address information and meandering at a predetermined period corresponding to the wobbling signal. Yes. One track (one round of track) has a plurality of wobbling address frames, and each wobbling address frame has a configuration as shown in FIG.

  As shown in FIG. 2, the wobbling address frame is composed of 60 bits, and the first 4 bits are a synchronization signal (Sync) indicating the start of the wobbling address frame. The next 4 bits are a layer (Layer) that indicates which of a plurality of recording layers. The next 20 bits are a track address. Further, the next 4 bits represent a frame number. The subsequent 14 bits are used as an error correction code (CRC), and an error detection code excluding a synchronization signal (Sync) and a clock synchronization mark area (Sync mark) described later is recorded. The next 12 bits are used as a clock synchronization mark area (in actuality, however, as will be described later with reference to FIG. 3, the clock synchronization mark area is separated at a 5-bit period). The last 2 bits (Reserved) are reserved for the future.

  For example, eight wobbling address frames are formed per track and are recorded in a state where the rotational angular velocity of the disk is constant (CAV (Constant Angular Velocity)).

  FIG. 3 shows a clock synchronization mark area and a clock synchronization mark (Fine Clock Mark). In each wobbling address frame, 60 bits of data are recorded. As shown in FIG. 3, 1 bit is represented by 7 waves (carriers) of a signal of a predetermined frequency. Will have 420 waves. If the optical disk 1 is rotated 1200 rpm, the frequency of this carrier is 67.2 kHz.

  As shown in FIG. 3, in the wobbling address frame shown in FIG. 2, each clock synchronization mark area is arranged bit by bit with an interval of 4 bits of address information. That is, data is recorded with a period of 5 bits. Of the 5 bits, the first 1 bit is a bit for a clock synchronization mark (Fine Clock Mark), and the remaining 4 bits are substantial address data not including a fine clock mark. The frequency of the carrier in the clock synchronization mark area is the center frequency of the frequency modulation range, and the frequency of the carrier in the address data area is a value corresponding to the address data. Accordingly, 12 bits (pieces) of fine clock marks and 48 bits (pieces) of address data are recorded in one frame, and 96 (= 12 × 8) in one rotation (one track). ) Fine clock marks are recorded.

  The address information is bi-phase modulated and then further frequency-modulated, and the pregroove is wobbled by this frequency-modulated wave. In the clock synchronization mark area, the pregroove wobbling frequency is set to the center frequency of the modulation frequency of the address information.

  The period (length) of the clock synchronization mark is 6 to 8 T when the recording / reproduction data modulation method is EFM (Eight To Fourteen Modulation: (8-14) modulation) as in the case of CD or the like. Become. A signal for one period (one wavelength) (a signal having a higher frequency than the carrier for wobbling) is superimposed on the carrier as a clock synchronization mark to wobble the track.

  FIG. 4 shows a configuration example of a wobbling address generation circuit that generates a wobbling signal for wobbling the pregroove 2. The generation circuit 11 generates a signal having a frequency of 44.1 kHz. The frequency of 44.1 kHz is the same frequency as the sampling clock for audio data of Minidisc (trademark).

  The signal generated by the generation circuit 11 is supplied to the division circuit 12, divided by the value 7, and then supplied to the biphase modulation circuit 13 as a biphase clock signal having a frequency of 6300 Hz. The bi-phase modulation circuit 13 is also supplied with ADIP (AD Address In Pre-groove) data as address data.

  The biphase modulation circuit 13 biphase modulates the biphase clock supplied from the divider 12 with ADIP data supplied from a circuit (not shown), and outputs the biphase signal to the FM modulation circuit 15. The FM modulation circuit 15 is also supplied with a carrier having a frequency of 22.05 kHz obtained by dividing the 44.1 kHz signal generated by the generation circuit 11 by the value 2 by the divider 14. The FM modulation circuit 15 frequency-modulates the carrier input from the divider 14 with the biphase signal input from the biphase modulation circuit 13, and outputs the FM signal obtained as a result. The left and right side walls of the pregroove 2 of the disk 1 are formed (wobbed) corresponding to the FM signal. As described above, the frequency of the carrier in the clock synchronization mark area is 22.05 kHz.

  5 and 6 show examples of the biphase signal output from the biphase modulation circuit 13. In this embodiment, when the preceding bit is 0, as shown in FIG. 5, “11101000” is used as the synchronization pattern, and when the preceding bit is 1, the synchronization pattern is as shown in FIG. "00010111" is used as shown in FIG.

  Data bits are bi-phase modulated and converted to channel bits. 5 and 6, the data bit “0” is set to “11” (when the previous bit is “0”) or “00” (when the previous bit is “1”). The data bit “1” is converted into the channel bit “01” (when the previous bit is “1”) or “10” (when the previous bit is “0”). SYNC is an irregular pattern that does not appear in modulation. “Wave Form” in FIG. 5 is obtained by converting channel bits into a pattern of 1, 0.

  FIG. 7 shows a configuration example of a recording apparatus for manufacturing the disc 1 having pregrooves. The wobbling signal generation circuit 21 has the configuration shown in FIG. 4 described above, and outputs the FM signal to the synthesis circuit 22. The mark signal generation circuit 23 generates a clock synchronization mark signal at the timing of forming the clock synchronization mark and outputs it to the synthesis circuit 22. The synthesizing circuit 22 synthesizes the FM signal output from the wobbling signal generating circuit 21 and the clock synchronization mark signal output from the mark signal generating circuit 23 and outputs the synthesized signal to the recording circuit 24. The recording circuit 24 controls the optical head 25 in response to the signal supplied from the synthesis circuit 22 to generate laser light for forming pregrooves and synchronization marks on the master 26. The spindle motor 27 rotates the master 26 at a predetermined speed.

  That is, the FM signal generated by the wobbling signal generation circuit 21 is combined with the clock synchronization mark signal output from the mark signal generation circuit 23 in the combining circuit 22 and input to the recording circuit 24. The recording circuit 24 controls the optical head 25 in response to the signal input from the synthesis circuit 22 and generates laser light. Laser light generated from the optical head 25 is applied to the master 26 rotated by the spindle motor 27 at a predetermined speed.

  The master 26 is developed, a stamper is created from the master 26, and the disk 1 as a large number of replicas is formed from the stamper. As a result, the disk 1 on which the pregroove 2 having the clock synchronization mark described above is formed is obtained.

  FIG. 8 shows a configuration example of an optical disc recording / reproducing apparatus for recording / reproducing data on / from the disc 1 thus obtained. The spindle motor 31 rotates the disk 1 at a predetermined speed. The optical head 32 irradiates the disk 1 with laser light, records data on the disk 1, and reproduces data from the reflected light. The recording / reproducing circuit 33 temporarily records recording data input from a device (not shown) in the memory 34. When the data for one cluster as a recording unit is stored in the memory 34, the data for one cluster is read. The signal is output to the optical head 32 by being modulated by a predetermined method. The recording / reproducing circuit 33 appropriately demodulates the data input from the optical head 32 and outputs it to a device (not shown).

  The address generating / reading circuit 35 generates an address (not an address recorded as wobbling information) to be recorded in the track (pregroove 2) in response to the control from the control circuit 38, and outputs it to the recording / reproducing circuit 33. ing. The recording / reproducing circuit 33 adds this address to recording data supplied from a device (not shown), and outputs it to the optical head 32. Also, when the address data is included in the reproduction data reproduced from the track of the disk 1, the optical head 32 separates the address data and outputs it to the address generation reading circuit 35. The address generation / read circuit 35 outputs the read address to the control circuit 38.

  The mark detection circuit 36 detects a component corresponding to the clock synchronization mark from the RF signal (wobbling signal) reproduced and output by the optical head 32. The frame address detection circuit 37 reads address information included in the wobbling signal from the RF signal (wobbling signal) output from the optical head 32, detects the frame address, and supplies the frame address to the cluster counter 46.

  The mark period detection circuit 40 determines the periodicity of detection pulses output when the mark detection circuit 36 detects a clock synchronization mark. That is, since the clock synchronization mark is generated at a constant cycle (every 5 bits), it is determined whether or not the detection pulse input from the mark detection circuit 36 is a detection pulse generated at this fixed cycle. If it is a detection pulse generated at a period of, a pulse synchronized with the detection pulse is generated and output to the phase comparator 42 of the PLL circuit 41 at the subsequent stage. Further, the mark period detection circuit 40 generates a pseudo pulse at a predetermined timing so that the PLL circuit 41 at the subsequent stage does not lock to an incorrect phase when the detection pulse is not input at a constant period.

  The PLL circuit 41 includes a low-pass filter 43, a voltage controlled oscillator (VCO) 44, and a frequency divider 45 in addition to the phase comparator 42. The phase comparator 42 compares the phases of the input from the mark period detection circuit 40 and the input from the frequency divider 45 and outputs the phase error. The low-pass filter 43 compensates the phase of the phase error signal output from the phase comparator 42 and outputs it to the VCO 44. The VCO 44 generates a clock having a phase corresponding to the output of the low pass filter 43 and outputs it to the frequency divider 45. The frequency divider 45 divides the clock input from the VCO 44 by a predetermined value and outputs the result of the frequency division to the phase comparator 42.

  The clock output from the VCO 44 is supplied to each circuit and is also supplied to the cluster counter 46. The cluster counter 46 counts the number of clocks output from the VCO 44 based on the frame address in the wobbling signal supplied from the frame address detection circuit 37, and the count value is set to a predetermined value (one cluster). When the value corresponding to the length) is reached, a cluster start pulse is generated and output to the control circuit 38.

  The sled motor 39 is controlled by the control circuit 38 to move the optical head 32 to a predetermined track position of the disk 1. The control circuit 38 controls the spindle motor 31 so as to rotate the disk 1 at a predetermined speed.

  Next, the operation will be described. Here, the operation at the time of data recording will be described. The optical head 32 irradiates the optical disk 1 with laser light and outputs an RF signal (wobbling signal) obtained from the reflected light. The frame address detection circuit 37 reads the frame number (FIG. 2) from the wobbling signal and outputs the read result to the control circuit 38 and also supplies it to the cluster counter 46. The wobbling signal output from the optical head 32 is also input to the mark detection circuit 36, where a clock synchronization mark is detected and supplied to the mark period detection circuit 40.

  The mark period detection circuit 40 determines the periodicity of the clock synchronization mark (occurs at a rate of once every 5 bits as shown in FIG. 3), generates a predetermined pulse corresponding thereto, and Output. The output from the PLL circuit 41 is supplied to the cluster counter 46.

  The control circuit 38 can detect the position of the reference clock synchronization mark in one track circumference from the frame address supplied from the frame address detection circuit 37 and the configuration of the wobbling address frame. With this as a reference, any position on the track can be accessed from the recording clock.

  FIG. 9 shows an example of a sector format of data recorded in a track of a proposed high density CD-ROM. As shown in the figure, each sector has 2 frames in the horizontal direction, 14 frames in the vertical direction, and 28 frames as a whole, and a data area of 1 sector is configured with a capacity of 2 kilobytes (2048 bytes). ing.

  The first two bytes of one frame are FS (Frame Sync: synchronization signal), and the subsequent 85 bytes are a data area. The 20 bytes of the data area at the head of the sector are used as an address area, and a sector address (sector number) and a track address (track number) are recorded. Predetermined data such as computer data and video data is recorded in an area following the address area of the data area.

  A 4-byte EDC is arranged at the end of the data area of the sector. This is an error detection code for 2048-byte data.

  An 8-bit parity C1 and a 14-bit parity C2 are arranged at the right ends of the two frames arranged in the horizontal direction. These are error correction codes, and are set for 170 bytes of data of two frames. The C1 series is set for two frames of data in the horizontal direction (horizontal direction) in the figure. On the other hand, the C2 sequence is encoded in a manner interleaved with the C1 sequence. That is, data is set for 170 bytes (340 frames) from the upper left to the lower right (in an oblique direction).

  FIG. 10 shows a configuration example of the ECC block of the cluster. One cluster is composed of an integral multiple of sectors (in this embodiment, 8 sectors (= 28 frames = 16 kilobytes)). As shown in the figure, the C2 sequence of error correction codes is completed in one cluster.

  FIG. 11 shows a configuration example of the link area. A link area is formed between clusters. The link area is composed of two frames, and the data of one frame is 85 bytes as in the case of the data area. A 2-byte FS (Frame Sync: synchronization signal) is arranged at the head of each frame. A 1-byte postamble and a 2-byte postbuffer belong to the previous cluster. In the postamble, data for adjusting the mark length of the last data and returning the signal polarity is recorded. The The post buffer is a buffer area for absorbing jitter due to eccentricity or the like.

  From the next 2-byte prebuffer (Prebuffer) of the postbuffer, it belongs to the next cluster to be recorded. This pre-buffer is a buffer that absorbs the start position of the cluster. The next 16 bytes are ALPC (Automatic Laser Power Control), which is a recording power setting area in which data for setting the output during laser beam recording or reproduction to a predetermined value is recorded. The next 64 bytes are set as VFO, and data for PLL pull-in is recorded. That is, the clock for executing the synchronous pull-in operation is recorded in the PLL circuit 41 shown in FIG.

  Next to the FS of the next frame is a 38-byte VFO, and the PLL circuit drawing data for the recording data is recorded. The VFO is followed by a 4-bit security control.

  Copy protection information is recorded in the security control. For example, when this copy protection information is recorded in the data area, it is handled as data and may be read or rewritten freely from the host computer, and the protection function may not be performed. On the other hand, when the copy protection information is recorded in the link area, the link area information is not data, so it cannot be accessed from the host computer and becomes very effective copy protection information.

  The next 8-byte address (Address) is composed of a 2-byte address mark (AM), a 4-byte track and cluster address (Address), and a 2-byte error detection code (CRC). As the above VFO and address, substantially the same data is recorded twice in order to increase the detection probability of the address. However, the VFO has a first length of 38 bytes and a second length of 19 bytes. Finally, a 2-byte sync for data start synchronization is provided. Here, a synchronization signal indicating the start position of the recording data is recorded.

  Thus, in this embodiment, by setting the clock synchronization mark area as the center frequency of the modulation frequency of the wobbling carrier of the wobbling address information, the clock synchronization mark area can be changed without affecting the detection of the wobbling address information. The clock synchronization mark can be easily detected while being easily detected. By forming a plurality of clock synchronization marks around one track, the recording clock can be accurately reproduced from the period in which the clock synchronization marks are detected. As a result, the recording / reproducing sector position can be determined with high accuracy, and jitter due to eccentricity can be suppressed. As a result, high-density random recording / reproduction is possible. In addition, since it is not necessary to increase the buffer between clusters, higher-density recording / reproduction is possible.

  In addition, by configuring the overhead area in units of data frames, it becomes easy to ensure the period regardless of the overhead, and recording / reproduction can be performed at random positions. Further, in a writable disc such as a CD-ROM, the data area format is made common with the read-only high-density CD-ROM, and the frame structure of the link area is made the same as that of the data frame structure. The system can be shared, and the read-only hardware and the configuration of the optical disk apparatus can be shared.

  It is also possible to apply this link area to a ROM disk so that the ROM disk and the RAM disk have a common format. In that case, in the ROM disk, information can be recorded in the post buffer, pre-buffer, and ALPC in the link area. For example, a VFO can be inserted to provide continuity to the PLL from the previous cluster. Alternatively, it is possible to insert an address and increase the information probability of the address.

  FIG. 12 shows another configuration example (format) of the wobbling address frame. As shown in the figure, this wobbling address frame is composed of 48 bits, and the first 4 bits are a synchronization signal (Sync) indicating the start of the wobbling address frame. The next 4 bits are a layer (Layer) that indicates which of a plurality of recording layers. The next 20 bits are a track address (track number). Further, the next 4 bits represent the frame number of the address frame. The subsequent 14 bits are used as an error detection code (CRC), and an error detection code for data excluding the synchronization signal (Sync) is recorded. The last 2 bits (Reserved) are reserved for the future. That is, in this embodiment, the clock synchronization mark area (sync mark area) in FIG. 2 is omitted.

  This wobbling address frame is recorded in a CAV disk shape in which the rotational angular velocity of the disk is constant, for example, for 8 address frames per track (1 rotation). Therefore, for example, a value from 0 to 7 is recorded as the frame number of the address frame.

  FIG. 13 shows a configuration example of a wobbling signal generation circuit that generates a wobbling signal for wobbling the pregroove 2 corresponding to the address frame having the format shown in FIG. The basic configuration is the same as in FIG. 4, but the frequency is different. That is, the generation circuit 11 generates a signal having a frequency of 115.2 kHz. The signal generated by the generation circuit 11 is supplied to the division circuit 12, divided by the value 7.5, and then supplied to the biphase modulation circuit 13 as a biphase clock signal having a frequency of 15.36 kHz. The bi-phase modulation circuit 13 is also supplied with ADIP (Address In Pre-groove) data in the frame format shown in FIG.

  The biphase modulation circuit 13 biphase modulates the biphase clock supplied from the divider 12 with ADIP data (address data) supplied from a circuit (not shown), and outputs the biphase signal to the FM modulation circuit 15. is doing. The FM modulation circuit 15 also receives a carrier having a frequency of 57.6 kHz obtained by dividing the 115.2 kHz signal generated by the generation circuit 11 by the value 2 by the divider 14. The FM modulation circuit 15 modulates the frequency of the carrier input from the divider 14 with the biphase signal input from the biphase modulation circuit 13 and outputs a frequency modulation signal obtained as a result. The left and right side walls of the pregroove 2 of the disk 1 are formed (wobbed) corresponding to this frequency modulation signal.

  14 and 15 show examples of the biphase signal output from the biphase modulation circuit 13. In this embodiment, when the preceding bit is 0, as shown in FIG. 14, “11101000” is used as the synchronization pattern (SYNC), and when the preceding bit is 1, the synchronization pattern is As shown in FIG. 15, “00010111” having a phase opposite to that shown in FIG. 14 is used. SYNC is a unique pattern that does not appear in modulation.

  Of the data bits (Data Bits) of the address data (ADIP data), “0” is bi-phase modulated, and “11” (when the previous channel bit is 0) or “00” (the previous channel bit is 1). ) Is converted into channel bits. Also, “1” is converted into a channel bit of “10” (when the previous channel bit is 0) or “01” (when the previous channel bit is 1). Which of the two patterns is converted depends on the previous code. That is, the “Wave Form” (waveform) in FIGS. 14 and 15 represents a channel bit pattern of 1 and 0 as a high level signal of 1 and a low level signal of 0, but this waveform is continuous. Thus, one of the two patterns is selected.

  The FM modulation circuit 15 frequency-modulates the carrier supplied from the divider 14 as shown in FIG. 16 in response to the biphase signal as shown in FIG.

  That is, when the channel bit data (biphase signal) is 0, the FM modulation circuit 15 outputs 3.5-wave carriers in a period corresponding to half the length of one data bit. The 3.5-wave carrier starts from a positive half wave or a negative half wave.

  On the other hand, when the channel bit data (biphase signal) is 1, four-wave carriers are output in a period corresponding to half the length of one data bit. These four wave carriers are also carriers starting from a positive half wave or carriers starting from a negative half wave.

  Accordingly, when the channel data bit 00 is input corresponding to the data 0, the FM modulation circuit 15 generates 7 (= 3.5 + 3.5) frequency modulation waves in the period corresponding to the length of the data bit. When channel data bit 11 is input, 8 frequency (= 4 + 4) frequency modulation waves are output. When channel data bits 10 or 01 are input corresponding to data 1, 7.5 frequency (= 4 + 3.5 = 3.5 + 4) frequency modulation waves are output.

  The carrier of 57.6 kHz inputted to the FM modulation circuit 15 corresponds to 7.5 waves, and the FM modulation circuit 15 corresponds to the data of this 7.5 waves, or ± 6 Generate 7 or 8 frequency modulated waves shifted by .67% (= 0.5 / 7.5).

  As described above, the carrier starting from the positive half wave and the carrier starting from the negative half wave corresponding to channel data 0 and channel data 1 are selected to be continuous with the previous signal.

  FIG. 17 shows an example of the frequency modulation wave output from the FM modulation circuit 15 in this way. In this example, the first data bit is 0 and the channel data bit is 00. For the first channel data bit 0, a carrier of 3.5 waves starting from a positive half wave from the start point is selected. As a result, the end point of the carrier ends with a positive half wave. Therefore, 3.5 waves starting from the negative half wave are selected for the next channel data bit 0, and a total of 7 frequency modulation waves are selected for data bit 0.

  This data bit 0 is followed by data bit 1 (channel bit 10). Since the 3.5 wave of channel data bit 0 corresponding to the previous data bit 0 ends in the negative half wave, the carrier of the four waves of the first channel data bit 1 corresponding to data bit 1 is Those starting with a positive half-wave are selected. Since the four waves of channel data bit 1 end with a negative half wave, the next four waves of channel data bit 0 are selected starting from the positive half wave.

  In the same manner, 7.5 waves, 8 waves, and 7 waves corresponding to data bit 1 (channel data bit 10), data bit 0 (channel data bit 11), and data bit 0 (channel data bit 00). Carriers are formed and output so as to be continuous at the boundary portion (start point and end point) of data bits.

  As shown in FIG. 17, in this embodiment, the length of the channel bit is an integral multiple of 1/2 of the wavelength of the carrier in any of the 7-wave, 7.5-wave, and 8-wave carriers. It is said that the length. That is, the length of the channel bit is 7 times the wavelength of 7-wave carrier (frequency-modulated wave) and 8 times the half of 8-wave carrier (frequency-modulated wave). It is said that the length. The length of the channel bit is 7 times 1/2 of the wavelength of the carrier of 7.5 waves (when the channel bit is 0) or 8 times (when the channel bit is 1).

  Further, in this embodiment, the boundary portion (end point or start point) of the channel bits subjected to biphase modulation is the zero cross point of the frequency modulated wave. As a result, the phase of the address data (channel bit data) and the frequency modulation wave coincide with each other, the boundary between the bits can be easily identified, and the erroneous detection of the address data bits can be prevented. Accurate reproduction is facilitated.

  In this embodiment, the boundary portion (start point and end point) of the data bit corresponds to the edge (zero cross point) of the frequency modulation wave. As a result, the clock can be generated with reference to the edge of the frequency modulation wave. However, in this embodiment, as will be described later with reference to FIG. 18, the clock is generated with reference to the clock synchronization mark.

  Such a disc 1 can also be manufactured by the recording apparatus having the configuration shown in FIG.

  However, in this embodiment, as shown in FIGS. 18A to 18D, the channel bit data is 00 (data 0), 11 (data 0), 10 (data 1), or 01 (data 1). At a certain time, a clock synchronization mark having a frequency higher than the modulation frequency (57.6 kHz) of the address information is synthesized at the zero cross point of the carrier at the center of each data (channel bit switching point). This clock synchronization mark is recorded for each data bit or for every predetermined number of data bits (for example, every 4 data bits that are 1 bit less than the case shown in FIG. 3 (with an interval of 3 data bits)). . As a result, as shown in FIG. 12, the clock synchronization mark area (12-bit sync mark area) shown in FIG. 2 becomes unnecessary.

  In this way, by inserting the clock synchronization mark at the zero crossing point of the wobbling frequency modulation wave corresponding to the center of the address data bit (channel data bit switching point), the fluctuation in the amplitude of the clock synchronization mark is reduced, and the detection thereof is reduced. It becomes easy.

  That is, in the FM modulation circuit 15, when the channel data bit is 0, frequency modulation is performed such that the frequency is shifted by -5% from the center frequency, and when the channel data bit is 1, the frequency is shifted by + 5% from the center frequency. When frequency modulation is performed, the boundary between the data bits or channel data bits and the zero cross point of the frequency modulation wave do not match, and channel data bits (or data bits) are easily detected erroneously. The insertion position of the clock synchronization mark is not necessarily a zero cross point, but is superimposed on a point having a predetermined amplitude value of the frequency modulated wave. As a result, the level of the clock synchronization mark increases or decreases by the amount of the amplitude value, making it difficult to detect. According to the present embodiment, the clock synchronization mark is always arranged at the zero-cross position of the frequency modulation wave, so that it can be easily detected (identified from the frequency modulation wave).

  FIG. 19 shows a configuration example of an optical disc recording / reproducing apparatus for recording / reproducing data on / from the disc 1 thus obtained. The basic configuration is the same as in FIG. 8, but in this embodiment, a ROM 47 is further added.

  In the ROM 47, a table that defines the correspondence between the track number in the address frame (FIG. 12) and the zone in which the data recording area of the disk 1 is divided, and if necessary, the zone and the band to which the zone corresponds are stored. A table defining the relationship is stored.

  That is, the control circuit 38 records or reproduces data by dividing the disc 1 into a plurality of zones (in this embodiment, m + 2 zones from the 0th zone to the m + 1th zone) as shown in FIG. . Now, the data frame per track in the 0th zone (this data frame is different from the address frame described with reference to FIGS. 2 and 12, and the data frame as described with reference to FIGS. 10 and 11). In the next first zone, the number of data frames per track is n + 8, where n is the number of blocks. In the same manner, the number of data frames in the outermost zone increases by 8 compared to the adjacent inner zone, and n + 8 × (m + 1) data frames in the m + 1th outermost zone. Number.

  The first zone is switched from a radial position where a capacity of n + 8 frames is obtained with the same linear density as the innermost circumference linear density of the zeroth zone. Similarly, the mth zone is the mth zone from the radial position where the capacity of n + 8 × m frames can be obtained with the same linear density as the innermost circumferential line density of the 0th zone.

  For example, if the radius of the disc 1 having a diameter of 120 mm is in the range of 24 mm to 58 mm as the recording / reproducing area, the track pitch is 0.87 μm, and the linear density is about 0.39 μm / bit, the recording / reproducing area is shown in FIG. As shown, it is divided into 92 zones from zone 0 to zone 91. In the 0th zone with a disc radius of 24 mm, there are 520 frames per track (one rotation), and 8 frames are increased per track as the zone is incremented by one. Detailed parameters of each zone are shown in FIGS.

  As will be described later, in this embodiment, since one sector is composed of 24 frames (data frames), the number of frames incremented for each zone (= 8) is the number of frames constituting this one sector. That is, it is set to a value smaller than (= 24). As a result, many zones can be formed in finer units, and the capacity of the disk 1 can be increased. This method is called zone CLD (Zoned Constant Linear Dencity).

  22 to 25, the data in each column includes the zone number, radius, number of frames per track, number of tracks per zone, number of recording / playback units (blocks) per zone (number of clusters), The shortest linear density in the zone, the capacity of the zone, the first rotational speed of the zone, the minimum linear speed of the zone at the first rotational speed, the maximum linear speed of the zone at the first rotational speed, the It represents the second rotational speed of the zone, the minimum linear speed of the zone at the second rotational speed, or the maximum linear speed of the zone at the second rotational speed, respectively. The first rotational speed represents the rotational speed of CAV per minute when the data transfer rate is 11.08 Mbps. The second rotation speed is the same as that for 4 Zoned CLD divided into 4 rotation bands when the bands are configured so that the change in linear velocity in each band is the same in each band. Represents the number of revolutions.

  In this embodiment, the number of tracks in each zone is fixed at 424, and this number of tracks is the number of frames of one recording / playback unit (the number of frames of an ECC block (cluster)) (described later with reference to FIG. 30). )).

  In this embodiment, the number of tracks in each zone is one times the number of data frames (424 frames) constituting the recording / reproducing unit, but can be an integral multiple. As a result, no excessive data frame is generated, and an integer number of recording / reproduction units (blocks) are arranged in each zone, so that zoning efficiency can be improved. As a result, a capacity larger than the zone CAV and smaller than the zone CLV but close to the zone CLV can be obtained.

  In addition, by performing zoning close to CLV in this way, the change in the clock frequency between the zone and the next zone becomes small, and even when the playback is performed by a playback device dedicated to CLV, even between zones where the clock frequency changes. The clock can be extracted and the zones can be reproduced continuously.

  Next, the operation of the embodiment of FIG. 19 will be described. Here, the operation at the time of data recording will be described. The optical head 32 irradiates the optical disk 1 with laser light and outputs an RF signal (wobbling signal) obtained from the reflected light. The frame address detection circuit 37 reads the frame address (frame number) from the wobbling signal, outputs the read result to the control circuit 38, and supplies it to the cluster counter 46. The wobbling signal is also input to the mark detection circuit 36, where a clock synchronization mark is detected, and the detection result is supplied to the mark period detection circuit 40.

  The mark period detection circuit 40 determines the periodicity of the clock synchronization mark, generates a predetermined pulse corresponding thereto, and outputs it to the PLL circuit 41. The PLL circuit 41 generates a clock (recording clock) synchronized with this pulse and supplies it to the cluster counter 46.

  The control circuit 38 can detect the position of the reference clock synchronization mark in one track (one rotation) from the frame address (frame number) supplied from the frame address detection circuit 37. For example, an arbitrary position on the track (an arbitrary position during one rotation) can be accessed from the count value of the recording clock with reference to the clock synchronization mark detected at the beginning of the frame of frame number 0 (address frame). It becomes possible.

  As described above, when an arbitrary position on the track is accessed, it is necessary to determine which zone the access point belongs to and generate a clock having a frequency corresponding to the zone in the VCO 44. . Therefore, the control circuit 38 further executes a clock switching process as shown in the flowchart of FIG.

  That is, first in step S 1, the control circuit 38 reads the track number from the frame address of the access point output by the frame address detection circuit 37. In step S 2, the zone corresponding to the track number read in step S 1 is read from the table stored in the ROM 47. As described above, in the table of the ROM 47, it is stored in advance which of the 0th zone to the 91st zone each numbered track belongs.

  Accordingly, in step S3, it is determined whether or not the track number just read is a new zone different from the zone accessed so far. If it is determined that the zone is a new zone, the process proceeds to step S4, and the control circuit 38 controls the frequency divider 45 to set a frequency division ratio corresponding to the new zone. As a result, a recording clock having a different frequency for each zone is output from the VCO 44.

  If it is determined in step S3 that the current zone is not a new zone, the process in step S4 is skipped. That is, the frequency division ratio of the frequency divider 45 is not changed and is left as it is.

  Next, the format of the recording data will be described. In this embodiment, one cluster is composed of 32 kbytes, and data is recorded with this cluster as a unit. This cluster is composed as follows.

  That is, 2 kbytes (2048 bytes) of data is extracted as one sector of data, and an overhead of 16 bytes is added thereto as shown in FIG. This overhead includes a sector address (an address generated or read by the address generation and reading circuit 35 in FIG. 19), an error detection code for error detection, and the like.

  The total of 2064 (= 2048 + 16) bytes of data is 12 × 172 (= 2064) bytes of data as shown in FIG. Then, 16 pieces of data corresponding to one sector are collected to obtain 192 (= 12 × 16) × 172 bytes of data. A 10-byte inner code (PI) and a 16-byte outer code (PO) are added to the 192 × 172 bytes of data as parity for each byte in the horizontal and vertical directions.

  Further, of the data thus blocked into 208 (= 192 + 16) × 182 (= 172 + 10) bytes, the 16 × 182 byte outer code (PO) is divided into 16 1 × 182 byte data. Then, as shown in FIG. 29, one by one is added below the 16 sector data of number 0 to number 15 of 12 × 182 bytes, and interleaved. Then, 13 (= 12 + 1) × 182 bytes of data is used as one sector of data.

  Furthermore, as shown in FIG. 30, the 208 × 182 byte data shown in FIG. 29 is divided into two in the vertical direction, and one frame is 91 bytes of data, and 208 × 2 frames of data. Then, 2 × 4 frame link data (link area data) is added to the head of the 208 × 2 frame data (more accurately, as will be described later with reference to FIG. 31) Part of the data is recorded at the beginning of the cluster and the rest is recorded at the end of the cluster). A 2-byte frame synchronization signal (FS) is further added to the head of the 91-byte frame data. As a result, as shown in FIG. 30, the data for one frame is 93 bytes in total, and the data is a total of 212 (= 208 + 4) × (93 × 2) bytes (424 frames). This is data for one cluster (a block as a recording unit). The size of the actual data portion excluding the overhead portion is 32 kbytes (= 2048 × 16/1024 kbytes).

  That is, in this embodiment, one cluster is composed of 16 sectors, and one sector is composed of 24 frames.

  Since such data is recorded on the disk 1 in units of clusters, a link area is arranged between the clusters as shown in FIG.

  As shown in FIG. 31, the link area (Linking Frame) consists of 8 data frames and is inserted between 32 kbyte data blocks. Each cluster is a link area in front of a 32 kbyte data block, such as slice / PLL data or link data such as frame synchronization signals SY1 to SY7, a 32 kbyte data block, and a link area behind a 32 kbyte data block. It consists of postamble and postguard.

  Slice is data for setting a time constant for binarizing reproduction data, and PLL is data for reproducing a clock. The frame synchronization signals (frame sync) SY1 to SY7 are selected and added from states 1 to 4 as will be described later with reference to FIG.

  In the postamble, data for adjusting the mark length of the last data and returning the signal polarity is recorded. The post guard is an area that absorbs recording jitter that occurs according to the eccentricity of the disk, the recording sensitivity of the disk, and the like. Further, the post guard prevents the data from interfering with the next recorded link area even when the data recording start position is changed as will be described later. In the case where there is no jitter at all and the DPS (Data Position Shift) described later is 0 byte, the post guard is recorded by being overlapped with the next data by 8 bytes.

  The synchronization signal (sync) is 4-byte data and is a signal for synchronization. The last 4 bytes of the link area are reserved for future use.

  In each cluster, recording of information is started from the start point (Start Point), and the recording is ended when the start point is exceeded by 8 bytes (overlap). Further, at the time of recording, the recording / reproducing circuit 33 randomly selects any value from 0 to 64 bytes as the DPS, and the link area data and the 32 kbyte block data according to the selected DPS value. Change the recording position.

  As shown in an enlarged view in FIG. 31, for example, when 0 byte is selected as the DPS, 14-byte link data is added before the first frame synchronization signal SY2 in the front link area, and the rear After the last frame synchronization signal SY7 in the link area, 85 bytes of link data is added.

  When 32 bytes are selected as the DPS, 46 bytes of link data are added before the first frame synchronization signal SY2 in the front link area, and after the last frame synchronization signal SY7 in the rear link area, 53-byte link data is added.

  Further, when 64 bytes are selected as the DPS, 78 bytes of link data are added before the first frame synchronization signal SY2 in the front link area, and after the last frame synchronization signal SY7 in the rear link area, 21-byte link data is added.

  As described above, the position where the link data and the 32 kbyte data block are recorded changes in accordance with the value of the DPS selected by the recording / reproducing circuit 33. Therefore, for example, when information is recorded on a phase change disk or the like, it is possible to prevent the same data (for example, a frame synchronization signal or the like) from being repeatedly recorded on the same part of the disk. At that time, since the start point is fixed, the recording timing can be generated in the same manner as in the prior art.

  FIG. 32 shows the structure of each frame and frame synchronization signal when the disk is a ROM disk (playback-only disk) or a RAM disk (rewritable disk). In the ROM disk, one sector is composed of 13 row data, that is, 26 frames, and frame synchronization signals SY0 to SY7 are added to the head of each frame.

  In the case of a RAM disk, an 8-frame link area is added after 13 rows of data, that is, 26 frames of data, followed by 26 frames of data. The configuration (array) of the frame synchronization signal in the data area of the RAM disk and the frame synchronization signal in the data area of the ROM disk are the same. Further, the frame synchronization signal in the link area of the RAM disk has the same configuration (array) as the last part of the frame synchronization signal in the data area. That is, the link areas SY1 to SY4 and SY7 have the same pattern as the 10th to 13th lines of the data area. With such a configuration, the RAM disk can be reproduced even by a reproduction apparatus dedicated to the ROM disk.

  That is, in the reproduction apparatus dedicated to the ROM disk, eight frame synchronization signals SY1, SY7, SY2, SY7, SY3, SY7, SY4, SY7 stored in the 10th to 13th rows of the data block are detected. Then, since it is made to recognize that the next data is the head part of the data block, by storing these eight frame synchronization signals in the link area, the data area following the link area is stored. The head can be recognized by the playback device.

  FIG. 33 shows an example of the frame synchronization signals SY0 to SY7 shown in FIG. The frame synchronization signal is 2 bytes of data, but in this embodiment, the data after conversion into channel bit data is shown, so the data length of each frame synchronization signal is 32 bits (4 bytes). It has become. For example, there are four types of states 1 to 4 in SY0, and when added to 91-byte frame data (see FIG. 20), data in a state where DSV (Digital Sum Value) is minimized. Is selected and added as a frame synchronization signal.

  FIG. 34 shows another configuration example of the recording / reproducing apparatus. In this embodiment, the track address detection circuit 48 detects the track address (track number) from the wobbling signal output from the optical head 32 and outputs it to the control circuit 38.

  The address generation / read circuit 35 detects a frame synchronization signal FS (frame sync) in the data, and outputs the detection result to the frame sync (FS) counter 49. The FS counter 49 counts the FS detection pulses output from the address generation reading circuit 35 and outputs the count value to the control circuit 38. The control circuit 38 is also supplied with a detection signal from the mark detection circuit 36.

Other configurations are the same as those in FIG.

  When the point to be accessed is acquired by the sector number, the control circuit 38 performs processing for replacing the sector number with the track number and the data frame number in the track. That is, in the ROM 47, for example, as shown in FIG. 35, there is a table showing the correspondence between sector numbers, zone numbers, ECC block numbers, number of frames per zone, track numbers, number of frames per track, and the like. It is remembered. The control circuit 38 refers to this table and reads the track number corresponding to the designated sector number and the number of data frames in the track. Then, the control circuit 38 reads the track number from the output of the track address detection circuit 48.

  That is, the track address detection circuit 48 detects the track address (track number) from the wobbling signal output from the optical head 32. As described with reference to FIG. 12, the track address (track number) is recorded in the 48-bit wobbling address frame. The track address detection circuit 48 detects this track number and outputs it to the control circuit 38.

  When a desired track number is detected by the track address detection circuit 48, the control circuit 38 next detects the reference position of the track.

  That is, as shown in FIG. 36, a track number is recorded on the disc 1 as wobbling information, and a clock synchronization mark is recorded in an address frame of each track at a cycle of 4 bits. The control circuit 38 is inserted into the first bit of 48 bits of the first address frame (number 0 address frame in the example of FIG. 36) of the track (number 0 track). Is detected as a reference clock synchronization mark.

  Further, the control circuit 38 resets the count value of the FS counter 49 when one reference clock synchronization mark is detected for one track circumference. Thereafter, the FS counter 49 counts when a frame synchronization signal is detected. When the count value of the FS counter 49 becomes a value corresponding to the sector number to be searched, the sector is detected as a sector to be searched.

  Then, when the recording of the predetermined sector is started, the control circuit 38 sets the recording start position of the recording of the sector to a range of (0 to 2) ± 4 bytes from the timing of the zero cross of the reference clock synchronization mark. Control to be. This makes it possible to perform access in units of tracks and data frames.

  The length (number of bytes) of each area in the above embodiment is an example, and a predetermined value can be set as appropriate.

It is a figure explaining the state by which the optical disk of this invention was wobbled. It is a figure which shows the structural example of a wobbling address frame. It is a figure which shows a clock synchronization mark area and a clock synchronization mark. It is a figure which shows the structural example of a wobbling address generation circuit. FIG. 5 is a diagram illustrating an example of a biphase signal output from the biphase modulation circuit 13 of FIG. 4. It is a figure which shows the other example of the biphase signal which the biphase modulation circuit of FIG. 4 outputs. It is a block diagram which shows the structural example of the recording device for manufacturing the disk 1 which has a pre-groove. It is a block diagram which shows the structural example of the optical disk recording / reproducing apparatus of this invention. It is a figure which shows the example of the sector format of the proposed high density CD-ROM. It is a figure which shows the structural example of the ECC block of a cluster. It is a figure which shows the structural example of a link area. It is a figure which shows the other structural example of a wobbling address frame. It is a figure which shows the other structural example of a wobbling signal generation circuit. It is a figure which shows the example of the biphase signal which the biphase modulation circuit 13 of FIG. 13 outputs. It is a figure which shows the other example of the biphase signal which the biphase modulation circuit 13 of FIG. 13 outputs. It is a figure explaining the frequency modulation which FM modulation circuit 15 of FIG. 13 performs. It is a figure which shows the frequency modulation wave which the FM modulation circuit 15 of FIG. 13 outputs. It is a figure explaining the operation | movement of the synthetic | combination circuit 22 of FIG. It is a block diagram which shows the other structural example of the optical disk recording / reproducing apparatus of this invention. It is a figure explaining the zone in a disc. It is a figure explaining the specific example of the zone in a disk. It is a figure explaining the parameter of each zone. It is a figure explaining the parameter of each zone. It is a figure explaining the parameter of each zone. It is a figure explaining the parameter of each zone. 20 is a flowchart for explaining clock switching processing in the embodiment of FIG. It is a figure explaining the format of the data for 1 sector. It is a figure explaining the structure of 32 kbytes data. It is a figure explaining the state which interleaved the outer code | symbol of FIG. It is a figure explaining the structure of the data of a block of 32k bytes. It is a figure which shows the structural example of a link area. It is a figure explaining the synchronizing signal of a ROM disk and a RAM disk. It is a figure explaining the pattern of a synchronizing signal. It is a block diagram which shows the further another structural example of the optical disk recording / reproducing apparatus of this invention. It is a figure which shows the example of the table memorize | stored in ROM47 in FIG. It is a figure explaining the operation | movement of the Example of FIG.

Explanation of symbols

  1 optical disk, 2 pregroove, 11 generation circuit, 12, 14 divider, 13 biphase modulation circuit, 15 FM modulation circuit, 21 wobbling signal generation circuit, 22 synthesis circuit, 23 mark signal generation circuit, 24 recording circuit, 25 Optical head, 26 master disk, 27 spindle motor, 31 spindle motor, 32 optical head, 33 recording / reproducing circuit, 34 memory, 35 address generation reading circuit, 36 mark detection circuit, 37 frame address detection circuit, 38 control circuit, 39 thread motor , 40 mark period detection circuit, 41 PLL circuit, 42 phase comparator, 43 LPF, 44 VCO, 45 frequency divider, 46 cluster counter, 47 ROM, 48 track address detection circuit, 49 FS counter

Claims (5)

In an optical disc having a pregroove formed in a spiral shape or concentric shape, a track for recording data is formed in advance.
The pregroove includes a plurality of wobbling frames,
In the wobbling frame,
A predetermined number of bits in the first first area are wobbled to represent a synchronization signal,
The predetermined number of bits in the second area after the first area is wobbled to indicate which of the plurality of recording layers is,
The predetermined number of bits in the third area after the second area is wobbling corresponding to an address indicating which of the plurality of recording units included in the recording layer. An optical disc. The optical disk according to claim 1, wherein the wobbling frame further includes a fourth area wobbled so as to represent an error correction code in an area after the third area. The optical disc according to claim 1, wherein the wobbling frame further includes a clock synchronization mark area including a clock synchronization mark in an area after the third area. A track for recording data is formed in advance and has a pregroove formed in a spiral shape or a concentric shape, and the pregroove includes a plurality of wobbling frames, and the wobbling frame has a predetermined first region in the first area The number of bits is wobbled to represent the synchronization signal, and the predetermined number of bits in the second area after the first area represents which of the plurality of recording layers The predetermined number of bits in the third area after the second area is wobbled in correspondence with an address indicating which of the plurality of recording units is included in the recording layer. In an optical disc recording apparatus for recording data on an optical disc,
Recording / reproducing means for reproducing second data necessary for recording the first data on the optical disc from the optical disc, and recording the first data on the optical disc;
Control means for controlling the recording / reproducing means, and
The recording / reproducing means separates address data including information indicating a recording position of the plurality of recording layers from the reproduced second data. And
The said control means controls recording of the said 1st data to the said optical disk by the said recording / reproducing means based on the said address data. The optical disk recording device characterized by the above-mentioned. A track for recording data is formed in advance and has a pregroove formed in a spiral shape or a concentric shape, and the pregroove includes a plurality of wobbling frames, and the wobbling frame has a predetermined first region in the first area The number of bits is wobbled to represent the synchronization signal, and the predetermined number of bits in the second area after the first area represents which of the plurality of recording layers The predetermined number of bits in the third area after the second area is wobbled in correspondence with an address indicating which of the plurality of recording units is included in the recording layer. In an optical disc recording method of an optical disc recording apparatus for recording data on an optical disc,
Second data necessary for recording the first data on the optical disc is reproduced from the optical disc,
From the reproduced second data, the recording position of the data separates address data including information indicating which one of a plurality of recording layers,
An optical disk recording method comprising: controlling recording of the first data onto the optical disk based on the separated address data.

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