JP4557272B2 - Recording / reproducing apparatus and method - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a recording / reproducing apparatus and method, and in particular, even in a state where data is recorded discontinuously on a CLV disc in which addresses are recorded by wobbling and both recording and reproduction are possible. The present invention relates to a recording / reproducing apparatus and method capable of accurately controlling the rotation of a disc and accurately reproducing recorded data.
[0002]
[Prior art]
In an optical disc capable of both recording and reproduction, grooves and lands are formed in a spiral shape or concentric shape so that tracking control can be performed even when data is not recorded, at least one of which is A track for recording or reproducing data. The edge of the groove or land is wobbled by an FM signal obtained by frequency-modulating a predetermined carrier corresponding to the address information. Such an optical disc can be randomly accessed, and data may be recorded intermittently without being sequentially (continuously) recorded. In such a case, the data is intermittently scattered in a track shape.
[0003]
By the way, in a reproduction apparatus for a reproduction-only disk such as a compact disk (CD), and particularly in an inexpensive reproduction apparatus, recorded data is reproduced and a clock is generated from the reproduction data to control the rotation of the disk. Play. Then, so-called CLV reproduction is performed in which the rotation of the spindle motor that drives the disk is controlled so that the clock has a constant frequency and phase.
[0004]
[Problems to be solved by the invention]
In such a playback apparatus that performs CLV playback, when playing back an optical disc that can be recorded and played back, playback data can be obtained only partially when a track on which data is recorded intermittently is played back. The clock could not be reproduced, and eventually the rotation of the optical disk could not be accurately controlled, and in the worst case, the spindle motor could run away.
[0005]
The present invention has been made in view of such a situation, and makes it possible to accurately control the rotation of a disc even when data is recorded intermittently.
[0006]
[Means for Solving the Problems]
  The recording / reproducing apparatus according to claim 1 includes a detecting means for detecting a recording / reproducing unit in which no data is recorded in a predetermined area of the track in a recording medium on which data is recorded on a part of the track, and detection When the means detects a recording / playback unit in which no data is recorded,Frame sync signal andRecording means for recording dummy data.
[0007]
  Claim8The recording / reproducing method described in 1) detects a recording / reproducing unit in which data is not recorded in a predetermined area of the track in a recording medium in which data is recorded on a part of the track, and recording in which data is not recorded. When a playback unit is detected, the unitFrame sync signal andIt is characterized by recording dummy data.
[0008]
  A recording / reproducing apparatus according to claim 1 and a claim8In the recording / reproducing method described in 1), when a recording / reproducing unit in which no data is recorded is detected in a recording medium on which data is recorded in a part of a track, the recording / reproducing unit is used.Frame sync signal andDummy data is recorded.
[0009]
DETAILED DESCRIPTION OF THE INVENTION
FIG. 1 shows a configuration example of an optical disc used in the recording / reproducing apparatus of the present invention. As shown in the figure, a pregroove 2 is formed in advance in a spiral shape on the disk (optical disk) 1 from the inner periphery to the outer periphery. Of course, the pregroove 2 can also be formed concentrically.
[0010]
Further, as shown in FIG. 1 in which a part of the pregroove 2 is enlarged, the left and right side walls are wobbled corresponding to the address information and meandering corresponding to the frequency modulation wave. One track has a plurality of wobbling address frames.
[0011]
FIG. 2 shows the configuration (format) of the wobbling address frame. As shown in the figure, the wobbling address frame is composed of 48 bits, and the first 4 bits are a synchronization signal (Sync) indicating the start of the wobbling address frame. The next 4 bits are a layer (Layer) that indicates which of a plurality of recording layers. The next 20 bits are used as a track address (track number). Further, the next 4 bits represent the frame number of the address frame. The subsequent 14 bits are used as an error detection code (CRC), and an error detection code for data excluding the synchronization signal (Sync) is recorded.
The last 2 bits (Reserved) are reserved for the future.
[0012]
The wobbling address frame is recorded in a CAV disk shape in which the rotational angular velocity of the disk is constant, for example, for 8 address frames per track (1 rotation). Therefore, for example, values of 0 to 7 are recorded as the frame numbers in FIG.
[0013]
FIG. 3 shows a configuration example of a wobbling signal generation circuit that generates a wobbling signal for wobbling the pregroove 2 corresponding to the address frame having the format shown in FIG. The generation circuit 11 generates a signal having a frequency of 115.2 kHz. The signal generated by the generation circuit 11 is supplied to the division circuit 12, divided by the value 7.5, and then supplied to the biphase modulation circuit 13 as a biphase clock signal having a frequency of 15.36 kHz. The bi-phase modulation circuit 13 is also supplied with ADIP (Address In Pre-groove) data in the frame format shown in FIG.
[0014]
The biphase modulation circuit 13 biphase modulates the biphase clock supplied from the divider 12 with ADIP data (address data) supplied from a circuit (not shown), and outputs the biphase signal to the FM modulation circuit 15. is doing. The FM modulation circuit 15 also receives a carrier having a frequency of 57.6 kHz obtained by dividing the 115.2 kHz signal generated by the generation circuit 11 by the value 2 by the divider 14. The FM modulation circuit 15 modulates the frequency of the carrier input from the divider 14 with the biphase signal input from the biphase modulation circuit 13 and outputs a frequency modulation signal obtained as a result. The left and right side walls of the pre-groove 2 of the disk 1 are formed (wobbed) corresponding to this frequency modulation signal.
[0015]
4 and 5 show examples of the biphase signal output from the biphase modulation circuit 13. In this embodiment, when the preceding bit is 0, as shown in FIG. 4, “11101000” is used as the synchronization pattern (SYNC), and when the preceding bit is 1, the synchronization pattern is As shown in FIG. 5, “00010111” having a phase opposite to that shown in FIG. 4 is used. SYNC is a unique pattern that does not appear in modulation.
[0016]
Of the data bits (Data Bits) of the address data (ADIP data), “0” is bi-phase modulated and is “11” (when the previous channel bit is 0) or “00” (the previous channel bit is 1). ) Is converted into channel bits. Also, “1” is converted into a channel bit of “10” (when the previous channel bit is 0) or “01” (when the previous channel bit is 1). Which of the two patterns is converted depends on the previous code. That is, the “Wave Form” (waveform) in FIGS. 4 and 5 represents a channel bit pattern of 1, 0 as a high level signal of 1 and a low level signal of 0. This waveform is continuous. Thus, one of the two patterns is selected.
[0017]
The FM modulation circuit 15 frequency-modulates the carrier supplied from the divider 14 as shown in FIG. 6 in response to the biphase signal as shown in FIG. 4 or FIG.
[0018]
That is, when the channel bit data (biphase signal) is 0, the FM modulation circuit 15 outputs 3.5-wave carriers in a period corresponding to half the length of one data bit. The 3.5-wave carrier starts from a positive half wave or a negative half wave.
[0019]
On the other hand, when the channel bit data (biphase signal) is 1, four-wave carriers are output in a period corresponding to half the length of one data bit. These four wave carriers are also carriers starting from a positive half wave or carriers starting from a negative half wave.
[0020]
Accordingly, when the channel data bit 00 is input corresponding to the data 0, the FM modulation circuit 15 generates 7 (= 3.5 + 3.5) frequency modulation waves in the period corresponding to the length of the data bit. When channel data bit 11 is input, 8 frequency (= 4 + 4) frequency modulation waves are output. When channel data bits 10 or 01 are input corresponding to data 1, 7.5 frequency (= 4 + 3.5 = 3.5 + 4) frequency modulation waves are output.
[0021]
The carrier of 57.6 kHz inputted to the FM modulation circuit 15 corresponds to 7.5 waves, and the FM modulation circuit 15 corresponds to the data of this 7.5 waves, or ± 6 Generate 7 or 8 frequency modulated waves shifted by .67% (= 0.5 / 7.5).
[0022]
As described above, the carrier starting from the positive half wave and the carrier starting from the negative half wave corresponding to channel data 0 and channel data 1 are selected to be continuous with the previous signal.
[0023]
FIG. 7 shows an example of the frequency modulated wave output from the FM modulation circuit 15 in this way. In this example, the first data bit is 0 and the channel data bit is 00. For the first channel data bit 0, a carrier of 3.5 waves starting from a positive half wave from the start point is selected. As a result, the end point of the carrier ends with a positive half wave. Therefore, 3.5 waves starting from the negative half wave are selected for the next channel data bit 0, and a total of 7 frequency modulation waves are selected for data bit 0.
[0024]
This data bit 0 is followed by data bit 1 (channel bit 10). Since the 3.5 wave of channel data bit 0 corresponding to the previous data bit 0 ends in the negative half wave, the carrier of the four waves of the first channel data bit 1 corresponding to data bit 1 is Those starting with a positive half-wave are selected. Since the four waves of channel data bit 1 end with a negative half wave, the next four waves of channel data bit 0 are selected starting from the positive half wave.
[0025]
In the same manner, 7.5 waves, 8 waves, and 7 waves corresponding to data bit 1 (channel data bit 10), data bit 0 (channel data bit 11), and data bit 0 (channel data bit 00). Carriers are formed and output so as to be continuous at the boundary portion (start point and end point) of data bits.
[0026]
As shown in FIG. 7, in this embodiment, the length of the channel bit is an integral multiple of 1/2 of the wavelength of the carrier in any of the 7-wave, 7.5-wave, and 8-wave carriers. It is said that the length. That is, the length of the channel bit is 7 times the wavelength of 7-wave carrier (frequency-modulated wave) and 8 times the half of 8-wave carrier (frequency-modulated wave). It is said that the length. The length of the channel bit is 7 times 1/2 of the wavelength of the carrier of 7.5 waves (when the channel bit is 0) or 8 times (when the channel bit is 1).
[0027]
Further, in this embodiment, the boundary portion (end point or start point) of the channel bits subjected to biphase modulation is the zero cross point of the frequency modulated wave. As a result, the phase of the address data (channel bit data) and the frequency modulation wave coincide with each other, the boundary between the bits can be easily identified, and the erroneous detection of the address data bits can be prevented. Accurate reproduction is facilitated.
[0028]
In this embodiment, the boundary portion (start point and end point) of the data bit corresponds to the edge (zero cross point) of the frequency modulation wave. As a result, the clock can be generated with reference to the edge of the frequency modulation wave. However, in this embodiment, as will be described later with reference to FIG. 9, the clock is generated based on the clock synchronization mark.
[0029]
FIG. 8 shows a configuration example of a recording apparatus (disk forming apparatus) for manufacturing the disk 1 having pregrooves. The wobbling signal generation circuit 21 has the configuration shown in FIG. 3 described above, and supplies the frequency modulation signal output from the FM modulation circuit 15 to the synthesis circuit 22. The mark signal generation circuit 23 generates a clock synchronization mark signal at a predetermined timing and outputs it to the synthesis circuit 22. The synthesizing circuit 22 synthesizes the frequency modulation signal output from the wobbling signal generation circuit 21 and the clock synchronization mark signal output from the mark signal generation circuit 23 and outputs the synthesized signal to the recording circuit 24.
[0030]
When the clock synchronization mark signal is supplied, the synthesis circuit 22 synthesizes the clock synchronization mark (Fine Clock Mark) with the carrier supplied from the wobbling signal generation circuit 21 as shown in FIG. When the recording / reproduction data is modulated by EFM (Eight To Fourteen Modulation: (8-14) modulation) + such as DVD, the length of the clock synchronization mark is 6 to 14T (T is the length of the bit cell). It is assumed.
[0031]
That is, as shown in FIGS. 9A to 9D, when the channel bit data is 00 (data 0), 11 (data 0), 10 (data 1) or 01 (data 1), the respective data A clock synchronization mark having a frequency higher than the modulation frequency (57.6 kHz) of the address information is synthesized at the zero cross point of the carrier at the center of the channel (channel bit switching point). The clock synchronization mark is recorded for each data bit or a predetermined number of data bits.
[0032]
In this way, by inserting the clock synchronization mark at the zero crossing point of the wobbling frequency modulation wave corresponding to the center of the address data bit (channel data bit switching point), fluctuations in the amplitude of the clock synchronization mark are reduced, and detection thereof is possible. It becomes easy.
[0033]
That is, in the FM modulation circuit 15, when the channel data bit is 0, frequency modulation is performed such that the frequency is shifted by -5% from the center frequency, and when the channel data bit is 1, the frequency is shifted by + 5% from the center frequency. When frequency modulation is performed, the boundary between the data bits or channel data bits and the zero cross point of the frequency modulation wave do not match, and channel data bits (or data bits) are easily detected erroneously. The insertion position of the clock synchronization mark is not necessarily a zero cross point, but is superimposed on a point having a predetermined amplitude value of the frequency modulation wave. As a result, the level of the clock synchronization mark increases or decreases by the amount of the amplitude value, making it difficult to detect. According to the present embodiment, since the clock synchronization mark is always arranged at the zero-cross position of the frequency modulation wave, it can be easily detected (identified from the frequency modulation wave).
[0034]
The recording circuit 24 controls the optical head 25 in response to the signal supplied from the combining circuit 22 and generates laser light for forming a pregroove (including a clock synchronization mark) on the master 26. The spindle motor 27 rotates the master 26 at a constant angular velocity (CAV).
[0035]
That is, the frequency modulation signal generated by the wobbling signal generation circuit 21 is combined with the clock synchronization mark signal output from the mark signal generation circuit 23 in the combining circuit 22 and input to the recording circuit 24. The recording circuit 24 controls the optical head 25 in response to the signal input from the synthesis circuit 22 and generates laser light. Laser light generated from the optical head 25 is applied to the master 26 rotated at a constant angular velocity by the spindle motor 27.
[0036]
The master 26 is developed, a stamper is created from the master 26, and the disk 1 as a large number of replicas is formed from the stamper. As a result, the disk 1 on which the pregroove 2 having the clock synchronization mark described above is formed is obtained.
[0037]
FIG. 10 shows a configuration example of an optical disc recording / reproducing apparatus for recording / reproducing data on / from the disc 1 thus obtained. The spindle motor 31 rotates the disk 1 at a predetermined angular velocity. The optical head 32 irradiates the disk 1 with laser light, records data on the disk 1, and reproduces data from the reflected light. The recording / reproducing circuit 33 temporarily stores recording data input from a device (not shown) in the memory 34, and the memory 34 stores data for one cluster (or data for one sector) as a recording unit. At this time, the data for one cluster is read out, modulated by a predetermined method, etc., and output to the optical head 32. The recording / reproducing circuit 33 appropriately demodulates the data input from the optical head 32 and outputs it to a device (not shown).
[0038]
The address generating / reading circuit 35 generates a data address (sector address) (described later with reference to FIG. 17) to be recorded in the track (pre-groove 2) in response to the control from the control circuit 38. 33 is output. The recording / reproducing circuit 33 adds this address to recording data supplied from a device (not shown), and outputs it to the optical head 32. Further, when the address data is included in the reproduction data reproduced from the track of the disk 1 by the optical head 32, the recording / reproducing circuit 33 separates the address data and outputs it to the address generating / reading circuit 35. The address generation / read circuit 35 outputs the read address to the control circuit 38.
[0039]
The mark detection circuit 36 detects a component corresponding to the clock synchronization mark from the RF signal reproduced and output by the optical head 32. The frame address detection circuit 37 reads address information (track number and frame number in FIG. 2) included in the wobbling signal from the RF signal output from the optical head 32 and supplies it to the cluster counter 46 and the control circuit 38. Yes.
[0040]
The mark period detection circuit 40 determines the periodicity of detection pulses output when the mark detection circuit 36 detects a clock synchronization mark. That is, since the clock synchronization mark is generated at a constant cycle, it is determined whether or not the detection pulse input from the mark detection circuit 36 is a detection pulse generated at this fixed cycle, and is generated at a fixed cycle. If it is a detection pulse, a pulse synchronized with the detection pulse is generated and output to the phase comparator 42 of the PLL circuit 41 at the subsequent stage. Further, the mark period detection circuit 40 generates a pseudo pulse at a predetermined timing so that the PLL circuit 41 at the subsequent stage does not lock to an incorrect phase when the detection pulse is not input at a constant period.
[0041]
The PLL circuit 41 includes a low-pass filter (LPF) 43, a voltage controlled oscillator (VCO) 44, and a frequency divider 45 in addition to the phase comparator 42. The phase comparator 42 compares the phases of the input from the mark period detection circuit 40 and the input from the frequency divider 45 and outputs the phase error. The low pass filter 43 smoothes the phase error signal output from the phase comparator 42 and outputs it to the VCO 44. The VCO 44 generates a clock having a phase corresponding to the output of the low pass filter 43 and outputs it to the frequency divider 45. The frequency divider 45 divides the clock input from the VCO 44 by a predetermined value (a value specified by the control circuit 38), and outputs the divided result to the phase comparator 42.
[0042]
The clock output from the VCO 44 is supplied to each circuit and is also supplied to the cluster counter 46. The cluster counter 46 counts the number of clocks output from the VCO 44 based on the frame address supplied from the frame address detection circuit 37, and the count value corresponds to a predetermined value (corresponding to the length of one cluster). A cluster start pulse is generated and output to the control circuit 38.
[0043]
The sled motor 39 is controlled by the control circuit 38 to move the optical head 32 to a predetermined track position of the disk 1. The control circuit 38 controls the spindle motor 31 to rotate the disk 1 at a predetermined angular velocity (CAV).
[0044]
The ROM 47 includes a table that defines the correspondence between the track number in the address frame (FIG. 2) and the zone in which the data recording area of the disk 1 is divided, and, if necessary, the band and the band corresponding to that zone ( A table defining the relationship of which will be described later in detail is stored.
[0045]
That is, the control circuit 38 records or reproduces data by dividing the disc 1 into a plurality of zones (in this embodiment, m + 2 zones from the 0th zone to the m + 1th zone) as shown in FIG. . Now, when the number of data frames per track in the 0th zone (this data frame is a unit of a block of data unlike the address frame described with reference to FIG. 2) is n, In the first zone, the number of data frames per track is n + 8. In the same manner, the number of data frames in the outermost zone increases by 8 compared to the adjacent inner zone, and n + 8 × (m + 1) data frames in the m + 1th outermost zone. Number.
[0046]
The first zone is switched from a radial position where a capacity of n + 8 frames is obtained with the same linear density as the innermost circumference linear density of the zeroth zone. Similarly, the mth zone is the mth zone from the radial position where the capacity of n + 8 × m frames can be obtained with the same linear density as the innermost circumferential line density of the 0th zone.
[0047]
For example, if the radius of the disk 1 is in the range of 24 mm to 58 mm as the recording / reproducing area, the track pitch is 0.87 μm, and the linear density is 0.38 μm / bit, the recording / reproducing area is as shown in FIGS. Into 93 zones. In the 0th zone with a disc radius of 24 mm, there are 520 frames per track (one rotation), and 8 frames are increased per track as the zone is incremented by one.
[0048]
As will be described later, in this embodiment, since one sector is composed of 24 frames (data frames), the number of frames incremented for each zone (= 8) is the number of frames constituting this one sector. That is, it is set to a value smaller than (= 24). As a result, many zones can be formed in finer units, and the capacity of the disk 1 can be increased. This method is called zone CLD (Constant Linear Dencity).
[0049]
12 to 15, the data in each column includes the zone number, the number of frames per radius, the number of tracks per zone, the number of recording / playback units (blocks) per zone (the number of clusters), The shortest line density in the zone, the capacity of the zone, the rotational speed of the zone, the minimum linear speed of the zone, or the maximum linear speed of the zone are respectively represented. The rotation speed represents the number of rotations per minute when the data transfer rate is 11.08 Mbps.
[0050]
In this embodiment, the number of tracks in each zone is fixed at 420, and this number of tracks is the number of frames in one recording / playback unit (the number of frames in the ECC block) (described later with reference to FIG. 20). Same value.
[0051]
In this embodiment, the number of tracks in each zone is one times the number of data frames (420 frames) constituting the recording / reproducing unit, but can be an integral multiple. As a result, no excessive data frame is generated, and an integer number of recording / reproduction units (blocks) are arranged in each zone, so that zoning efficiency can be improved. As a result, a capacity larger than the zone CAV and smaller than the zone CLV but close to the zone CLV can be obtained.
[0052]
In addition, by performing zoning close to CLV in this way, the change in the clock frequency between the zone and the next zone becomes small, and even when the playback is performed by a playback device dedicated to CLV, even between zones where the clock frequency changes. The clock can be extracted and the zones can be reproduced continuously.
[0053]
Next, the operation of the embodiment of FIG. 10 will be described. Here, the operation at the time of data recording will be described. The optical head 32 irradiates the optical disc 1 with laser light and outputs an RF signal obtained from the reflected light. The frame address detection circuit 37 reads wobbling information (address information) from this RF signal, outputs the read result to the control circuit 38, and supplies it to the cluster counter 46. The wobbling information is also input to the mark detection circuit 36, where a clock synchronization mark is detected and supplied to the mark period detection circuit 40.
[0054]
The mark period detection circuit 40 determines the periodicity of the clock synchronization mark, generates a predetermined pulse corresponding thereto, and outputs it to the PLL circuit 41. The PLL circuit 41 generates a clock (recording clock) synchronized with this pulse and supplies it to the cluster counter 46.
[0055]
The control circuit 38 can detect the position of the reference clock synchronization mark in one track (one rotation) from the frame address (frame number) supplied from the frame address detection circuit 37. For example, an arbitrary position on the track (an arbitrary position during one rotation) can be accessed from the count value of the recording clock with reference to the clock synchronization mark detected at the beginning of the frame of frame number 0 (address frame). It becomes possible.
[0056]
As described above, when an arbitrary position on the track is accessed, it is necessary to determine which zone the access point belongs to and generate a clock having a frequency corresponding to the zone in the VCO 44. . Therefore, the control circuit 38 further executes a clock switching process as shown in the flowchart of FIG.
[0057]
That is, first in step S 1, the control circuit 38 reads the track number from the frame address of the access point output by the frame address detection circuit 37. In step S 2, the zone corresponding to the track number read in step S 1 is read from the table stored in the ROM 47.
As described above, in the table of the ROM 47, it is stored in advance whether the track of each number belongs to, for example, the 0th zone to the 92nd zone.
[0058]
Accordingly, in step S3, it is determined whether or not the track number just read is a new zone different from the zone accessed so far. If it is determined that the zone is a new zone, the process proceeds to step S4, and the control circuit 38 controls the frequency divider 45 to set a frequency division ratio corresponding to the new zone. As a result, a recording clock having a different frequency for each zone is output from the VCO 44.
[0059]
If it is determined in step S3 that the current zone is not a new zone, the process in step S4 is skipped. That is, the frequency division ratio of the frequency divider 45 is not changed and is left as it is.
[0060]
Next, the format of the recording data will be described. In this embodiment, as described above, data is recorded in units of one cluster (32 kbytes). This cluster is configured as follows.
[0061]
That is, 2 kbytes (2048 bytes) of data is extracted as one sector of data, and an overhead of 16 bytes is added thereto as shown in FIG. This overhead includes a sector address (an address generated or read by the address generation / read circuit 35 in FIG. 10), an error detection code for error detection, and the like.
[0062]
This total of 2064 (= 2048 + 16) bytes of data is 12 × 172 (= 2064) bytes of data as shown in FIG. Then, 16 pieces of data corresponding to one sector are collected to obtain 192 (= 12 × 16) × 172 bytes of data. A 10-byte inner code (PI) and a 16-byte outer code (PO) are added to the 192 × 172 bytes of data as parity for each byte in the horizontal and vertical directions.
[0063]
Further, of the data thus blocked into 208 (= 192 + 16) × 182 (= 172 + 10) bytes, the 16 × 182 byte outer code (PO) is divided into 16 1 × 182 byte data. Then, as shown in FIG. 19, one by one is added below the 16 sector data of number 0 to number 15 of 12 × 182 bytes and interleaved. Then, 13 (= 12 + 1) × 182 bytes of data is used as one sector of data.
[0064]
Further, the 208 × 182 byte data shown in FIG. 19 is divided into two in the vertical direction as shown in FIG. 20, and one frame is 91 bytes of data, and 208 × 2 frames of data. Then, 2 × 2 frame link data (link area data) is added to the head of the 208 × 2 frame data (more precisely, as described later with reference to FIG. Part of the data is recorded at the beginning of the cluster and the rest is recorded at the end of the cluster). A 2-byte frame synchronization signal (FS) is further added to the head of the 91-byte frame data. As a result, as shown in FIG. 20, one frame of data is 93 bytes in total, and a total of 210 (= 208 + 2) × (93 × 2) bytes (420 frames) of block data. This is data for one cluster (a block as a recording unit). The size of the actual data part excluding the overhead part is 32 kbytes (= 2048 × 16/1024 kbytes).
[0065]
That is, in this embodiment, one cluster is composed of 16 sectors, and one sector is composed of 24 frames.
[0066]
Since such data is recorded on the disk 1 in units of clusters, a link area is arranged between the clusters as shown in FIG.
[0067]
As shown in FIG. 21, the link area is composed of four frames (data frames), and the data of one frame is 93 bytes as in the case of the data area (in the cluster). A 2-byte frame synchronization signal (FS) (Frame Sync) is arranged at the head of each frame.
[0068]
The link area is recorded by adding 86 bytes and 3 frames of data before a 32 kbyte data block (cluster). Of the 86 bytes of data, the first 20 bytes are used as a prebuffer and ALPC (Automatic Laser Power Control). The pre-buffer is a buffer that absorbs the deviation of the start position of the cluster due to jitter, and the ALPC is for setting recording power in which data for setting the output at the time of recording or reproduction of laser light to a predetermined value is recorded. It is an area.
[0069]
In the next 66 bytes, Slice / PLL is arranged. Slice is data for setting a time constant for binarizing reproduction data, and PLL is data for reproducing a clock.
[0070]
Slice / PLL is arranged in the following two frames, respectively. In the last one frame, the slice / PLL is arranged in the first 83 bytes, the synchronization signal (Sync) is arranged in the next 4 bytes, and the last 4 bytes are reserved for future use (Reserve). It is said.
[0071]
Further, after the 32 kbyte (cluster) data block, a 2-byte frame synchronization signal, a 1-byte postamble, and an 8-byte postbuffer are formed. In the postamble, the data for returning the signal polarity is recorded by adjusting the mark length of the last data. The post buffer is a buffer area for absorbing jitter due to eccentricity or the like. In the ideal state where there is no jitter, 4 bytes of the 8-byte post buffer overlap, and the pre-buffer and ALPC of the next cluster are recorded.
[0072]
It is also possible to apply this link area to a ROM disk so that the ROM disk and the RAM disk have a common format. In that case, in the ROM disk, information can be recorded in the post buffer, pre-buffer, and ALPC in the link area. For example, it is possible to insert an address and increase the information probability of the address.
[0073]
As shown in FIGS. 12 to 15, the disk 1 divided into 93 zones is schematically shown in FIG. 22 as described above. In the above-described embodiment, each of these 93 zones is driven at a constant (same) speed, but a plurality of zones constitute a band, Each band has a constant speed, but each band can be driven at a different angular speed.
[0074]
For example, as shown in FIG. 23 and FIG. 24, when the range from the innermost radius r0 to the outermost radius rn is an area where data is recorded and reproduced, an intermediate radius r3 (= (r0 + rn) The area is divided at the position of / 2). That is, it is divided into a band from radius r0 to radius r3 and a band from radius r3 to radius rn. In each band, when the disk 1 is rotated at a constant angular velocity, and the angular velocity (rotational velocity) at the radius r0 is R1, the angular velocity R3 at the radius r3 is inversely proportional to the radius, and therefore can be obtained from the following equation. it can.
R3 = R1 × (r0 / r3)
[0075]
As shown in FIG. 24, if the linear velocity at the radius r0 is v1, the linear velocity v4 at the radius r3 in the first band is proportional to the radius, and can be obtained from the following equation.
v4 = (r3 / r0) × v1
[0076]
Further, since the linear velocity at the radius r3 in the next band is v1, the linear velocity v3 at the radius rn can be obtained from the following equation.
v3 = (rn / r3) × v1
[0077]
If the region is divided into bands in this way, the rotation speed can be reduced in the band from the radius r3 to the radius rn than in the band from the radius r0 to the radius r3. The recording capacity can be increased as compared with the normal zone CAV method described above.
[0078]
In the embodiment shown in FIGS. 23 and 24, the band is divided by a radius r3 intermediate between the innermost radius r0 and the outermost radius rn. As a result, the widths of changes in linear velocity in the two bands are different.
[0079]
Therefore, for example, as shown in FIGS. 25 and 26, the widths of changes in linear velocity in the two bands can be made the same.
[0080]
That is, in this case, assuming that the radius for dividing the band is r2 and the linear velocity at the end point of each band is v2, the following equation is obtained from the relationship of the linear velocity.
v1 / r0 = v2 / r2
v1 / r2 = v2 / rn
[0081]
Therefore, the following equation is obtained from the above equation.
r2 = (r0 × rn)^1/2
v2 = (rn / r0)^1/2× v1
[0082]
In this case, if the rotational speed in the band from radius r0 to radius r2 is R1, and the rotational speed from radius r2 to radius rn is R2, R2 can be obtained from the following equation.
R2 = R1 (r0 / r2) = (r0 / rn)^1/2× R1
[0083]
In this way, if the two bands are divided by the radius r2, the width of the change in linear velocity in each band can be made the same.
[0084]
In the above embodiment, the number of bands is two, but may be four. FIGS. 27 and 28 correspond to FIGS. 23 and 24 and show a case where a band is generated by equally dividing the range from radius r0 and radius rn into radii r8, r9 and r10. 30 and 30 correspond to FIGS. 25 and 26, and show a case where the bands are divided by the radii r5, r6, and r7 so that the width of the linear velocity change in each band is the same.
[0085]
That is, in the embodiment shown in FIGS. 27 and 28, the range from the radius r0 to the radius rn is divided into four equal parts by the radii r8, r9, r10, so each radius is expressed by the following equation.
r8 = r0 + (rn−r0) / 4
r9 = (r0 + rn) / 2
r10 = r0 + (3/4) (rn−r0)
[0086]
Further, the rotational speeds R8, R9, and R10 of each band are expressed by the following equations, respectively.
R8 = R1 × (r0 / r8)
R9 = R1 × (r0 / r9)
R10 = R1 × (r0 / r10)
[0087]
Furthermore, the linear velocities v8, v9, v10, v11 at the end points of the bands of the radii r8, r9, r10, rn can be obtained from the following equations, respectively.
v8 = (v1 / r0) × r8
v9 = (v1 / r0) × r9
v10 = (v1 / r0) × r10
v11 = (v1 / r0) × rn
[0088]
On the other hand, in the embodiments of FIGS. 29 and 30, the rotational speeds R5, R6 and R7 from the radii r5 to r6, the radii r6 to r7, and the radius r7 to the radius rn can be obtained from the following equations, respectively.
R5 = R1 × (r0 / r5)
R6 = R1 × (r0 / r6)
R7 = R1 × (r0 / r7)
[0089]
In addition, as shown in FIG. 30, when the linear velocity at the radii r5, r6, r7, rn at the end points of each band is v5, the following equation is established.
v1 / v5 = r0 / r5 = r5 / r6 = r6 / r7 = r7 / rn
[0090]
Therefore, the following equation is obtained.
r5 = (r0 × r6)^1/2
r6 = (r0 × rn)^1/2
r7 = (r6 × rn)^1/2
[0091]
Further, the linear velocity v5 at the respective radii r5, r6, r7, rn can be obtained from the following equation.
[0092]
v5 = (r5 / r0) v1 = (r0 × r6)^1/2(V1 / r0)
= (R6 / r0)^1/2v1 = ((r0 × rn)^1/2/ R0)^1/2v1
= (Rn / r0)^1/4v1
[0093]
In the case of a normal CAV disk, the linear velocity at the position of the radius rn is vn. As a result, the change width is vn-v1, whereas in the embodiment shown in FIGS. 29 and 30, v5 It can be suppressed to a change width of −v1 (change width of ¼ or less of (vn−v1)).
[0094]
As described above, when the range from the radius r0 to the radius rn is divided into four bands at the radii r5, r6, and r7 so that the change width of the linear velocity is constant, the rotational speed, linear velocity, and The line density and the clock frequency change as shown in FIGS. 31 to 33, respectively.
[0095]
That is, the rotation speed is R1 in the band from radius r0 to radius r5, the rotation speed is R5 in the band from radius r5 to radius r6, and the rotation speed is in the band from radius r6 to radius r7. The speed is R6, and the rotation speed is R7 in the band from the radius r7 to the radius rn. As shown in FIG. 32, the linear velocity in each band increases from v1 to v5 from the innermost circumference to the outermost circumference, but the change width in each band is constant.
[0096]
As shown in FIG. 33, as described above, the clock frequency is constant in each zone, but is switched for each zone, and in each band, the zone on the outer peripheral side from the zone on the inner peripheral side. In this case, the clock frequency increases sequentially. The clock frequency at the start point of each band of radius r0, r5, r6, r7 is the same, but the width (number of tracks) of each band is different, so the value of the clock frequency at the end point of each band is The case is bigger.
[0097]
Further, the linear density is smaller on the outer peripheral side in each zone than on the inner peripheral side, but the change width is constant in any zone of any band.
[0098]
As described above, when a plurality of zones are collectively divided into a plurality of bands, the control circuit 38 executes the clock switching and rotation control processing shown in FIG. The processes in steps S11 to S14 are basically the same as the processes in steps S1 to S4 in FIG. That is, when the track number is read from the wobble address in step S11, the zone and band of the read track number are read from the ROM 47 in step S12. In step S13, it is determined whether or not the zone of the read track number is a new zone. If it is determined that the zone is a new zone, the process proceeds to step S14 to perform a frequency division ratio change process of the PLL circuit 41. Thereafter, in step S15, it is determined whether or not the band having the track number read in step S12 is a new band. If it is determined that the band is a new band, the process proceeds to step S16, and the control circuit 38 changes the rotational speed of the spindle motor 31 to an angular speed corresponding to the new band.
[0099]
If it is determined in step S13 that the zone is not a new zone, the processing in steps S14 to S16 is skipped. If it is determined in step S15 that the band with the read track number is not a new band, the processing in step S16 is performed. Is skipped.
[0100]
As described above, as shown in FIG. 22, each zone divided into 93 zones from zone 0 to zone 92 has a constant change rate of linear velocity in each band as shown in FIGS. 29 and 30. In this way, each parameter is as shown in FIGS. 35 to 38. In these figures, the data in the left seven columns are the same as those in FIGS. 12 to 15, and the data in the three right columns are the rotational speed in each zone, the lowest linear velocity in each zone, and the data in each zone. The maximum linear velocity is shown respectively. As shown in these drawings, in this embodiment, zone 0 to zone 15 are the first band, zone 16 to zone 35 are the second band, and zone 36 to zone 60 are the third band. The zones 61 to 92 are the fourth band.
[0101]
Note that the length (number of bytes) of each area in the above embodiment is an example, and a predetermined value can be set as appropriate.
[0102]
By the way, when the optical disc 1 is not a reproduction-only disc but also a recordable disc, random access is possible if the address is recorded by wobbling the edge of the groove or land as described above. . Therefore, for example, as shown in FIG. 39, a recorded area in which data is recorded is formed in a part of a track continuously formed in a spiral shape, and a predetermined section data is not recorded. Data may be intermittently recorded such that a recording area is formed and then a recorded area is formed again.
[0103]
Such a disc is mounted on an inexpensive playback device that performs so-called CLV playback, in which the rotation of the disc is controlled so that the clock included in the playback signal has a predetermined frequency and phase, and is recorded there. When data is to be reproduced, it is necessary to move the data reproduction point from a predetermined recorded area through the unrecorded area to the next recorded area. In such a case, the clock can be reproduced in the recorded area, but the clock cannot be reproduced in the unrecorded area. For this reason, it becomes impossible to accurately control the rotation of the disk. As a result, it becomes difficult to reproduce data, and in the worst case, the spindle motor goes out of control.
[0104]
In order to prevent this, the configuration shown in FIG. 40 can be further added to the recording / reproducing apparatus shown in FIG.
[0105]
That is, in the embodiment of FIG. 40, an envelope detection circuit 61 for detecting the envelope of the RF signal output from the optical head 32 by reproducing the optical disk 1 is provided. The comparator 62 compares the envelope signal output from the envelope detection circuit 61 with a predetermined reference level set in advance, and outputs the comparison result to the recorded / unrecorded determination circuit 63. The recording / non-recording determination circuit 63 is configured to output a determination result to the control circuit 38.
[0106]
The host computer 71 is connected to the recording / reproducing circuit 33 and the control circuit 38 via a SCSI bus. The host computer 71 has finalize application software 72, and appropriately controls the operation of the recording / reproducing apparatus. The input device 73 is operated by the user and outputs a signal corresponding to the operation to the host computer 71.
[0107]
Next, the operation will be described with reference to the flowchart of FIG. The process shown in the flowchart of FIG. 41 is directed to eject the optical disk 1 in a state where the user operates the input device 73 to instruct the host computer 71 to reproduce the optical disk 1 in the CLV reproducing apparatus. When the process starts.
[0108]
First, in step S31, the host computer 71 controls the control circuit 38 via the SCSI bus, and causes the optical head 32 to read the management information of the optical disc 1. That is, when data is recorded on the optical disc 1, the control circuit 38 records file allocation information indicating the recording position, alternate sector information, and the like on a predetermined track of the optical disc 1. The host computer 71 reads this management information via the recording / reproducing circuit 33. In step S32, the host computer 71 determines whether or not there is a zone in which data is recorded in only a part of the plurality of zones (data is stored). It is determined whether there is a zone in which recorded clusters and clusters in which no data is recorded exist.
[0109]
  In step S32, in principle, it is only necessary to determine whether or not there is an area in the track where data is not partially recorded. However, in this embodiment, more safety is ensured. Therefore, in a zone where a cluster as a recording / reproducing unit in which data is recorded and a cluster in which no data is recorded are mixed, as described later,No data is recordedDummy data is recorded for all the clusters. Then, at least in that zone, it is possible to control the rotation of the disk.
[0110]
When it is determined that there is a zone in which recorded clusters and unrecorded clusters are mixed, the host computer 71 proceeds to step S33 to transfer the optical head 32 to the zone and reproduce the track. As described above with reference to FIG. 21, in the optical disc 1, the cluster is composed of a data area for recording 32 kilobytes of data and a link area of 4 frames. When data is recorded in the data area of the cluster, various control data as shown in FIG. 21 is also recorded in each frame of the link area of the previous four frames. The envelope detection circuit 61 in FIG. 40 detects the envelope of the RF signal output from the optical head 32, and the comparator 62 sets the level of the envelope signal output from the envelope detection circuit 61 to a predetermined reference level set in advance. Compare.
[0111]
When data is recorded in the cluster, the envelope is higher than the reference level, and when data is not recorded in the cluster, the envelope level is lower than the reference level. The comparator 62 outputs a logic H, for example, when the envelope level is higher than the reference level, and outputs a logic L when it is smaller. Therefore, the recording / non-recording determination circuit 63 can determine from the output of the comparator 62 whether or not data is recorded in the currently reproduced cluster. The control circuit 38 takes in the determination result of the recording / non-recording determination circuit 63 and outputs it to the host computer 71 via the SCSI bus. Thereby, the host computer 71 can determine whether data is recorded in each cluster.
[0112]
In this embodiment, as will be described later with reference to step S34, in a zone in which a cluster in which data is recorded and a cluster in which data is not recorded are mixed, the cluster in which the data is not recorded Record dummy data. However, in order to make it possible to identify that the data is dummy data, as shown in FIG. 42, the first frame of the link frame of the cluster in which the dummy data is recorded is used as a monitor area. Do not record dummy data. Of course, no data is recorded in each frame of the link area of the cluster in which no data is recorded in the data area of 32 kilobytes.
Therefore, the detection of the envelope of the RF signal in step S33 is performed in the first frame of the link frame.
[0113]
If it is determined in step S33 that no data is recorded in the first frame of the link frame, the process proceeds to step S34, and a process of recording dummy data in the cluster is executed.
[0114]
Details of the process in step S34 are shown in FIG. That is, in step S41, as shown in FIG. 42, dummy data is recorded in the second to fourth frames in the link frame and the subsequent 32 kilobyte data area. That is, the host computer 71 outputs dummy data to the recording / reproducing circuit 33 via the SCSI bus, and records it on the optical disc 1 via the optical head 32.
[0115]
Returning to FIG. 41, after the process of recording the dummy data in the cluster in step S34 is executed, the process returns to step S33, and it is determined again whether there is another cluster in which no data is recorded, When such a cluster exists, the process proceeds to step S34, and a process of recording dummy data in the cluster is executed.
[0116]
By repeatedly executing the processing as described above, substantial data is recorded or dummy data is recorded in all clusters in the zone.
[0117]
When some data is recorded in all the clusters in the predetermined zone, NO is determined in step S33, and the process returns to step S32. In step S32, it is determined whether or not there is a zone in which other data-recorded clusters and non-recorded clusters are mixed. If it is determined that such a zone exists, Returning to step S33, similar processing is executed.
[0118]
If it is determined in step S32 that there is no longer any zone in which such clusters exist, the process proceeds from step S32 to step S35, and the host computer 71 controls the control circuit 38 to eject the optical disc 1 from the recording / reproducing apparatus. To execute the process.
[0119]
As described above, when ejection of the optical disc 1 is commanded in a state where playback is commanded by a playback device that performs CLV playback, dummy data is recorded in a cluster in an unrecorded area as shown in FIG. Will be. For this reason, when the optical disk 1 is CLV-reproduced, it is possible to continuously extract a clock from the reproduction signal, accurately control the rotation of the optical disk 1, and reproduce the data recorded there. .
[0120]
In the embodiment of FIG. 42, only the first frame of the four frames in the link area is used as the monitor area, and no dummy data is recorded.
Therefore, it is determined whether or not data is recorded in the first frame, and if it is recorded, it is assumed that substantial data is recorded in the subsequent cluster, and that cluster is a dummy. Data can be prevented from being recorded.
[0121]
However, for example, when a cluster in which data is substantially recorded is played back, the playback data cannot be obtained because the data of the first frame in the link area is due to damage to the disk or the like. In some cases, the cluster is mistakenly recognized as a cluster in which no data is recorded, and dummy data may be overwritten there.
[0122]
In order to prevent such a misjudgment, for example, as shown in FIG. 44, not only the first frame but also the third frame of the four link frames is set as a monitor area, and dummy data is provided there. You can avoid recording.
[0123]
When the format shown in FIG. 44 is used, the process in step S34 in FIG. 41 is the process shown in the flowchart in FIG.
[0124]
That is, in step S51, dummy data is recorded in the second frame of the link frame. In step S52, it is determined whether data is recorded in the third frame of the link frame. When it is determined that data is not recorded in the third frame (that is, when substantial data is not recorded in the cluster), the process proceeds to step S53, and the fourth frame of the link frame is followed by 32. A process of recording dummy data in the data area of kilobytes is executed.
[0125]
On the other hand, when it is determined in step S52 that data is recorded in the third frame of the link frame, the process of step S53 is skipped. That is, it is assumed that data is substantially recorded in the cluster, and the subsequent recording of dummy data is not performed. This prevents substantial data from being erased by dummy data.
[0126]
FIG. 46 shows another embodiment for determining whether data is recorded. In this embodiment, the demodulation circuit 81 demodulates the RF signal output from the optical head 32 and outputs the demodulation result to the frame synchronization signal detection circuit 82. The frame synchronization signal detection circuit 82 detects a frame synchronization signal from the output of the demodulation circuit 81 and outputs the detection result to the recording / non-recording determination circuit 63. The output of the demodulation circuit 81 is also directly supplied to the recording / non-recording determination circuit 63.
[0127]
The recording / non-recording determination circuit 63 determines the reproduction position of the demodulated data supplied from the demodulation circuit 81 from the frame synchronization signal detection position of the frame synchronization signal detection circuit 82. Then, it is determined whether or not an amount of data equal to or greater than a predetermined reference value is obtained from a predetermined frame among the four frames of the link frame described above. When data equal to or greater than the reference value is obtained, it is determined that the data is substantially recorded in the cluster. When the data amount is equal to or less than the reference value, the cluster is a blank cluster (data Is a substantially unrecorded cluster).
[0128]
Various other circuits can be considered as a circuit for determining whether or not data is recorded.
[0129]
In the above description, a cluster is used as a recording / reproducing unit, but other units may be used as a recording / reproducing unit.
[0130]
The present invention can also be applied to the case where data is recorded or reproduced on a disk other than the optical disk.
[0131]
【The invention's effect】
  As described above, according to the recording / reproducing apparatus according to claim 1 and the recording / reproducing method according to claim 9,In a recording medium in which data is recorded on a part of a track,When a recording / reproduction unit in which no data is recorded is detected, dummy data is recorded in the recording / reproduction unit. Therefore, even when reproduction is performed in the CLV reproduction device, the drive of the recording medium can be easily controlled. , The data recorded there can be reproduced accurately.
[Brief description of the drawings]
FIG. 1 is a diagram for explaining a state where a disk used in a recording / reproducing apparatus of the present invention is wobbled.
FIG. 2 is a diagram illustrating a configuration example of a wobbling address frame.
FIG. 3 is a diagram illustrating a configuration example of a wobbling signal generation circuit.
4 is a diagram illustrating an example of a biphase signal output from the biphase modulation circuit 13 of FIG. 3;
5 is a diagram illustrating another example of a biphase signal output from the biphase modulation circuit 13 of FIG. 3;
6 is a diagram for explaining frequency modulation performed by the FM modulation circuit 15 of FIG. 3; FIG.
7 is a diagram illustrating a frequency modulation wave output from the FM modulation circuit 15 of FIG. 3;
FIG. 8 is a diagram illustrating a configuration example of a recording apparatus for manufacturing a disk 1 having pregrooves.
FIG. 9 is a diagram for explaining the operation of the synthesis circuit 22 in FIG. 8;
FIG. 10 is a block diagram showing a configuration example of an optical disc recording / reproducing apparatus to which the recording / reproducing apparatus of the present invention is applied.
FIG. 11 is a diagram illustrating zones in a disc.
FIG. 12 is a diagram illustrating parameters of each zone.
FIG. 13 is a diagram illustrating parameters of each zone.
FIG. 14 is a diagram illustrating parameters of each zone.
FIG. 15 is a diagram illustrating parameters of each zone.
FIG. 16 is a flowchart for explaining clock switching processing in the embodiment of FIG. 10;
FIG. 17 is a diagram illustrating a data format for one sector.
FIG. 18 is a diagram for explaining the structure of 32 kbyte data.
19 is a diagram for explaining a state where outer codes in FIG. 18 are interleaved.
FIG. 20 is a diagram for explaining a data structure of a block of 32 kbytes.
FIG. 21 is a diagram illustrating a configuration example of a link area.
FIG. 22 is a diagram showing a state in which a disc is divided into 93 zones.
FIG. 23 is a diagram for explaining a disk rotation speed when divided into two bands.
FIG. 24 is a diagram for explaining linear velocities when divided into two bands.
FIG. 25 is a diagram for explaining the disk rotation speed when the band is divided into two bands;
FIG. 26 is a diagram for explaining a linear velocity in the case of being divided into two bands.
FIG. 27 is a diagram for explaining the disk rotation speed when divided into four bands.
FIG. 28 is a diagram for explaining linear velocities when divided into four bands.
FIG. 29 is a diagram for explaining the disk rotation speed when divided into four bands.
FIG. 30 is a diagram for explaining linear velocities when divided into four bands.
FIG. 31 is a diagram for explaining a disk rotation speed when divided into four bands.
FIG. 32 is a diagram for explaining linear velocities when divided into four bands.
FIG. 33 is a diagram for explaining a linear velocity and a clock frequency when divided into four bands.
FIG. 34 is a flowchart for explaining clock switching and rotation control processing in the case of dividing a band.
FIG. 35 is a diagram illustrating parameters in the case of dividing into four bands.
FIG. 36 is a diagram illustrating parameters in the case of dividing into four bands.
FIG. 37 is a diagram illustrating parameters in the case of dividing into four bands.
FIG. 38 is a diagram illustrating parameters in the case of dividing into four bands.
FIG. 39 is a diagram for explaining a recorded area and an unrecorded area of an optical disc.
FIG. 40 is a block diagram illustrating a configuration example of an additional part of the optical disc recording / reproducing apparatus.
FIG. 41 is a flowchart for explaining the operation of the embodiment of FIG. 40;
FIG. 42 is a diagram illustrating a format for recording dummy data.
43 is a flowchart for explaining more detailed processing in step S34 of FIG. 41. FIG.
44 is a diagram illustrating an example of another format for recording dummy data. FIG.
45 is a flowchart showing another example of processing in step S34 of FIG. 41. FIG.
FIG. 46 is a block diagram showing a configuration example of another additional part of the optical disc recording / reproducing apparatus.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 1 Optical disk, 2 Pregroove, 11 Generation circuit, 12, 14 Divider, 13 Biphase modulation circuit, 15 FM modulation circuit, 21 Wobbling signal generation circuit, 22 Synthesis circuit, 23 Mark signal generation circuit, 24 Recording circuit, 25 Optical head, 26 master disk, 27 spindle motor, 31 spindle motor, 32 optical head, 33 recording / reproducing circuit, 34 memory, 35 address generation reading circuit, 36 mark detection circuit, 37 frame address detection circuit, 38 control circuit, 39 thread motor , 40 mark period detection circuit, 41 PLL circuit, 42 phase comparator, 43 LPF, 44 VCO, 45 frequency divider, 46 cluster counter, 47 ROM, 61 envelope detection circuit, 62 comparator, 63 Recording / non-recording judgment circuit

Claims (8)

In a recording / reproducing apparatus for recording or reproducing data on a recording medium formed by wobbling so that a track for recording or reproducing data corresponds to an address,
Detecting means for detecting a recording / reproducing unit in which the data is not recorded in a predetermined area of the track in the recording medium in which the data is recorded on a part of the track;
A recording / reproducing apparatus comprising: a recording unit that records a frame synchronization signal and dummy data in the recording / reproducing unit when the detecting unit detects a recording / reproducing unit in which the data is not recorded. The recording / reproducing unit is composed of a cluster for recording or reproducing the data, and a link area arranged between the preceding and succeeding clusters.
The detection means detects that the data is not recorded in at least one of a plurality of frames constituting the link area from a recording / reproduction unit in which the dummy data is not recorded,
The recording means records the dummy data in the cluster excluding at least one of the frames in which the data of the recording / reproducing unit in which the dummy data is not recorded is not recorded, and the cluster. The recording / reproducing apparatus according to claim 1. The said recording means records the said dummy data in the flame | frame except the 1st and 3rd frame which comprises the said link area among the frames in which the said data are not recorded. The recording / reproducing apparatus described in 1. The recording medium is divided into a plurality of zones,
The recording means records the dummy data with respect to the unrecorded recording / reproducing unit in the zone including both the recording / reproducing unit in which the data is recorded and the unrecorded recording / reproducing unit. The recording / reproducing apparatus according to claim 1, wherein: The recording / reproducing apparatus according to claim 1, wherein the detecting unit detects a recording / reproducing unit in which the data is not recorded from an envelope of a reproduction signal obtained when the recording medium is reproduced. The recording / reproducing apparatus according to claim 1, wherein the detecting unit detects a recording / reproducing unit in which the data is not recorded from data obtained by demodulating a reproduction signal obtained when the recording medium is reproduced. The recording / reproducing apparatus according to claim 1, wherein the detection unit detects a recording / reproducing unit in which the data is not recorded when the ejection of the recording medium is instructed. In a recording / reproducing method for recording or reproducing data on a recording medium formed by wobbling so that a track for recording or reproducing data corresponds to an address,
In the recording medium in which the data is recorded on a part of the track, a recording / reproduction unit in which the data is not recorded in a predetermined area of the track is detected;
When a recording / reproducing unit in which no data is recorded is detected, a frame synchronization signal and dummy data are recorded in the recording / reproducing unit.

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