JPH11306685A - Signal processing circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To correctly detect a fine clock mark included in a wobble signal without causing any erroneous detection and detection omission independently of amplitude variation of a wobble signal. SOLUTION: A peak-hold level Lph following almost an envelope waveform of a wobble signal is obtained by performing peak-hold for a wobble signal, and a slice level Lsc is set by making gain variable and applying a low-pass filter for this peak-hold Lph. In this case, the slice level Lsc is made a waveform shape following almost an envelope waveform of an address information component of a wobble signal, further, a slightly larger level is set than amplitude of an address information component of a wobble signal in an extent in which a fine clock marker can be detected. Thereby, erroneous detection of an address information component can be prevented, and a component of a fine clock marker can be detected surely.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a signal processing circuit for detecting, for example, a signal superimposed on a certain signal such that the signal suddenly appears with a larger amplitude than the certain signal. It is about.

[0002]

2. Description of the Related Art CD (Compact Disc) and CD-ROM (Com
Disc-shaped optical recording media such as pact Disc-Read Only Memory) have become widespread. These CDs and CD-ROMs
At the time of manufacturing, a minute concave portion (physical pit) is formed on the surface of the plastic substrate, and information is recorded by this pit row. The pit train itself is used as a track, and the light beam spot for signal reproduction traces the track based on the pit train. That is, media such as CDs and CD-ROMs are read-only media, and cannot be added or rewritten after manufacturing.

On the other hand, in recent years, a write-once CD-R (R
Discs capable of recording and reproducing data, such as ecordable and rewritable CD-RWs (ReWritable), have become widespread. In these recording media, grooves as guide grooves are formed in a manufacturing process so that a light beam spot can properly trace in a recording area. In the case of a CD-R, data recording is performed by modulating the intensity of a light beam spot, thereby deforming the recording layer on the groove to form physical pits. Also CD
In the case of -RW, this is performed by forming phase pits by a so-called phase change method.

In recent years, DVDs (Digital Versataile Discs or Digital
l Video Discs), read-only discs such as DVD-ROMs, etc., have also been known.
Disc media having a recording capacity substantially equivalent to that of a D-ROM have also been proposed.

In order to record data on a recordable disc as described above, it is necessary to record address information so that data can be recorded at a predetermined position. This address information may be recorded on the disc as wobbles.

For example, a modulated signal obtained by modulating address information by FSK modulation (frequency shift keying modulation) is generated as a wobble signal. Tracks for recording data on the disc are formed in advance as grooves, for example, and the side walls of the groups are wobbled (meandering) in accordance with the wobble signal, that is, wobbled grooves are formed. . In this way, the address can be read from the wobble of the groove. For example, data can be recorded and reproduced at a desired position without forming pit data or the like indicating the address on the track in advance.

FIG. 14 shows an example of a groove structure of an optical disk. As shown in FIG.
The track on 0 is formed in advance from the inner periphery to the outer periphery in a spiral shape as a pre-group (sometimes simply referred to as a groove) 101. As shown in FIG. 14B, a part of the group 101 is wobbled on the right and left side walls in accordance with the wobble signal (address information). That is, the wobble is provided so as to meander at a predetermined cycle corresponding to the wobble signal generated based on the address. A land 102 is formed between the groove 101 and the adjacent groove 101. For example, data is recorded on the groove 101.

Further, the groove 101 shown in FIG. 14 can contain not only address information but also information as a fine clock mark used for clock synchronization. In other words, by arranging wobbles as fine clock marks at predetermined intervals according to the clock cycle, the reproduced information can be, for example, fine radial position information on one round track on the disk. In this case, a wobble signal to be recorded on the disk is generated by superimposing a signal as a fine clock mark on a wobble signal as address information obtained by FSK modulation.

[0009] As an actual wobble on a disk, an amplitude as a fine clock mark is arranged at a constant interval with respect to a constant minute amplitude corresponding to address information. In this case, the amplitude portion corresponding to the address information and the amplitude portion corresponding to the fine clock mark coexist as wobbles. Therefore, in order to detect the fine clock mark as accurately as possible from the reproduced wobble signal, an address is generally used. The amplitude of the fine clock mark is suddenly made larger than the wobble of the information.

For example, in order to generate a clock based on a fine clock mark, a signal portion corresponding to the fine clock mark is detected from a detection signal (hereinafter, referred to as a wobble signal) about a wobble read from a disk. FIG. 15 shows an example of this fine clock mark detection operation.

FIG. 15A shows a wobble signal Wb read from a disk. As described above, since the wobble portion corresponding to the address information has a constant minute amplitude, ideally the wobble signal Wb
As shown in FIG. 15A, a sudden large level of amplitude as the fine clock mark FCK is obtained for a waveform having a constant amplitude.

Here, when the fine clock mark FCK is to be detected from the waveform of the wobble signal Wb shown in FIG. 15A, the amplitude of the wobble signal Wb is set to be larger than the amplitude level L1 corresponding to the address information. Then, after preventing this from being detected, the predetermined level at which the level of the fine clock mark FCK is surely sliced within a range not exceeding the maximum amplitude of the fine clock mark FCK is determined by the slice levels Lsc and Lsc.
It is conceivable to set as sc. Then, the wobble signal waveform is compared with the slice level Lsc, and the wobble signal level is changed to the slice level Lsc.
Is exceeded, the pulse obtained as shown in FIG. 15B or FIG. 15C may be handled as the edge detection signal Edge.

For example, in order to obtain the edge detection signal Edge from the wobble signal Wb as described above, a configuration as shown in FIG. 16 may be employed. That is, the wobble signal Wb
Is compared with the slice level Lsc set as described above, and a comparator Comp that outputs the comparison result as an edge detection signal Edge may be provided.

[0014]

However, the actual amplitude level of the wobble signal read from the disk is shown in FIG.
As shown in FIG. 5 (a), the variation is not always constant, and greatly varies due to variations in the reflectivity of the disk, variations in the laser intensity applied to the disk for data reproduction, and crosstalk between adjacent grooves. Often do.

For example, the wobble signal Wb whose amplitude level fluctuates greatly in this way is shown in FIG.
If the slice level Lsc set as described in FIG. 5A is applied as it is, the following inconvenience may occur. That is, as shown in FIG.
When the amplitude of the wobble signal Wb has increased to some extent, the amplitude level L1 of the wobble signal corresponding to the address information exceeds the slice level Lsc, and FIG.
As shown in (e), the original fine clock mark F
There is a possibility that an erroneous detection such as outputting the edge detection signal Edge even at a timing other than CK may be caused. In addition,
In FIG. 15D, for convenience of explanation, the slice level Lsc is used.
Shows only the upper slice level Lsc of the wobble signal waveform.

In order to avoid such erroneous detection, the amplitude level L1 corresponding to the address information does not exceed the slice level as much as possible, for example, as shown in FIG. Fifteen
Suppose that the slice level Lsc is set higher than the absolute value of the amplitude level as shown in FIG. In this case, for example, when the amplitude fluctuation of the entire wobble signal Wb fluctuates to be small, the amplitude of the fine clock mark FCK cannot exceed the slice level Lsc, and is shown in FIG. In this manner, the fine clock mark FCK is used as the edge detection signal Edge.
May result in not detecting.

As described above, since the actual wobble signal has a fluctuation in the amplitude level, it is difficult to always properly detect the fine clock mark only by setting the slice level by a certain fixed value. It is.

[0018]

SUMMARY OF THE INVENTION In order to solve the above-mentioned problems, the present invention solves the above-mentioned problem by providing a signal of a certain kind, such as a wobble signal, having a larger amplitude than a sudden appearance such as a fine clock mark. From the signal where the signal is superimposed, regardless of the amplitude fluctuation of this signal,
An object of the present invention is to enable a signal having a large amplitude to be properly detected.

For this reason, for a processed signal formed by superimposing another specific signal having an amplitude larger than that of the specific signal on a specific signal, the other signal is detected. A peak hold means for outputting a peak hold signal obtained by performing peak hold on the input processed signal, and a processing signal based on the level of the input peak hold signal. Slice level setting means for determining a slice level with respect to the signal level, and signal detection means configured to detect another signal by using a detection signal obtained when the level of the processed signal exceeds the slice level. It was decided to comprise.

A track for recording data is formed by superimposing a second signal having an amplitude level larger than that of the first signal on a first signal corresponding to specific information. A signal processing circuit that performs signal processing for detecting a second signal is input to a meandering reproduction signal obtained based on the meandering, which is reproduced from an optical recording medium that is formed by meandering with a signal. Peak hold means for outputting a peak hold signal obtained by performing peak hold on the meandering reproduction signal, slice level setting means for determining a slice level for the meandering reproduction signal based on the level of the input peak hold signal, The second signal is obtained by utilizing the detection signal obtained when the level of the meandering reproduction signal exceeds the slice level. It was decided to constitute and a signal detection means adapted to detect.

[0021] Further, in order to detect another signal from a processing signal formed by superimposing another specific signal having an amplitude larger than the amplitude of the specific signal on a specific signal. As a signal processing circuit that performs signal processing of the above, a differentiating unit that outputs a differentiated signal by performing differentiation on the processed signal, and a peak holding unit that outputs a peak hold signal obtained by performing a peak hold on the input differentiated signal. By using a slice level setting means for determining a slice level for the differential signal based on the level of the input peak hold signal, and a detection signal obtained when the level of the differential signal exceeds the slice level. , And signal detection means configured to detect other signals.

A track for recording data is formed by superimposing a second signal having a larger amplitude level than the first signal on a first signal corresponding to certain information. A signal processing circuit for performing signal processing for detecting a second signal with respect to the meandering reproduction signal obtained based on the meandering, which is reproduced from the optical recording medium formed by meandering with the signal. Differentiating means for obtaining a differential signal by performing differentiation on, a peak hold means for outputting a peak hold signal obtained by performing peak hold on the input differential signal, and a level based on the input peak hold signal. Slice level setting means for determining a slice level for the differentiated signal, and determining that the level of the differentiated signal has exceeded the slice level It was decided to configure a detectably configured signal detecting means and the second signal by using the detection signal obtained can.

According to each of the above-described configurations, peak hold is performed on a signal to be processed (processed signal, meandering reproduction signal) or a differential signal of the signal to be processed. This makes it possible to obtain a signal substantially following the peak level of another signal (or the second signal) having a large amplitude level or the envelope of the signal before peak hold in the signal to be processed. Then, for example, by setting a signal level obtained by changing the level of the peak hold signal as a slice level, regardless of the amplitude fluctuation, other signals having a large amplitude level in the signal to be signal processed ( Or the second signal only), it is possible to obtain a detection operation for making a comparison with the slice level.

[0024]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, a signal processing circuit according to an embodiment of the present invention will be described. The following description will be made in the following order. 1. 1. Address format of optical disk Recording / playback device 3. Configuration of mark detection circuit 3-1. Overall configuration 3-2. Level comparator and its operation (first example) 3-3. Level comparator and its operation (second example) 3-4. Level comparator and its operation (third example) 3-5. Level comparator and its operation (fourth example)

1. Address Format of Optical Disk The optical disk of this example is an optical disk that records data by a phase change method, and has a diameter of 120 mm. Also, it is a two-layered disc with a disc thickness (substrate) of 0.6 mm,
As a whole, the disk thickness is 1.2 mm.

Tracks are formed in advance on the disk by grooves (grooves), and physical addresses are expressed by wobbling (meandering) the grooves. The groove is wobbled by a signal obtained by FM-modulating the address (FSK modulation), so that the absolute address can be extracted by FM-demodulating the reproduction information from the groove. The disk is driven to rotate by a CAV (constant angular velocity) method, and the absolute address included in the groove is CAV data accordingly. The groove depth is a laser wavelength λ / 8 for recording / reproducing, the groove width is 0.48 μm, and the wobbling amplitude is 12.5 nm.
It has been. Note that the laser wavelength λ = 650 nm (−5 /
+15 nm), aperture ratio NA of optical head of recording / reproducing device
= 0.6.

In this optical disc, a groove recording method is adopted (lands are not used for recording), and a track pitch from a center of a groove to a center of an adjacent groove in a track width direction. The track pitch is set to 0.80 μm. The data is recorded at a constant linear density (CLD). The linear density is 0.35 μm / bit. However, a certain width is set as the linear density range, and in practice, a very large number of zoning settings are performed, so that the disk as a whole has a state close to a constant linear density. This is Zone CLD
(Zoned Constant Linear Density). 1 of diameter
By setting a recordable area where data can be recorded on a 20-mm disc and setting a zone CLD, a track pitch of 0.80 μm achieves a recording capacity of 3.0 GB / side on one side (one recording layer). Value.

In the disc of this embodiment, for example, management information such as control data is recorded as read-only data as an emboss area on the innermost and outermost sides. In this groove area, a track is formed in advance by a wobbling groove, and the wobbling groove expresses an absolute address. Therefore, the recording / reproducing apparatus can obtain information such as an absolute address by extracting a signal corresponding to the wobble state of the groove when driving the disk.

As an example of the groove structure of the optical disk of this embodiment, as in the example described with reference to FIG. 10A, a pre-group is formed in advance from the inner periphery to the outer periphery in a spiral shape. Note that the pre-group can be formed concentrically.

One track (one track) of the disk has a plurality of wobbling address frames. The wobbling address frame is divided into eight in the disk rotation direction as shown in FIG. 1, and each is divided into servo segments (segment0 to segment7).
It has been. One servo segment (hereinafter simply referred to as a segment) includes 48-bit information mainly including an absolute address, and wobbling per segment is 360 waves. Each segment (segment
In each wobbling address frame as (0 to segment7), 48-bit wobble data is FM-modulated to form a wobble groove.

The fine clock mark (Fine Cloth mark)
ck Mark) are formed at equal intervals on the wobbling groove. This is used to generate a reference clock for data recording by a PLL circuit. 96 fine clock marks are formed per rotation of the disk. Therefore, 12 fine clock marks are formed per segment.

Each segment (segment 0 to seg
Each wobbling address frame as the ment 7) has the configuration shown in FIG. In the 48-bit wobbling address frame, the first 4 bits are a synchronization signal (S) indicating the start of the wobbling address frame.
ync). This 4-bit synchronization pattern is 8
This is bi-phase data that forms 4-bit data using channel bits. The next 4 bits are layer information (Layer) indicating which layer of the plurality of recording layers or what kind of layer structure the disc has.

The next 20 bits are used as a track address (track number) as an absolute address on the disk. Further, the next 4 bits indicate a segment number. The segment number value is segment0 to segment
The segment number is a value of “0” to “7” corresponding to t7, that is, the segment number is a value indicating the circumferential position of the disk. The next two bits are reserved, and the last 14 bits of the wobbling address frame are error-correcting codes (C
RC) is formed.

As described above, fine clock marks are formed at equal intervals in the wobbling address frame. FIG. 2 shows the state of the fine clock mark. Assuming that 48 bits of data are recorded in each wobbling address frame and one bit is represented by seven waves (carriers) of a predetermined frequency signal as shown in FIG. , There will be 360 waves. Assuming that the optical disc 1 is rotated at 1939 revolutions per minute, the frequency of this carrier is 93.1 KHz.

As shown in FIG. 2, in the wobbling address frame shown in FIG. 3, one bit is assigned to every four bits of the address information for the fine clock mark, that is, four bits are used as a period. The fine clock mark is superimposed on one of the bits. The first one bit in units of four bits is a bit including a fine clock mark, and the remaining three bits are bits not including a fine clock mark. The bit including the fine clock mark is shown enlarged in the lower part of FIG. 2, and as shown, a waveform as the fine clock mark FCK is included at the center position of the data bit length. The actual wobble amplitude of the groove on the disk is, for example, about 12 nm due to the address data. The wobble amplitude instantaneously increases to, for example, about 30 nm in a portion corresponding to the fine clock mark FCK.

As described above, 12 fine clock marks are recorded every three bits in one frame, and therefore, 96 (= 1) in one rotation (one track).
2 × 8) fine clock marks are recorded. This fine clock mark (PLL clock generated from the fine clock mark in the recording / reproducing apparatus)
Can be information indicating the circumferential position, which is finer than the segment number.

The carrier frequency of each 48-bit data is set to a value corresponding to each data. Each data such as the track number is bi-phase modulated and then frequency-modulated, and the pre-groove is wobbled with this frequency-modulated wave.

As can be seen from the above description, the wobble of the disc is obtained by using the wobbling address frame (see FIG. 3) on which the fine clock mark is superimposed.
FSK (Frequency) which is one of FM modulation (frequency modulation)
It is formed by wobbling a groove with a signal obtained by performing Shift Keying (modulation).
That is, the sequence of the data value of a certain data portion in the wobbling address frame is, for example, as shown in FIG.
As shown in the figure, '0', '1', '1', '0',
Assume that it is '1'. By FSK-modulating this, as shown in FIG. 4 (b), for example, for each bit period, frequencies f0, f1, f1, f0, f1 (f0 and f1 are predetermined carrier frequencies different from each other). The signal changes in frequency. In this case, the amplitude level is constant. This is the basic amplitude of the wobble. That is, the wobble width is constant and the frequencies f0, f1, f1, f0, f
A wobble corresponding to No. 1 is formed.

Actually, the fine clock mark is superimposed on the wobble shape, which is the wobbling address frame shown in FIG. 4B, so that the wobble shape recorded on the disk of the present embodiment is obtained. Is as shown in FIG. The fine clock mark FCK has a larger amplitude than the wobble shape of the wobbling address frame. Therefore, even if the fine clock mark FCK has an actual wobble shape, the fine clock mark FCK has a predetermined wobble width larger than other wobble portions. is there. Then, as described later, by detecting the fine clock mark FCK from the read signal (wobble signal Wb) from the disk, the fine clock mark FCK as shown in FIG.
A pulse synchronized with the insertion timing is obtained, which is used as a clock for recording data.

2. Recording / reproducing device 2-1. Overall Configuration FIG. 5 shows an example of the configuration of an optical disk recording / reproducing apparatus for recording or reproducing data on a disk in the format described above. The spindle motor 31
The disk 1 is rotated at a predetermined speed. That is, CAV rotation drive is executed. Here, it is assumed that the disc 1 includes a disc having the format described above.
The optical head 32 irradiates the disk 1 with laser light, records data on the disk 1, and reproduces data from the reflected light.

The recording / reproducing circuit 33 temporarily records the recording data input from a device (not shown) (for example, a host computer) in the memory 34, and when the memory 34 stores one cluster of data as a recording unit, The data for one cluster is read out and subjected to encoding such as interleaving, addition of an error correction code, and 8-16 modulation to generate recording data. Then, the recording data is transferred to the optical head 3
2 to execute a recording operation on the disk 1. At the time of reproduction, the recording / reproducing circuit 33 includes the optical head 3
The data obtained from 2 is decoded by interleaving or the like by 8-16 demodulation and error correction processing, and the decoded data is output to a device (not shown).

At the time of recording, the address generating / reading circuit 35
Generates an address to be recorded in a track (pre-group) (this is not an address recorded as wobbling information) in response to control from a control circuit 38 formed by a microcomputer, for example. Output to the reproduction circuit 33. The recording / reproducing circuit 33 adds the address to the recording data, outputs the address to the optical head 32, and records it as address data.

The recording / reproducing circuit 33 separates the address data from the reproduced data reproduced from the track of the disk 1 when the reproduced data includes the address data.
Output to The address generating / reading circuit 35 outputs the read address to the control circuit 38.

Further, the address generating / reading circuit 35 detects a frame synchronization signal FS (frame sync) in the data, and outputs the detection result to a frame sync (FS) counter 49. The FS counter 49 counts the FS detection pulse output from the address generation / read circuit 35 and outputs the count value to the control circuit 38.

The mark detection circuit 36 basically operates as a wobble signal Wb reproduced and output by the optical head 32.
(A signal obtained based on wobbling), a component corresponding to the fine clock mark is detected. In this embodiment, the detection is performed by comparing the wobble signal Wb with a slice level Lsc set as described later.

The mark detection circuit 36 is also configured to determine the periodicity of a detection pulse as a fine clock mark detection signal. That is, since the fine clock mark is generated at a constant period (every 4 bits), it is determined whether or not the edge detection signal of the fine clock mark is a detection pulse generated at the constant period. However, if the detection pulse is generated at a constant period, the detection pulse is used as a correct fine clock mark detection signal in the subsequent stage.
Output to the phase comparator 42 of the LL circuit 41. The mark detection circuit 36 also generates a pseudo pulse at a predetermined timing so that the PLL circuit 41 at the subsequent stage does not lock to an incorrect phase when a detection pulse is not input at a fixed cycle. Is done. The configuration relating to the detection of the fine clock mark FCK in the mark detection circuit 36 will be described later.

The address reproducing circuit 37 reproduces address information Ad from the wobbling signal Wb output from the optical head 32. As described with reference to FIG. 3, the track number (track address) and the segment number (circumferential position information) are recorded in the 48-bit wobbling address frame. Is obtained as address information Ad,
It is supplied to the control circuit 38. The track address of the reproduced address information Ad is also supplied to the cluster counter 46. The internal configuration of the address reproduction circuit 37 according to the present embodiment will be described later.

The PLL circuit 41 includes a phase comparator 42,
Low-pass filter 43, voltage controlled oscillator (VCO) 4
4 and a frequency divider 45. Phase comparator 42
Compares the phase of the input from the mark detection circuit 36 with the phase of the input from the frequency divider 45, and outputs the phase error. The low-pass filter 43 compensates for the phase of the phase error signal output from the phase comparator 42 and outputs it to the VCO 44. VC
O44 generates a clock having a phase corresponding to the output of the low-pass filter 43 and outputs the clock to the frequency divider 45. Divider 4
Numeral 5 divides the clock input from the VCO 44 by a predetermined value and outputs the frequency-divided result to the phase comparator 42.

The clock output from the VCO 44 is supplied to a required circuit as a recording clock, and is also supplied to a cluster counter 46. Cluster counter 4
Reference numeral 6 denotes a VCO 44 based on the track address in the wobbling signal supplied from the address reproducing circuit 37.
Is counted, and when the counted value reaches a predetermined value (a value corresponding to the length of one cluster), a cluster start pulse is generated and output to the control circuit 38. ing.

The thread motor 39 is controlled by a control circuit 38 to move the optical head 32 to a predetermined track position on the disk 1. The control circuit 38
Controls the spindle motor 31 to rotate the disk 1 at a predetermined speed.

The ROM 47 stores a table defining the correspondence between the track numbers in the address frame and the zones into which the data recording area of the disk 1 is divided, and, if necessary, the relationship between the zones and the bands to which the zones correspond. Is stored. Although the zoning format of this example will not be described in detail, the control circuit 38
Controls each unit so that a recording / reproducing operation according to the zoning format is executed.

That is, when the control circuit 38 obtains a point to be accessed by a sector number, the control circuit 38 performs a process of replacing the sector number with a track number and a data frame number in the track. For this purpose, the ROM 47 stores a sector number, a zone number, an ECC block number,
A table is stored that shows the correspondence between the number of frames per zone, the track number, the number of frames per track, and the like. The control circuit 38 reads the track number corresponding to the designated sector number and the number of data frames in the track with reference to the table.

On the other hand, the control circuit 38 detects the track number, that is, the current track address detected from the wobbling signal, based on the track address obtained by the address reproducing circuit 37. Then, when the desired (access target) track number is detected by the address reproducing circuit 37, the control circuit 38 next detects the reference position of the track. On the disk 1, a track number is recorded as wobbling information, and a clock synchronization mark is recorded in a 4-bit cycle in an address frame of each track. Address frame (segment number 0
The fine clock mark inserted in the first bit out of the 48 bits of the address frame is detected as a reference fine clock mark.

Further, the control circuit 38 resets the count value of the FS counter 49 when one reference fine clock mark is detected for one round of the track. The FS counter 49 thereafter counts the frame synchronization signal when it is detected. When the count value of the FS counter 49 reaches a value corresponding to the sector number to be searched, the sector is determined to be a sector to be searched.

When the control circuit 38 starts recording in a predetermined sector, the control circuit 38 sets the recording start position of recording in that sector from (0-2) ± 4 bytes from the zero-cross timing of the reference fine clock mark. Is controlled so as to be within the range. As described above, the control circuit 38 determines an arbitrary position on the track (an arbitrary position during one rotation) from the count value of the recording clock with reference to the clock synchronization mark detected first, for example, in the frame of frame number 0 (address frame). At the position ()) can be controlled. That is, access can be made on a track and data frame basis.

When an arbitrary position on a track is accessed in this way, it is necessary to determine to which zone the access point belongs, and to generate a clock having a frequency corresponding to the zone in the VCO 44. There is.
Therefore, the control circuit 38 determines whether or not the read track number is a new zone different from the previously accessed zone, and if it is a new zone, controls the frequency divider 45 to Set the division ratio corresponding to the new zone. As a result, a recording clock having a different frequency is output from the VCO 44 for each zone.

3. Configuration of mark detection circuit 3-1. Overall Configuration FIG. 6 shows the configuration of the mark detection circuit 36 shown in FIG.
2 shows a configuration as a circuit part for detecting CK. Accordingly, the configuration of the circuit system for determining the periodicity of the fine clock mark FCK and for interpolating by generating a pseudo pulse is omitted here.

The wobble signal Wb output from the optical head 32 is input to a level comparator 62 and a differentiating circuit 63 via a terminal 61. In this case, the level comparator 62 outputs an edge detection signal Edge by comparing the slice level Lsc set as described later with the level of the input wobble signal Wb. Supply.

The edge detection signal Edge referred to here is
This is a detection signal in which a pulse is obtained at a timing corresponding to the fine clock mark FCK in the input wobble signal Wb. For example, if the wobble signal Wb shown in FIG. 13A is input to the level comparator 62, the edge detection signal Edge is as shown in FIG. 13B. That is, in the wobble signal Wb, the signal has a waveform such that an H-level pulse is obtained, for example, corresponding to the timing of the waveform of the fine clock mark FCK protruding upward.

The differentiating circuit 63 generates and outputs a differential signal DIF for the input wobble signal Wb.
In this case, the differential signal DIF is based on the wobble signal Wb as shown in FIG.
As shown in FIG. 3C, a signal corresponding to the fine clock mark FCK protruding at a large level becomes a signal from which a peak differential waveform can be suddenly obtained. This differential signal D
The IF is output to the level comparator 64.

In the level comparator 64, the differential signal D
By comparing the IF level with the slice level Lsc1 or Lsc2 set as described later, the timing of the differential waveform portion corresponding to the fine clock mark FCK is detected, and as shown in FIG. And outputs the window signal Window. In this case, the window signal Window is set to the fine clock mark FC.
The signal is a signal from which an H-level pulse is obtained corresponding to the differential waveform portion corresponding to K. This window signal Wi
ndown is output to the AND gate 65.

In the AND gate 65, the input edge detection signal Edge (FIG. 13B) and the window signal W
By taking a logical product with the window (FIG. 13D),
The clock mark signal CLM shown in FIG. In the present embodiment, the clock mark signal C
LM is a detection signal for the fine clock mark obtained based on the wobble signal Wb. In the actual mark detection circuit 36, on the basis of the clock mark signal CLM, the periodicity of the fine clock mark FCK is determined as described with reference to FIG. 5, and the clock mark signal CLM is lost. In such a case, signal processing such as generation of a pseudo pulse is performed to generate an intrinsic mark detection signal, and the PLL is generated.
This is output to the circuit 41.

3-2. Level Comparator and Its Operation (First Example) As described above, it is known that the wobble signal Wb read from the optical head 32 fluctuates in amplitude level due to various factors. Therefore, in this embodiment,
In the mark detection circuit 36 having the configuration shown in FIG. 6, the level comparators 62 and 64 have the following configuration so that the clock mark signal CLM is properly detected regardless of the fluctuation of the wobble signal Wb amplitude level. Is adopted.

FIG. 7 shows a configuration example as a first example of the level comparator 62 or the level comparator 64 according to the present embodiment. The level comparator 62 (64) shown in this figure includes a peak hold circuit 73, a gain circuit 74, and a comparator 72.

Here, assuming that the configuration shown in FIG. 7 is a level comparator 62, the wobble signal Wb from the optical head 32 is input via a terminal 71 and is input to a non-inverting input of a comparator 72, and The signal is branched and input to the peak hold circuit 73.

In this case, the time constant of the peak hold circuit 73 is set to a value sufficiently slower than the period of the fine clock mark FCK appearing in the wobble signal. Therefore, the peak hold level Lp, which is the level of the peak hold signal output from the peak hold circuit 73,
As shown in FIG. 8, h is held at the peak value of the fine clock mark FCK, which is the peak of the wobble signal Wb, and this held level is almost maintained until the next fine clock mark FCK appears. Waveform. That is, for example, the wobble signal Wb
With its own amplitude fluctuation, fine clock mark FC
Even if there is a change in the amplitude level of K, a waveform is obtained in which the peak value (the peak value of the fine clock mark FCK) of the wobble signal Wb is substantially maintained following the change in the amplitude. is there.

Therefore, in the gain circuit 74 at the subsequent stage of the peak hold circuit 73, a value obtained by multiplying the inputted peak hold level Lph by a predetermined constant smaller than 1 is set as the slice level Lsc, and the comparator 72 Input to the inverted input of. Here, the constant for setting the slice level Lsc is set so as to obtain a level having a margin that does not sufficiently reach the peak of the wobble signal component corresponding to the address information. The slice level Lsc thus set is obtained as a level slightly lower than the peak hold level Lph, for example, as shown in FIG. However,
At this time, a level at which the slice of the wobble signal component corresponding to the address information is not sliced is set.

Then, the comparator 72 compares the slice level Lsc set as described above with the level of the wobble signal Wb, and
When the level of b exceeds the slice level Lsc, an H level signal is output. In this case, this becomes the edge detection signal Edge. As a result, even if the wobble signal Wb varies in amplitude as shown in FIG. 8, for example, the amplitude other than the fine clock mark FCK does not exceed the slice level Lsc, and only the amplitude of the fine clock mark FCK is changed. It is possible to reliably obtain a state that exceeds the slice level Lsc. This is because, regardless of the amplitude fluctuation of the wobble signal Wb, the comparator 72 detects the H-level detection signal corresponding to only the signal component of the fine clock mark FCK (that is, FIG. 13).
This means that the edge detection signal Edge) shown in (b) is almost certainly output. Conversely, it is possible to prevent the waveform portion of the wobble signal Wb other than the fine clock mark FCK from being erroneously detected, and prevent the amplitude portion of the fine clock mark FCK from being sliced by the slice level Lsc and causing omission in detection. Will be.

The configuration shown in FIG. 7 can be applied to the level comparator 64 to which the differentiated signal DIF of the differentiating circuit 63 is input, as described above. In this case, for example, a slice level Lsc1 as shown in FIG. 13C is obtained for the differential waveform DIF.
That is, in the differential waveform DIF, a level slightly lower than this is set after almost following the peak obtained corresponding to the fine clock mark FCK. Also at this time, the level setting of the slice level Lsc1 (gain setting of the gain circuit 74) is performed in consideration of the fact that waveform portions other than those corresponding to the fine clock mark FCK do not exceed the slice level Lsc1.

For example, in actuality, a variation also appears in the differential waveform DIF in accordance with the variation in the wobble signal Wb.
Slice level Lsc1 and differential waveform DIF as described above
Is input to the comparator 72, so that only the waveform portion corresponding to the fine clock mark FCK is sliced from the differential waveform DIF, so that an H-level signal can be reliably output. That is, it is possible to accurately detect the waveform corresponding to the fine clock mark FCK in the differential waveform DIF without generating erroneous detection or omission of detection, and to generate the window signal Window (FIG. 13D).

Accordingly, the mark detection circuit 36 shown in FIG.
In FIG. 7, the configuration shown in FIG.
In the present embodiment, by adopting 2, 64, the clock mark signal CLM can be accurately detected regardless of the level fluctuation of the wobble signal Wb.

3-3. Level Comparator and Its Operation (Second Example) Next, the configuration of a level comparator 62 (64) as a second example of the present embodiment will be described with reference to FIGS.

FIG. 9 shows a configuration of a level comparator 62 (64) as a second example. In this figure, the same parts as those in FIG. 7 are denoted by the same reference numerals.

The level comparator 62 (6) shown in FIG.
As 4), a form in which a low-pass filter 76 is provided between the gain circuit 74 and the inverted input of the comparator 72 is adopted.

If the configuration shown in FIG. 9 is the level comparator 62, the time constant to be set for the peak hold circuit 73 here is longer than the period of the fine clock mark FCK appearing in the wobble signal. The setting is made so as to be fast and slower than the cycle of the amplitude component corresponding to the address information.

Therefore, as shown in FIG. 10, the peak hold level Lph output from the peak hold circuit 73 in FIG. 9 is the wobble signal corresponding to the address and the peak of the wobble signal corresponding to the fine clock mark FCK. As a result, a level of a waveform which is close to the envelope of the wobble signal is obtained.

Therefore, in this case, the peak hold level Lph obtained in this way is output by the gain circuit 74 multiplied by one or more predetermined constants, and then the predetermined time constant is set. Through the low-pass filter 76. Here, as the slice level Lsc obtained through the low-pass filter 76, the fine clock mark FCK is obtained by removing the high frequency component.
Will be suppressed. As a result, as shown in FIG. 10, after changing so as to substantially follow the envelope waveform of the wobble signal component corresponding to the address, the level is slightly higher than the envelope waveform of the wobble signal component corresponding to the address. Waveform is slice level Ls
c will be obtained.

The slice level Lsc of such a waveform
And the wobble signal Wb, which is the original signal,
By comparing at 2, the amplitude of the wobble signal corresponding to the address information is not detected, and the amplitude of the fine clock mark FCK is reliably detected, so that the edge detection signal Edge can be obtained. .

Similarly, when the configuration shown in FIG. 9 is applied to level comparator 64, peak hold circuit 73
Represents the fine clock mark F as the differential signal DIF
The period is set so as to be faster than the period in which the waveform portion corresponding to CK appears, and later than the period of the amplitude component corresponding to the address information. (As a result, the configuration shown in FIG. The time constant of the peak hold circuit 73 when applied to the level comparator 62 may be the same.) The slice level finally obtained through the low-pass filter 76 is the slice level Ls with respect to the differential waveform DIF as shown in FIG.
The level shown as c2 is obtained. Thereby, the fine clock mark FC is detected without detecting the waveform portion corresponding to the address information in the differential waveform DIF.
Only the waveform portion corresponding to K can be reliably detected and output as a window signal Window. As a result, the clock mark signal CLM (FIG. 13) output from the AND gate 65 (see FIG. 6)
(E)), it is possible to obtain an appropriate signal without detection omission or erroneous detection.

3-4. FIG. 11 shows a level comparator 62 (6) as a third example.
4) shows the configuration. In this figure, the same parts as those in FIG. The level comparator 62 (64) shown in this figure is different from the configuration shown in FIG.
7 is provided. The fine clock mark removal filter 77 is formed by, for example, a band-pass filter.
Is provided for the preceding stage.

As described above, wobble signal Wb corresponds to a signal obtained by superimposing fine clock mark FCK on a signal obtained by modulating address information by FSK modulation. Therefore, assuming that the configuration shown in FIG. 11 is the level comparator 62, the FSK modulation carrier frequency (f0, f1 (FIG.
If a characteristic as a band-pass filter that passes nearby frequency components is given, the peak portion corresponding to the fine clock mark FCK is considerably suppressed as the wobble signal Wb input to the subsequent peak hold circuit 73. Thus, a waveform in which the steep level fluctuation of the portion corresponding to the fine clock mark FCK is further suppressed can be obtained as the peak hold level Lph which is the output of the peak hold circuit 73. Become. That is, as the slice level Lsc finally obtained, a waveform that more faithfully follows only the fluctuation of the signal component corresponding to the address information in the wobble signal is obtained. In other words, a waveform change due to the influence of the fine clock mark FCK in the slice level Lsc is further suppressed.

Further, by the function of the fine clock mark removal filter 77 being a band pass filter, it is possible to suppress the fluctuation of the DC component existing in the wobble signal Wb.

The above-described configuration is also applicable to the level comparator 64 in this case.
If the band is set so as to pass the frequency band (f0, f1) of the waveform portion corresponding to the address information in F, the slice level Ls shown in FIG.
As c2, it is possible to obtain a waveform that follows the waveform corresponding to the address information of the differential waveform DIF and that is further less affected by the differential waveform of the fine clock mark FCK, and that the direct current due to the influence of the wobble signal as the original signal can be obtained. The effect of suppressing the components can also be obtained.

As described above, when the fine clock mark removal filter 77 is provided, the edge detection signal Edge or the window signal Window is generated under the condition that the possibility of erroneous detection or detection omission is further reduced. As a result, a more accurate detection operation of the fine clock mark FCK (clock mark signal CLM) is expected.

3-5. Level Comparator and Its Operation (Fourth Example) FIG. 12 shows a level comparator 62 (6
4) shows the configuration. Also in this figure, the same parts as those in FIGS. 9 and 11 are denoted by the same reference numerals, and the description thereof will be omitted.

The level comparator 62 (6
As 4), it can be seen that a configuration in which a low-pass filter 78 is provided instead of the fine clock mark removal filter 77 in the configuration shown in FIG.

Even with such a configuration, the wobble signal Wb (or the differential signal DIF) passes through the low-pass filter 78, thereby suppressing a sharp change in the signal component corresponding to the fine clock mark FCK from the signal. As a result of the above signal processing performed by the functional circuit unit, a slice level Lsc (or Lsc2) of a waveform having a smaller level change corresponding to the fine clock mark FCK is obtained. Edge and a detection operation of the window signal Window are obtained.

As described above, the mark detection circuit 36 of the present embodiment
Although four examples of the configuration of the level comparators 62 and 64 have been shown as the configuration, the actual configuration is not limited to this. For example, the low-pass filter 78 described with reference to FIG. 12 may be provided in addition to the configuration illustrated in FIG. 11 in order to expect a more reliable detection operation. In the configuration, if a sufficiently accurate detection result can be obtained by the operation of the low-pass filter 78 at the preceding stage, for example, the low-pass filter 76 at the subsequent stage may be omitted as shown by a broken line.

Which of the above four examples should be used as the actual level comparators 62 and 64 may be arbitrarily determined in consideration of the actual detection result and the like. Assuming that the configuration of the first example is adopted, the level comparator 64 arbitrarily determines the combination of the configuration examples to be adopted between the level comparators 62 and 64, such as adopting a configuration other than the first example. It doesn't matter. Further, in the description of each of the above four examples, the configuration in which the slice level is set with respect to the upper amplitude of the wobble signal has been described. Of course, it is also possible to adopt a configuration in which is set.

In the present invention, the information recorded as a wobble is not limited to address information and a synchronization detection signal such as a fine clock mark.
The present invention is applicable even when other information is recorded. In the above-described embodiment, the case where wobble is recorded in the groove on the disc has been described. However, for example, a disc having a format in which a land as a convex portion is defined as a track and a wobble is formed on this land is defined. The present invention can be applied to any of the above. Further, the present invention is not limited to the configurations of the recording / reproducing apparatus and the mark detection circuit as the above-described embodiments. Further, various numerical values described as the disk format are also examples, and may be changed as appropriate in practice.

[0091]

As described above, according to the present invention, a signal (specific signal, first signal) corresponding to address information such as a wobble signal is detected for synchronization detection having a larger amplitude than this signal. A wobble signal or a differential signal obtained by differentiating the wobble signal when detecting the fine clock mark from the wobble signal (meandering reproduction signal, processing signal) on which the fine clock mark (other signal, second signal) is superimposed. The slice level for the wobble signal is set based on the peak hold signal obtained by peak-holding the signal, and based on the detection signal obtained when the amplitude of the wobble signal is equal to or higher than this slice level,
Fine clock marks are detected.

In this case, the peak hold signal is a signal substantially following the peak level of the fine clock mark or the envelope waveform of the wobble signal itself, regardless of the fluctuation of the amplitude level of the wobble signal. And
For example, when the slice level is set by appropriately varying the level of the peak hold signal, the slice level is not a certain level but has a level that fluctuates according to the amplitude fluctuation of the wobble signal. Therefore, if the slice level obtained in this manner is compared with the wobble signal (or differential signal) as the original signal and the detection is performed, the wobble signal component corresponding to the address information is not detected, and the fine signal is not detected. Only the signal component corresponding to the clock mark can be detected. In other words, even if the original wobble signal has a fluctuation in the amplitude level, an accurate fine clock mark detection operation can be obtained by performing the detection with the slice level following the fluctuation.

Further, by providing low-pass filter means before or after the peak hold circuit that outputs the peak hold signal, a steep amplitude corresponding to a fine clock mark in the peak hold signal is consequently suppressed. That is, by setting the slice level based on this signal, the detection of the signal corresponding to the fine clock mark from the wobble signal or the differential signal is performed more accurately.

Also, for example, by providing a band-pass filter before the peak hold circuit, a steep change in amplitude corresponding to the fine clock mark in the peak hold signal can be suppressed. Alternatively, it is also possible to suppress DC fluctuations in the differential signal, and thus, in this case, an accurate detection operation of the signal corresponding to the fine clock mark is expected.

[Brief description of the drawings]

FIG. 1 is an explanatory diagram of a CAV format of a wobbling address of a disk according to an embodiment.

FIG. 2 is an explanatory diagram of a segment of a wobbling address of the disk according to the embodiment;

FIG. 3 is an explanatory diagram of a frame structure of a wobbling address of the disk according to the embodiment;

FIG. 4 is an explanatory diagram showing a wobble shape obtained by FSK modulation and a wobble shape including a fine clock mark according to the embodiment.

FIG. 5 is a block diagram of a recording / reproducing device to which the disc of the embodiment corresponds.

FIG. 6 is a block diagram illustrating a configuration of a mark detection circuit according to the embodiment;

FIG. 7 is a block diagram illustrating a configuration of a level comparator (first example) provided in the mark detection circuit illustrated in FIG. 6;

8 is a waveform chart showing an operation of the level comparator shown in FIG.

FIG. 9 is a block diagram illustrating a configuration of a level comparator (second example) provided in the mark detection circuit illustrated in FIG. 6;

FIG. 10 is a waveform chart showing an operation of the level comparator shown in FIG.

11 is a block diagram showing a configuration of a level comparator (third example) provided in the mark detection circuit shown in FIG.

12 is a block diagram showing a configuration of a level comparator (fourth example) provided in the mark detection circuit shown in FIG.

FIG. 13 is a waveform chart showing an operation of the mark detection circuit shown in FIG.

FIG. 14 is an explanatory diagram conceptually showing a wobble shape including a fine clock mark.

FIG. 15 is a waveform diagram showing a relationship between a slice level setting for detecting a fine clock mark from a wobble signal and a wobble signal.

FIG. 16 is a block diagram showing a configuration example for obtaining an edge detection signal used for fine clock mark detection.

[Explanation of symbols]

1 disc (optical disc), 31 spindle motor, 32 optical head, 33 recording / reproducing circuit, 34 memory, 35 address generating / reading circuit, 36 mark detecting circuit, 37 address reproducing circuit, 38 control circuit, 39
Thread motor, 41 PLL circuit, 42 phase comparator, 43 low-pass filter, 44 VCO, 45 frequency divider, 46 cluster counter, 47 RAM, 62,
64 level comparator, 63 differentiator, 72 comparator, 73 peak hold circuit, 74 gain circuit, 76, 78 low pass filter, 77 fine clock mark removal filter

Claims (16)

[Claims] 1. A processing signal formed by superimposing another signal having an amplitude larger than the amplitude of a specific signal on a specific signal, and detecting the other signal. A peak hold means for outputting a peak hold signal obtained by performing peak hold on the input processing signal, and a signal processing circuit for performing a signal processing based on a level of the input peak hold signal. Slice level setting means for determining a slice level for the processing signal, and a detection signal obtained when the level of the processing signal exceeds the slice level is used to detect the other signal. A signal processing circuit comprising: signal detection means. 2. A low pass filter means for passing a predetermined low frequency band with respect to a peak hold signal output from said peak hold means, wherein said peak hold signal passed through said low pass filter means is supplied to said slice level setting means. The signal processing circuit according to claim 1, wherein the signal processing circuit is configured to be input to the signal processing circuit. 3. A low-pass filter for passing the processed signal through a predetermined low band, wherein the processed signal via the low-pass filter is input to the peak hold means. The signal processing circuit according to claim 1, wherein: 4. A band pass filter means for passing a predetermined band with respect to the processed signal, wherein the processed signal passed through the band pass filter means is inputted to the peak hold means. The signal processing circuit according to claim 1, wherein 5. A track for recording data is formed by superimposing a second signal having a larger amplitude level than the first signal on a first signal corresponding to specific information. A signal processing circuit for performing signal processing for detecting the second signal with respect to the meandering reproduction signal obtained based on the meandering, which is reproduced from the optical recording medium formed by meandering with the signal. Peak hold means for outputting a peak hold signal obtained by performing peak hold on the obtained meandering reproduction signal; and a slice level for determining a slice level for the meandering reproduction signal based on the level of the input peak hold signal. Setting means, utilizing a detection signal obtained when the level of the meandering reproduction signal exceeds the slice level And a signal detecting means for detecting the second signal. 6. A low-pass filter means for passing a predetermined low band with respect to a peak hold signal output from said peak hold means, wherein said peak hold signal passed through said low-pass filter means is applied to said slice level setting means. 6. The signal processing circuit according to claim 5, wherein the signal processing circuit is configured to be input to the signal processing circuit. 7. A low-pass filter means for passing a predetermined low frequency band of the meandering reproduction signal, wherein the meandering reproduction signal via the low-pass filter means is inputted to the peak hold means. The signal processing circuit according to claim 5, wherein 8. A band pass filter means for passing a predetermined band with respect to the meandering reproduction signal, wherein the meandering reproduction signal passed through the band pass filter means is inputted to the peak hold means. The signal processing circuit according to claim 5, wherein: 9. A processing signal formed by superimposing another specific signal having an amplitude larger than that of the specific signal on a specific signal, and detecting the other signal. Signal processing circuit for performing a signal processing for differentiating the processed signal to output a differentiated signal, and a peak for outputting a peak hold signal obtained by performing a peak hold on the input differentiated signal. Holding means; slice level setting means for determining a slice level for the differentiated signal based on the level of the input peak hold signal; obtained when the level of the differentiated signal exceeds the slice level Signal detection means configured to detect the other signal by using the detection signal. Signal processing circuit, wherein the door. 10. A low pass filter means for passing a predetermined low band with respect to a peak hold signal outputted from said peak hold means, wherein said peak hold signal passed through said low pass filter means is supplied to said slice level setting means. The signal processing circuit according to claim 9, wherein the signal processing circuit is configured to be input to the signal processing circuit. 11. A low-pass filter means for passing the differential signal through a predetermined low band, wherein the differential signal passed through the low-pass filter means is inputted to the peak hold means. The signal processing circuit according to claim 9, wherein: 12. A band pass filter means for passing a predetermined band with respect to said differential signal, wherein said differential signal passed through said band pass filter means is inputted to said peak hold means. The signal processing circuit according to claim 9, wherein: 13. A track for recording data is formed by superimposing a second signal having an amplitude level larger than the first signal on a first signal corresponding to specific information. A signal processing circuit that performs signal processing for detecting the second signal with respect to a meandering reproduction signal obtained based on the meandering, which is reproduced from an optical recording medium that is formed by meandering with the signal. A differentiating means for obtaining a differential signal by differentiating the meandering reproduction signal; a peak holding means for outputting a peak hold signal obtained by performing a peak hold on the input differential signal; Slice level setting means for determining a slice level for the differentiated signal based on the level; A signal detection unit configured to detect the second signal by using a detection signal obtained when the signal level exceeds the rice level. 14. A low pass filter means for passing a predetermined low band with respect to a peak hold signal output from said peak hold means, wherein said peak hold signal passed through said low pass filter means is supplied to said slice level setting means. The signal processing circuit according to claim 13, wherein the signal processing circuit is configured to be input to the signal processing circuit. 15. A low pass filter means for passing the differential signal through a predetermined low frequency band, wherein the differential signal passed through the low pass filter means is inputted to the peak hold means. The signal processing circuit according to claim 13, wherein: 16. A band pass filter means for passing a predetermined band with respect to the differentiated signal, wherein the differential signal passed through the band pass filter means is inputted to the peak hold means. The signal processing circuit according to claim 13, wherein: