JPH0664855B2 - Frame synchronization detector - Google Patents

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a frame synchronization detecting device capable of surely detecting frame synchronization in a recording device having a data recording format in which a frame structure is recorded.

[Prior Art] Although an apparatus using a magnetic recording medium such as a magnetic tape or a magnetic disk is widely used as an auxiliary storage device of a computer system, in recent years, the recording density is remarkably higher than those of these magnetic recording media. There is a proposal to use a possible optical recording medium (for example, an optical disk) as an auxiliary storage device.

For example, in the case of an optical disc, the diameter of 1
2 μm pits (small holes) on the surface recording track
to record data by forming in μm order period (interval), the storage capacity of ¹ 10 per sheet in a diameter of about 30 cm ¹
It is a 10 ^{1 2} bit about. Usually, one recording track is set in a spiral shape, or a plurality of recording tracks are set in a concentric shape at predetermined intervals.

In general, the access speed of the auxiliary storage device is much slower than that of the main storage device, so that data is recorded in a continuous area in blocks of a certain amount.

At that time, a predetermined block of data is configured in a sector so that reading and writing of data can be surely performed in a short time.
An address (sector address) is assigned to each sector for identification.

7 (a) and 7 (b) show an example of a data recording format in a track of an optical disc.

In the same figure (a), in the track TR, a plurality of sectors SC, each consisting of a pre-formatted area PF, a data area DF, and a gap GP1 separating the pre-formatted area PF and the data area DF, are separated from each other by a gap GP2. Is set automatically.

The pre-format area PF is divided into tracks T in advance by separating the data area DF and the gap GP2 by the number of bits.
Formed in R.

In addition, as shown in FIG.
PF is a sync signal for matching the circuit conditions, that is, a preamble composed of a bit sync signal BS for synchronizing the bit clock of the data writing / reading circuit with the generation timing of the recording data, for detecting this pre-formatted area PF. The sector synchronization signal SS is composed of a bit string (pattern) having a sharp autocorrelation, and the sector address SA for identifying the sector SC.

A PLL (P-hase Locked Loop) for extracting a bit clock and data based on a read signal from the optical pickup unit as a bit synchronization signal BS forming a preamble
A signal is used so that the circuit can be locked properly.
For example, it is a signal that changes the state of the read signal in the minimum inversion period (that is, "010101 ..." In which the recording state on the optical disc is the repetition of the minimum pit length).

Further, the data area DF includes a plurality of data having a frame structure with a frame synchronization signal FS and a preamble (bit synchronization signal B added at the beginning of these data.
S). The number of bits of the preamble in the data area DF is smaller than that of the preamble in the preformat area PF.
Has a sharp pattern of autocorrelation similar to the sector synchronization signal SS.

It should be noted that the preamble of the above preformatted area PF
BS, sector synchronization signal SS, sector address SA, gap GP
1, GP2, the preamble BS of the data area DF, and the frame synchronization signal FS are recorded on the optical disc in a non-modulated state, and the frame data of the data area DF is recorded in a state of being subjected to predetermined modulation.

Now, when recording data in such a recording format, first, the sector synchronization signal SS is detected after bit synchronization is performed with the preamble of the preformatted area PF, and the sector address SA is read based on the detection timing.

If it represents the desired sector, write the preamble of the data area DF after the gap GP1 and then the first
The frame data of the frame is written after the frame synchronization signal FS, and the frame synchronization signal FS and the frame data of each frame are sequentially recorded.

When reading data, read the sector address SA in the same way as above, and if it indicates the desired sector,
After re-synchronizing the bits with the preamble in the data area, the frame data for each frame is read based on the timing at which the frame synchronization signal FS is detected.

Then, the read frame data is converted into original data before modulation by a predetermined demodulation process.

In this way, the data is recorded and read by referring to the pre-formatted area recorded in advance.

By the way, although the optical disc has a remarkably large recording density as described above, it is considered that the optical disc is considerably susceptible to the bit error rate and the rotational fluctuation of the drive system.

On the other hand, in general, since a systematic error correction code is added to each frame data before modulation, even if a data error occurs, it can be completely recovered to some extent, and there is no major problem.

Also, considering the case where the frame synchronization signal FS could not be detected due to a bit error or rotation fluctuation, when the frame synchronization signal FS immediately before that is detected, an interpolation signal or the like is generated based on the detection timing. By doing so, it is possible to generate the frame synchronization timing in a pseudo manner, but in particular, the rotation fluctuation between the end of the preformat area PF and the detection of the first frame synchronization signal FS of the data area DF. If, for example, the values become large, the first frame synchronization signal FS may not be detected.

When such a situation occurs, it may take a relatively long time to detect the subsequent frame synchronization signal FS, and the frame synchronization cannot be detected for the data frame during that time, and as a result, the data of that portion cannot be detected. There was a problem that occurred.

Further, when the state in which the frame synchronization signal cannot be detected continues and the pseudo frame synchronization detection by the above-described interpolation signal continues, there is a possibility that the actual generation timing of the frame synchronization signal cannot be detected.

[Purpose] The present invention has been made to solve the above-mentioned disadvantages of the conventional technique, and an object of the present invention is to provide a frame synchronization detection device that is resistant to bit errors, drive system rotation fluctuations, and the like. Further, even if the state in which the frame synchronization signal cannot be detected continues, the frame synchronization signal that appears properly immediately after that can be surely detected.

[Structure] In the present invention, as the prediction function for detecting the frame synchronization signal, the maximum detection window prediction function having the maximum detection window at the beginning of the frame detection operation is used, and after the frame synchronization signal is detected, the optimum prediction function is used. Is used to speed up frame synchronization detection. Further, since the output timing of the sync detection signal is matched between when the frame sync signal is detected at a predetermined timing and when the frame sync detection is performed by the interpolated signal, even when the frame sync signal cannot be detected continuously. Immediately after that, it is possible to reliably detect the frame synchronization signal that appears properly. Further, when the frame synchronization signal can be actually detected, the output of the interpolated signal is prohibited so that an unnecessary signal is not output.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

First, the principle of the present invention will be described.

In the present invention, as shown in FIG. 1, in the preamble PA of the data area DF, a plurality of signals in which the frame synchronization signal FS is added to the beginning of the bit synchronization signal BS having the same length as the data amount of one frame are provided. Individually arranged, the frame data area FFD is detected by detecting the frame synchronization in advance with this preamble PA.
The FD is designed to be able to reliably detect frame synchronization.

The frame synchronization signal FS is composed of a bit string having a sharp autocorrelation pattern, for example, 001100111100
(12 bits).

Then, the frame synchronization detection is performed by the method as shown in FIG.

That is, when the sector is detected, first, the mode is shifted to the search mode in which the frame synchronization signal FS is detected by using the search mode prediction function FC1 having a very large detection window width with respect to the frame synchronization signal FS.

In this search mode, the search mode prediction function FC1
When the frame sync signal FS is detected by, a sync detection pulse is output. When the frame synchronization signal FS cannot be detected, the synchronization interpolation pulse is output instead of the synchronization detection pulse at the timing synchronized with the prediction detection timing,
This process is repeated until the frame synchronization signal FS can be actually detected.

In this way, when the frame sync detection is performed by the search mode prediction function FC1, the next step is the frame sync signal FS.
Using the synchronization mode prediction function FC2, which is the optimum prediction function for, shifts to the synchronization mode for detecting the frame synchronization signal FS.

In this synchronization mode, the synchronization mode prediction function FC2 outputs a synchronization detection pulse when the frame synchronization signal FS is detected, and when the frame synchronization signal FS cannot be detected, at the timing synchronized with the prediction detection timing,
A synchronous interpolation pulse is output instead of the synchronous detection pulse, and the above processing is repeated until the data reading of the sector is completed.

As the search mode prediction function FC1, for example, there is one that becomes “1111111111111111111” as shown in FIG. 3, and in this search mode prediction function FC1, in the state where no bit error occurs, the search mode prediction function FC1 is 8 The frame sync signal FS can be detected even if there is a bit shift. In addition,
If there is a bit error, the frame sync signal FS is not detected. That is, there is no possibility of false detection.

In addition, the synchronization mode prediction function (that is, the optimum prediction function) FC2 in this case is “112232211” as shown in FIG.
With such a synchronization mode prediction function FC2, the frame synchronization signal FS can be detected even when there is a 4-bit shift from the predicted position in the state where no bit error has occurred, and when the predicted position has the frame synchronous signal FS, The frame synchronization signal FS can be detected even if a 2-bit bit error occurs.

As described above, in the first part of the preamble PA, since the frame synchronization signal FS is detected by using the search mode prediction function FC1 having a very wide detection window width, the frame synchronization signal FS is detected in the state where no bit error occurs. Detection of is realized at an early stage. Further, after the frame synchronization signal FS is once detected, the frame synchronization signal FS is detected by using the synchronization mode prediction function FC2 which is an optimum prediction function that is resistant to errors, so that the frame synchronization can be surely detected.

FIG. 5 shows an apparatus according to one embodiment of the present invention.

In the figure, the read data DT separated from the read signal from the optical disc by the data separation circuit (not shown) is added to the data input terminal of the serial / parallel converter 1, and the read signal DT is also read from the read signal by the data separation circuit. The separated clock pulse CP is applied to the clock input terminals of the serial / parallel converter 1 and the counter 2.

The serial / parallel converter 1 converts the input data DT into 12-bit parallel data PD12 having the same length as the frame synchronization signal FS, and outputs this parallel data PD12 to a ROM (read only memory) 3. .

ROM3 is a 12-bit data pattern and frame sync signal
The data BN representing the number of bits in which FS coincides is stored, and the data BN corresponding to the input parallel data PD12 is output to the addition point 4.

In this way, the serial / parallel converter 1 and the ROM 3 compare the pattern of the data DT having a predetermined number of consecutive bits with the pattern of the frame synchronization signal FS, and output the data corresponding to the number of matching bits. Is configured.

The count value CDF of the counter 2 is the search mode prediction function FC1, the synchronization mode prediction function FC2, and the synchronization interpolation pulse PI.
F is added to the ROM5 which is generated at a predetermined timing of one frame period, and the search mode prediction function FC1 (2 bit width) output from this ROM5 is applied to the input terminals 1A and 2A of the selector 6 to predict the synchronous mode. The function FC2 is applied to the input terminals 1B and 2B of the selector 6, and the synchronous interpolation pulse PIF is applied to the input terminals 3A and 3B of the selector 6, respectively.

In this way, the ROM 5 of the counter 2 constitutes a prediction function generator that generates the prediction function and the synchronous interpolation pulse for each frame in synchronization with the input of the data DT.

The selector 6 selects the input terminals 1B, 2B, 3B when the select input terminal S is at the logic level L, selects the input terminals 1A, 2A, 3A when the select input terminal S is at the logic level H, and When the signal applied to the strobe input terminal ST is at the logic level L, the respective signals are output from the output terminals 1Y, 2Y, 3Y, and when the signal applied to the strobe input terminal ST is at the logic level H, the output terminals 1Y, 2Y, 3Y are output. The signal output from is prohibited.

The search mode prediction function FC1 and the synchronization mode prediction function FC2 output from the output terminals 1Y and 2Y of the selector 6 are added to the other input terminal of the addition point 4 and the synchronous interpolation pulse output from the output terminal 3Y. The PIF is added to one input terminal of the OR circuit 7.

The addition point 4 adds the data BN added from the ROM 5 and the value of the search mode prediction function FC1 or the synchronization mode prediction function FC2 added from the selector 6, and outputs the addition result to the synchronization detection circuit 8.

The synchronization detection circuit 8 outputs the output signal of the addition point 4 to a threshold value obtained by adding 1 to the length of the frame synchronization signal FS, that is, in this case.
Compared with 13, if the addition result is 13 or more, it is determined that the frame synchronization signal FS is detected and a synchronization detection pulse PSD is generated,
The sync detection pulse PSD is applied to the clock input terminals of the 9-bit delay circuit 9 and the flip-flop 10.

The output pulse PD1 of the delay circuit 9 is a 3-bit delay circuit 11
And the other input terminal of the OR circuit 7, the output pulse PD2 of the delay circuit 11 is applied to the clock input terminal of the flip-flop 12, and the one input terminal of the AND circuit 14 via the inverter 13. Has been added to.

The output of the flip-flop 10 is applied to the strobe signal SST and the output of the flip-flop 12 is applied to the strobe input terminal ST and the select input terminal S of the selector 6, respectively, and the output signal of the OR circuit 7 is The frame synchronization detection signal PFD is output to the signal demodulator of the next stage and the like, and is also applied to one input terminal of the OR circuit 15.

A sector detection signal SD indicating that the target sector has been detected, which is output from the drive device of the optical disk device, is added to the other input terminal of the OR circuit 15, and the output of the OR circuit 15 is output from the counter 2. It is added to the clear input terminal.

In addition, the sector end signal EOS output from the signal demodulator
Is a signal which falls to the logic level L when the data of the last frame of the sector is completely demodulated, and is applied to the clear input terminal (negative logic) of the flip-flop 12 and the other input terminal of the AND circuit 14. There is.

With the above configuration, when the drive device of the optical disk device rotationally drives the optical disk and the sector address SA of the target sector is detected, the drive device
The sector detection signal SD is output at a predetermined timing. As a result, the counter 2 starts counting clock pulses CP from zero, so that the search mode prediction function FC1, the synchronization mode prediction function FC2, and the synchronization interpolation pulse PIF are output from the ROM 5 at a predetermined timing (see FIG. 6 ( a), (c),
(See (b)).

Further, at this time point, since both the flip-flops 10 and 12 are cleared, both the strobe signal SST and the select signal SS are at the logic level L (see FIGS. 6 (e) and 6 (f)). Thus, the selector 6 selects the input terminals 1A, 2A, 3A and outputs the search mode prediction function FC1 applied to the input terminals 1A, 2A to the addition point 4 (see FIG. 6 (f)).

Now, here is the first frame sync signal of the preamble PA
If FS cannot be detected as shown by the broken line portion A1 in FIG. 6 (g) due to a bit error or the like,
The synchronous interpolation pulse PIF output at the timing immediately after the output of the search mode prediction function FC1 is completed is the selector 6
Frame sync detection pulse PFD (see FIG. 6 (l)) via the output terminal 3Y (see FIG. 6 (k)) and the OR circuit 7.
Is output as.

Further, the frame synchronization detection pulse PFD is the OR circuit 15
Is added to the reset input terminal of the counter 2 via the, and the counter 2 is cleared to zero at the rising timing thereof, and the counting operation is repeated again from zero. by this,
The prediction function generating operation of the next cycle is executed.

Then, for example, when the second frame synchronization signal FS appears in the data DT as shown as A2 in FIG. 6 (g), the synchronization detection circuit 8 is input at the time when the last bit of this frame synchronization signal FS is input. The synchronous detection pulse PSD is output from the output terminal (see FIG. 6 (h)), which sets the flip-flop 10 to set the strobe signal SST to the logical level H and inhibits the signal output of the selector 6. At this point, the output of the search mode prediction function FC1 from the selector 6 to the addition point 4 is cut off.

When this synchronization detection pulse PSD is delayed by 9 bits by the delay circuit 9 and output as the pulse PD1, this pulse P
D1 is output as a frame synchronization detection pulse PFD via the OR circuit 7, which allows the counter 2 to operate in the same manner as described above.
Is cleared and the prediction function generating operation of the next cycle is executed.

Further, when the frame synchronization signal FS is detected in this way, the selector 6 is in the output prohibited state when the synchronization interpolation pulse PIF is output at the above-mentioned timing. PIF output is prohibited.

When the pulse PD1 is delayed by 3 bits by the delay circuit 11 and output as a pulse PD2 (see FIG. 6 (j)), this pulse PD2 is applied to the clock input terminal of the flip-flop 12 and at the same time the inverter 13 Is converted into a pulse of negative logic and applied to the clear input terminal of the flip-flop 10 via the AND circuit 14.

As a result, the flip-flop 10 is reset and the flip-flop 12 is set at the same time. As a result, the output prohibited state of the selector 6 is released, and thereafter, the selector 6 selects the input terminals 1B, 2B and 3B. Then input end 1
The synchronous mode prediction function FC2 added to B and 2B is output to the addition point 4.

In this way, once the frame synchronization signal FS is detected, thereafter, the frame synchronization detection mode is shifted from the search mode to the synchronization mode.

Also in this synchronous mode, almost the same detection operation as in the search mode described above is executed.

That is, in this synchronization mode, when the frame synchronization signal FS cannot be detected, as shown by the broken line portion A3 in FIG. 6 (g), the synchronization interpolation pulse PIF output at the above-described timing is the frame. It is output as the sync detection pulse PFD.

Further, when the frame synchronization signal FS is detected as indicated by A4 in FIG. 6 (g), the selector 6 is in the output disabled state for 12 bits from that point, so that the synchronization interpolation pulse is generated.
The PIF output is prohibited, and the pulse PD1 is output as the frame synchronization detection signal PFD 9 bits after the detection timing.

Then, every time the frame synchronization detection signal PFD is output, the prediction function generating operation is returned to the initial state and repeatedly executed.

After that, when the reading of the frame data for one sector is completed, the sector end signal EOS falls, the flip-flops 10 and 12 are cleared, and the initial state is restored.

By the way, in the embodiment described above, the frame synchronization signal
Synchronous interpolation pulse PI output when FS cannot be detected
Sync detection output when the frame sync signal FS is detected at the timing at which the frame sync detection pulse PFD is output based on F and at the predetermined timing, that is, at the center timing of the search mode prediction function FC1 and the sync mode prediction function FC2. Frame sync detection pulse P based on pulse PSD
In order to match the timing at which the FD is output, the sync detection pulse PSD is delayed by 9 bits and output as a frame sync detection pulse PFD.

This allows the frame sync detection pulse to be detected when the frame sync signal FS is actually detected and when it is not detected.
Since the PFD output timing is the same, when the frame sync signal FS cannot be detected continuously, the predicted position for frame sync detection (prediction timing) does not greatly deviate from the proper predicted position, and immediately after that state. Even if the frame sync signal FS is within the detection range of the prediction function
Can be captured.

In addition, since the prediction function generation operation is repeatedly executed from the initial state, that is, the frame start state by the output timing of the frame synchronization detection pulse PFD, when the frame synchronization signal FS is detected at a timing before the center of the prediction function. , The operation of generating the prediction function returns to the initial state at the timing when 9 bits have passed, and therefore the synchronous interpolation pulse PIF is not generated and output to the OR circuit 7.

On the other hand, when the frame synchronization signal FS is detected at a timing later than the center of the prediction function, the synchronization interpolation pulse PIF is generated before 9 bits have passed from that timing, so that the synchronization is also used in this case. Interpolation pulse PIF selector 6
Since it is not output from the flip-flop 10,
The selector 6 is set to the output prohibited state for 12 bits from the detection timing. In addition, this output disable state
The 12 bits are set to ensure that the synchronous interpolation pulse PIF can be masked.

Although the frame synchronization signal is composed of a 12-bit bit pattern in the above-described embodiment, this bit pattern is not limited to that described above. The contents of the search mode prediction function and the synchronization mode prediction function described above may be appropriately selected although they correspond to the contents of the frame synchronization signal. Further, the number of bits of the delay circuits 9 and 11 may be set accordingly.

[Effect] As described above, according to the present invention, the frame synchronization is first detected in the state where the detection window width is large, and when the synchronization detection is successful, thereafter, the frame synchronization is strictly performed in the state where the detection window width is small. Since the detection is performed, there is an advantage that the frame synchronization can be quickly achieved even when the rotation fluctuation between the preformatted area and the data area becomes large. Further, since the output timing of the frame synchronization detection signal by the interpolated signal and the output timing of the frame synchronization detection signal when the frame synchronization signal is detected at a predetermined timing are matched, the state in which the frame synchronization signal cannot be detected continues. Even in such a case, the frame synchronization signal that appears properly immediately after that can be surely detected, and therefore, the loss of synchronization after once detecting the frame synchronization can be prevented.

[Brief description of drawings]

FIG. 1 is a signal arrangement diagram showing an example of a data recording format according to the present invention, FIG. 2 is a flow chart for explaining the operation of the present invention, and FIG. 3 is a signal arrangement showing an example of a search mode prediction function. 4 and 5 are signal arrangement diagrams showing an example of the synchronization mode prediction function, FIG. 5 is a block diagram showing an embodiment of the present invention, and FIGS. 6 (a) to 6 (l) are shown in FIG. FIG. 7A is a waveform diagram for explaining the operation of the device shown in FIG. 7, FIG. 7A is a signal arrangement diagram showing an example of the recording format of the optical disc, and FIG. 7B is a signal showing an example of the recording format per sector. FIG. 1 ... serial / parallel converter, 2 ... counter, 3,
5 …… ROM (Read Only Memory), 4 …… Addition points,
6 ... Selector, 7,15 ... OR circuit, 8 ... Sync detection circuit, 9,11 ... Delay circuit, 10,12 ... Flip-flop, 1
3 ... Inverter, 14 ... AND circuit.

Claims (1)

[Claims] 1. A recording format in which a plurality of data frames separated by a frame sync signal having a pattern of a preamble and a sharp autocorrelation for arranging a circuit condition are arranged following a preformatted area indicating the beginning of a sector. In a frame synchronization detecting device for detecting a frame synchronization signal from data recorded on a recording medium, a maximum detection window prediction function having a maximum detection window width for detecting the frame synchronization signal and an optimum prediction function corresponding to the frame synchronization signal. And a prediction function generating means for generating an interpolation flag signal corresponding to the detection prediction timing of the frame synchronization signal, and one of the maximum detection window prediction function and the optimum prediction function. Selecting means, and the matching state of the data read from the recording medium and the frame synchronization signal. Of the frame synchronization detection discriminating means for discriminating the detection state of the frame synchronization signal on the basis of the output signal of the selecting means and the output signal of the matching filter means. The first delay means for delaying the output by the first delay bit number, the second delay means for delaying the output of the first delay means by the second delay bit number, and the frame synchronization detection determining means. A first flip-flop set at the output and reset by the output of the second delay means; and a second flip-flop set at the output of the second delay means. The output signal and the interpolation flag signal are output as a frame detection signal, and the signal output of the selecting means is prohibited by the output of the first flip-flop. , The frame synchronization detector for causing selected the optimum prediction function to the selection means by the output of said second flip-flop.