JPS626467A - Data recording and reproducing system - Google Patents

Abstract

PURPOSE:To discriminate a sector surely and to read out data even if a data error is generated in a preformat area by discriminating the sector from a sector address recorded in a preamble at the reading of data. CONSTITUTION:Since a frame synchronizing signal FS1, number information FNn for discriminating the frame synchronizing signal and plural sector addresses SA for discriminating sectors are recorded in a preamble PA1 of a data area part FFD1, and at the reading of data, a sector concerned is discriminated from the sector addresses SA recorded in the preamble PA1, the sector can be surely discriminated and data can be read out even if a data error is generated in the preformat area. Since the bit rate of the preamble is set up to one over an integer of the bit rate of a data recording area to record data, the preamble can be surely discriminated from the data recording area in the data area part.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field] The present invention relates to a frame synchronization detection device that can reliably detect frame synchronization in a recording device having a data recording format in which data is recorded in a frame structure.

[Prior Art] Devices using magnetic recording media such as magnetic tapes and magnetic disks are widely used as auxiliary storage devices in computer systems. There have been proposals to use optical recording media (for example, optical discs) that can be used as auxiliary storage devices.

For example, in the case of optical discs, by means of a laser spot.

Data is recorded by forming bits (small holes) with a diameter of about 1 μm on the recording track on the surface at a period (interval) of about 2 μm, and the storage capacity is 1011 to 100 per disk with a diameter of about 30 cm. It is about 1o L 2 bits.

Now, since the access speed of auxiliary storage devices is generally much slower than that of main storage devices, data is recorded in blocks of a certain amount in consecutive areas.

At that time, to ensure that data can be read and written in a short time, predetermined blocks of data are organized into sectors,
Each sector is identified by assigning an address (sector address).

FIGS. 11(a) and 11(b) show an example of a data recording format in transport of an optical disc.

In the same figure (a), the track TR includes a preformat area PF, a data area DF, and a gap GPI separating the preformat area PF and the data area DF.
A plurality of sectors SC are consecutively set apart from each other by a gap GP2.

Note that the preformat area PF is formed in advance on the track TH at an interval of the total number of bits from the data area D'' and the gap GP2.

In addition, as shown in FIG. 6(b), the preformat area PF contains a synchronization signal for matching circuit conditions, that is, a bit synchronization signal for synchronizing the bit clock of the data write/read circuit with the generation timing of recording data. It consists of a preamble consisting of BS, a sector synchronization signal SS consisting of a bit string (pattern) with a sharp autocorrelation for detecting this preformat area PF, and a sector address SA for identifying the sector SC.

As the bit synchronization signal BS forming the preamble, a PLL (P-hase) is used to extract the bit clock and data based on successive signals from the optical pickup unit.
For example, a signal that changes the state of the read signal with a minimum inversion cycle (i.e., a signal that changes the state of the read signal with a minimum reversal period (i.e., rololo, in which the state of recording on the optical disc is a repetition of the minimum pit length) is used.
l...'').

Further, the data area OF consists of a plurality of pieces of data to which a frame synchronization signal FS is attached and forms a frame, and a preamble (bit synchronization signal BS) attached to the beginning of these data. Note that the preamble in the data area OF requires a smaller number of bits than the preamble in the preformat area PF, and the frame synchronization signal FS is composed of sharp autocorrelated bangs similar to the sector synchronization signal SS.

Note that the preamble BS, sector synchronization signal SS, sector address SA, gap GPI, GP2) of the preformat area PF and the preamble BS and frame synchronization signal FS of the data area DF are recorded on the optical disc in an unmodulated state. , the frame data in the data area OF is recorded in a state where it has been subjected to predetermined modulation.

Now, when recording data in such a recording format, first, the preamble of the preformat area PF is used to record the first pitch.
After synchronization, the sector synchronization signal ss is detected, and the sector address SA is read out based on the detection timing.

If it rains the desired sector, the gap GPI
After writing the preamble of the data area DF, the frame data of the first frame is sent to the frame synchronization signal FS.
Then, the frame synchronization signal FS and frame data of each frame are sequentially recorded.

When reading data, read the sector address SA in the same way as described above, and if it indicates the desired sector, resynchronize the bits with the preamble of the data area, and then use the timing when the frame synchronization signal FS is detected. Read frame data for each frame.

And this read frame data.

The data is converted into the original data before modulation by predetermined demodulation processing.

In this way, data is recorded and read by referring to the pre-format area recorded in advance.

Incidentally, although optical disks have a significantly high recording density as described above, they are considered to be quite susceptible to bit error rates, rotational fluctuations of the drive system, and the like.

On the other hand, since a systematic error correction code is usually added to each frame data before modulation, even if a data error occurs, it can be completely recovered to a certain extent and there is no major problem.

However, if a data error occurs in the preformat area after data recording and the sector synchronization signal FS cannot be detected, the sector cannot be accessed and the recorded data cannot be read. was occurring.

Note that in order to improve the reliability of detecting the sector synchronization signal SA, it is possible to record the sector synchronization signal FS and sector address SA multiple times in the preformat area, but this will further reduce the data recording area. This gives rise to the problem of becoming.

[Purpose] The present invention has been made in order to solve the above-mentioned disadvantages of the prior art, and provides a data recorder that can reliably identify sectors and read data even if a data error occurs in a preformatted area. [Structure] In order to achieve this object, the present invention provides a frame synchronization signal, number information for identifying the frame synchronization signal, and a sector address for identifying the sector. A plurality of sectors are recorded in the preamble of the data area, and when reading data, the sector is identified from the sector address recorded in the preamble. Furthermore, since the preamble and the data recording area are recorded at different bit rates, it is possible to reliably identify the preamble and the data recording area in the data area.

Embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

FIGS. 1(a) and 1(b) show a preamble PAL of a data area OF and a frame data area FFD 1 according to an embodiment of the present invention. It should be noted that, as a matter of course, immediately before the preamble PAL, the message shown in Fig. 11(a)
A preformat area PF similar to PF is recorded on the optical disc in advance.

This preamble PAL is a bit synchronization signal BS of a predetermined length for matching the circuit conditions of the reading means, such as a pattern with sharp autocorrelation (for example,
A frame synchronization signal FS consisting of a bit string of
I, sector address SA (
(same as that recorded in the preformat area PF) and a frame number FNn for identifying the frame synchronization signal FSI in this preamble PAL.
(value is n) is made up of (n+1) devices.

Further, the frame data area FFDI has a pattern with a sharp autocorrelation different from the frame synchronization signal FSI (for example, ro
OOOLLLOOLLJ) and a plurality of frame data FDD of a predetermined length are arranged.

The data area DF including the preamble FAI is generated according to the format by the signal generator shown in FIG.

In the same figure, a bit synchronization signal generation circuit 1 is for generating a bit synchronization signal BS of a preamble PAL, and its output is applied to an input terminal A of a multiplexer 2, and a frame synchronization signal generation circuit 3 is for generating a bit synchronization signal BS of a preamble PAL.
The output of the frame synchronization signal FSI is applied to the input terminal B of the multiplexer 2.

The sector address generation circuit 4 generates a sector address corresponding to the sector address data DDS applied in advance from the optical disk drive device (path shown), and its output is applied to the input terminal C of the multiplexer 2. , frame number generation circuit 5 is preamble PA
Frame number FN of L (FN.

-FNo), and its output is applied to the input end of multiplexer 2.

Further, the frame synchronization signal generation circuit 6 generates a frame synchronization signal FS2 for the frame data area FFD1, the output of which is applied to the input terminal E of the multiplexer 2, and the modulation circuit 7 generates a frame synchronization signal FS2 for the frame data area FFD1. It modulates the recorded data DT using a predetermined modulation method,
Its output is applied to the input F of multiplexer 2.

The clock generator 8 generates a clock signal CPI having a frequency fcl for recording the frame data area FFD 1, and this clock signal CPI is applied to the frame synchronization signal generation circuit 6 and the modulation circuit 7. It is added to the frequency divider 9.

The frequency divider 9 divides the clock signal CPI by 1/n (n is an integer) to form a clock signal CP2 having a frequency fc2. They are added to a synchronization signal generation circuit 3, a sector address generation circuit 4, and a frame number generation circuit 5, respectively. Further, the frequency division ratio n in this frequency divider 9 is set to 2, for example, so that
The bit rate for recording the preamble FAI is 172 times the bit rate for recording the frame data area FFDI.
become.

Further, the format control circuit 1o sequentially drives each of the above-mentioned elements to form the data area FD according to its format.

With the above configuration, when the sector detection signal SD indicating that the target sector has been detected is applied from the optical disc drive device, the format control circuit 10 first selects the input terminal A of the multiplexer 2, and then selects the bit The synchronization signal generating circuit 1 is operated once to generate a bit synchronization signal BS.

Subsequently, the frame synchronization signal generation circuit 3, the sector address generation circuit 4, and the frame number generation circuit 5 are repeatedly activated to reduce the value of the frame number FN from n by 1 until it becomes 0, and the elements for the activation are The multiplexer 2 sequentially selects input terminals B, C, and D corresponding to the input terminals B, C, and D, and outputs them to the next stage recording section (path shown).

When the preamble PAL is completed in this way, the format control circuit 10 operates the frame synchronization signal generation circuit 6, and then operates the modulation circuit 7 to input and modulate the recording data DT for one frame. At the same time, input terminals E and F are selected by the multiplexer 2 and outputted to the recording section, and this is repeated for each frame to complete data recording in one sector.

Note that the frame synchronization signals FSI, FS2) sector address SA and frame number FN are signals of bit strings that have been modulated by a predetermined modulation method or satisfy the modulation rules.

FIG. 3 shows an example of a reading section that reads the above-mentioned preamble PAI and frame data area FFDI.

In the figure, a readout signal SR output from a signal readout section (shown in the figure) consisting of an optical pickup, etc. is filtered by a low-pass filter 21 whose cutoff frequency is set to fc2 corresponding to the signal frequency of the preamble PAL. are applied to the low-pass filter 22 set to fcl corresponding to the signal frequency of the frame data area FFDI, and the outputs of these low-pass filters 21 and 22 are.

The signals are applied to input terminals A and B of a multiplexer 23, respectively, and the output of this multiplexer 23 is applied to a bit synchronization circuit 24 composed of a PLL circuit, a data separator, and the like.

The bit synchronization circuit 23 has the faster frequency fcl of the bit rates of the preamble PAL and the frame data area FFD l set as its operating frequency, and its PLL circuit is locked by the bit synchronization signal BS in the preamble PAL, and this The preamble PAL and the read data RD corresponding to the recording data in the frame data area FFDI are separated.

The read data RD is processed by a frame synchronization detection circuit 25 that detects a frame synchronization signal FSI, a sector address detection circuit 26 that detects a sector address SA. and a frame number detection circuit 27 for detecting the frame number FN, a frame synchronization detection circuit 28 for detecting the frame synchronization signal FS2, and a demodulation circuit 29, respectively.

The frame synchronization detection circuit 25 determines the frame synchronization signal FS1 from the input read data RD, and generates a frame detection signal FDDI corresponding to the timing at which this frame synchronization signal FSI is detected. It is added to the address detection circuit 26.

The sector address detection circuit 26 receives a frame detection signal FD.
The sector address SA is determined from the input read data ItD based on the timing of receiving Dl, and the sector address SA is added in advance from the optical disk drive device (path shown) to the target sector address. If it does not match SSA, the sector address SA determined at that time is output to the optical disk drive device as the detected sector address DSA.

Thereby, the optical disk drive device executes access control to the target sector by referring to this detected sector address DSA. Furthermore, if the determined sector address SA matches the target sector address SSA, a sector detection signal DO3 is output to the frame number detection circuit 27.

The frame number detection circuit 27 receives a frame detection signal FDD.
Based on the reception timing of I, determine the frame number FN from the input read data RD, and if the value is 0.
When frame number FNo is detected, multiplexer 2
3 and the preamble end signal EOP output to the frame synchronization detection circuit 28 is raised to logic level 11. Furthermore, the preamble end signal EOP remains at logic level II until reading of one sector is completed.

The frame synchronization detection circuit 28 determines the frame synchronization signal FS2 from the input read data RD while the applied preamble end signal EOP is at logic level 11, and detects the frame synchronization signal FS2 at the timing when this frame synchronization signal FS2 is detected. Correspondingly, a frame detection signal FDD2 is generated. This frame detection signal FDD2 is transmitted to the demodulation circuit 2.
9 as well as the frame synchronization detection signal DFD.
The signal is output to the next stage circuit such as an error correction circuit (the path shown).

The demodulation circuit 29 determines the recording data for one frame from the input read data RD based on the reception timing of the frame detection signal FDD2, and converts it into the original data DA.
The data DAT is demodulated to T and outputted to the next stage circuit.

Therefore, first, when the preamble PAL is input, the preamble end signal EOP output from the frame number detection circuit 27 is at the logic level L, so the multiplexer 23
Low-pass filter 21 that separates frequencies corresponding to AL
The output of is selected and output to the bit synchronization circuit 24.

As a result, when the frame synchronization signal FSI in the preamble PAL is detected and the frame detection signal FDDI is output from the frame synchronization detection circuit 25, the sector address SA is determined by the sector address detection circuit 26 in synchronization with this timing. If the determined sector is the target sector, the frame number FN is sequentially detected by the frame number detection circuit 27 in synchronization with the generation timing of the sector detection signal DO3 outputted from the sector detection circuit 26.

Its value is determined.

Then, the frame number detection circuit 27 detects the frame number FN.
When detecting o and determining that the preamble PAL has ended, the preamble end signal EOP is raised.

As a result, the multiplexer 23 selects the output of the low-pass filter 22 that separates the frequency corresponding to the frame data area FFDI and outputs it to the bit synchronization circuit 24, and the frame synchronization detection circuit 28 starts operating.

As a result, the frame synchronization detection circuit 28 detects the frame synchronization signal FFD1 in the subsequent frame data area FFD1.
When S2 is detected and a frame detection signal FDD2 is output, data DAT for one frame is output from the demodulation circuit 29 in synchronization with the generation timing of this frame synchronization signal FFD2.

Note that the determination of the sector address SA by the sector address detection circuit 26 is based on so-called majority logic, etc., which determines the sector address SA that appears most frequently among the plurality of sector addresses SA recorded in the preamble PAL as the sector address SA of that sector. can be used.

Now, the above-mentioned bit synchronization circuit 24 has its operating frequency set to the frequency fc1 corresponding to the bit rate of the frame data area FFDI, and can not only separate the recording data of this frame data area FFDI, but also use the frequency fcl The bit synchronization circuit 24 is configured so that it can also separate the recorded data of the preamble PAI having a frequency fc2 of 1/n (1/2 in this case) of .

FIG. 4 shows an example of the bit synchronization circuit 24. This bit synchronization circuit 24 detects the rising and falling edges of input data and forms a reference pulse with the same waveform as the PLL clock so that the PLL circuit can be locked with the preamble FAI data having a small bit rate. At the same time, a comparison pulse for phase comparison is independently formed. As a result, 1 of the frequency fcl
/n frequency fc2 bit synchronization signal BS
The circuit is properly locked. Basically, when recording data on an optical disk, the repetition frequency of the minimum pit length is twice the bit rate frequency due to the modulation rules, so the period of the input data is at least as long as the PLL clock. It becomes larger than twice the period.

In the same figure, the input data IND (see FIG. 5(a)) applied from the multiplexer 23 detects its rising edge and falling edge and generates an edge detection pulse FDP (see FIG. 5(b)). Output edge detection circuit 31 and PLL clock PCL (Fig. 5(e)
The edge detection pulse EDP is added to the data sampling circuit 32 which holds the level state at the rising timing of the reference pulse generator 33 (see below) and outputs it as read data RD. is added to the set input terminal of the device 34.

The reference pulse generator 33 generates a PLL clock PC in synchronization with the rising timing of the edge detection pulse EDP.
A reference pulse TP having the same waveform as L (see FIG. 5(c)) is generated, and the reference pulse TP is output to the reference phase input terminal of the phase comparator 35. Further, the reset input terminal of the comparison pulse generator 34 is connected to the PLL clock P.
CL is applied, and the comparison pulse generator 34 generates a rising edge of the reference pulse TP at the rising edge of the reference pulse TP.
A comparison pulse HP (see FIG. 5(d)) which falls at the falling edge of the LL clock PCL is formed, and the comparison pulse HP is applied to the comparison phase input terminal of the phase comparator 34.

The phase comparator 35 detects the phase error between the input data IND and the PLL clock PCL from the timing of the falling edge of the reference pulse TP and the falling edge of the comparison pulse HP. In this case, set the up/down signal LID output to the up/down counter 36 to logic level H, and set the reference pulse T.
If P falls later, the up/down signal UD is set to logic level L.

The up/down counter 36 counts up the clock signal applied from the oscillator 37 when the up/down signal UD is at logic level H.

When the up/down signal UD is at logic level L, the clock signal MCK is counted down. and.

When counting up, a carry signal CY is output every time the count value reaches a preset K, and when counting down, the count value is preset to K and a borrow signal BR is output every time the count value reaches 0. Output.

These carry signal CY and borrow signal BR are applied to the increment input terminal INC and decrement input terminal DEC of the incrementer-decrementer 38, respectively.

The incrementer-decrementer 38 generates a clock signal CCK (see FIG. 6(a)) which is obtained by dividing the clock signal MCK (see FIG. 6(a)) from the 5 oscillator 37 into 172.
d)) as well as a carry signal CY (see 6th
(see figure (b)), the timing of the clock signal CCK is changed to 17 at a predetermined timing from the falling edge of the clock signal CCK.
When the borrow signal BR (see FIG. 6(c)) is advanced by two cycles (that is, a pulse is added: part A in FIG. 6(d)) and the borrow signal BR (see FIG. 6(c)) is added, the timing of the clock signal CCK is set at a predetermined timing from the falling edge of the borrow signal BR (see FIG. 6(c)). is sent for 172 cycles (that is, the pulse is removed; part 8 of FIG. 6(d)).

This tarokk signal CC is added to the 1 frequency divider 39 and 1
/N and output as the PLL clock PCL. Note that the PLL clock P output from this frequency divider 39
Since the frequency of CL is equal to the bit rate frequency fcl of the frame data area FFD 1, the frequency of the clock signal MCK output from the oscillator 37 is set to 2N times fcl.

In this way, input data IND and PLL clock P
The edge detection circuit 31
, reference pulse generator 33, comparison pulse generator 34, phase comparator 35. up/down counter 36, oscillator 37,
Incrementor decrementer 38. The PLL circuit consisting of the frequency divider 39 is activated, and the PLL circuit is applied to the input data IND.
Clock PCL is locked.

As a result, the input data IND is properly sampled by the data sample circuit 32, and the read data RD is
is output. Further, the PLL clock PCL is outputted to a reading section or the like as a bit clock.

Also, the data of preamble PAL is input data IND.
7(a) to (f), the phase comparator 35 outputs an up/down signal UD corresponding to the phase difference between the input data IND and the PLL clock PCL. , As a result, the PLL circuit operates so that the PLL clock PCL is synchronized with the input data IND.

Now, in the embodiment described above, the preamble PAL
The frame synchronization signal FSI located in the frame data area FFDI and the frame synchronization signal FS2 located in the frame data area FFDI
The pattern of the preamble PAL and frame data area FFDI has been changed so that the preamble PAL and frame data area FFDI can be clearly identified.
Since the bit rate of data recording in 1 is changed, even if the frame synchronization signals placed in the preamble and frame data area have the same pattern, there will be no problem such as confusion between the preamble and frame data area.

Therefore, next, in the preamble and frame data area,
Another embodiment of the present invention in which frame synchronization signals of the same pattern are arranged will be described.

FIGS. 8(a) and 8(b-) show a preamble PA2 and a frame data area F according to another embodiment of the present invention.
FD2 is shown.

As shown in the figure, the frame synchronization signal FSI arranged in the frame data area FFD2 has the same pattern as the frame synchronization signal FSI arranged in the preamble PA2.

Such preamble PA2 and frame data area F
FD2 is generated by a signal generator as shown in FIG. In this figure, the same parts and corresponding parts as in FIG. 2 are given the same reference numerals, and the explanation thereof will be omitted.

In the figure, input terminals A, B, and C of a multiplexer 2.

The bit synchronization signal generation port JIt1, the sector address generation circuit 4, the frame number generation circuit 5, the outputs of the frame synchronization signal generation circuit 3 and the modulation circuit 7 are added to D, D, and E, respectively. A multiplexer 11 applies either the clock signal CPI output from the clock generator 6 or the clock signal CP2 output from the frequency divider 9 to the synchronization signal generation circuit 3 .

Therefore, when generating the preamble PA2, the format control circuit 10 selects the clock signal CP2 applied to the input terminal A in the multiplexer 12, and selects the bit synchronization signal generation circuit 1, the frame synchronization signal generation circuit 3, the sector The address generation circuit 4 and the frame number generation circuit 5 are sequentially operated in the same manner as described above, and
Input terminals A and D are input to the multiplexer 2 in synchronization with the activation timing of each element.

B and C are selected in sequence.

Next, when generating the frame data area FFD2.

The format control circuit 11 causes the multiplexer 11 to select the clock signal CPI applied to the input terminal B, and the frame synchronization signal generation circuit 3 and the modulation circuit 7.
are activated sequentially in the same manner as described above, and in synchronization with the activation timing of each element, the input terminals of the multiplexer 11 are used to sequentially select IEs.

As described above, in this embodiment, the frame synchronization signal generation circuit 3 is connected to the preamble PA2 and the frame data area FFD.
2, the configuration of the signal generator becomes simpler.

FIG. 10 shows a reading section that reads preamble PA2 and frame data area FFD2. In this figure, the same parts and corresponding parts as in FIG. 3 are given the same reference numerals, and the explanation thereof will be omitted.

In the figure, the read data RD output from the bit synchronization circuit 24 selects output terminal X when the preamble end signal EOP is at logic level I5, and selects output terminal Y when the preamble end signal EOP is at logic level 11. It is also added to the demultiplexer 41 that performs.

Therefore, the preamble end signal EOP is at the logic level /
In the case of L/L, the output signal of the low-pass filter 21 is selected by the multiplexer 23, so the output signal of the low-pass filter 2 is output from the output terminal X of the demultiplexer 41.
The read data RD corresponding to the preamble PA2 outputted by No. 1 is outputted and applied to the sector address detection circuit 26 and the frame number detection circuit 27.

Furthermore, when the preamble end signal EOP is at logic level H, the multiplexer 23 causes the low-pass filter 22 to
Since the output signal of demultiplexer 4 is selected,
The read data RD corresponding to the frame data area FDD2 output from the low-pass filter 22 is outputted from the output terminal Y of 1 and is applied to the demodulation circuit 29.

Further, the frame detection signal FDDI and the preamble end signal [EOP are applied to the AND circuit 42,
The output of this AND circuit 42 is the frame synchronization detection signal DF.
It is output as D to the next stage circuit.

In the above configuration, first, when the preamble PA2 is input, the preamble end signal IEOP is at the logic level, so the multiplexer 23
selects the output of the low-pass filter 21, and also selects the output of the sector address detection circuit 2 via the demultiplexer 41.
6 and frame number detection circuit 26.
Read data RD corresponding to 2 is output.

Therefore, similarly to the embodiment described above, the sector address detection circuit 26 detects the sector address SA in synchronization with the timing of the frame aspect ratio signal FDDI output from the frame synchronization detection circuit 25, and this detects the sector address SA, which is aligned with the target sector address SSA. If the sector address detection circuit 27 does not match the target sector address SSA, the detected sector address DSA is responded to the optical disk drive device from the sector address detection circuit 27, and if the detected sector address SA matches the target sector address SSA, it is synchronized with the detection timing. Then, the sector detection signal DO3 is output to the frame number detection circuit 27.

As a result, when the frame number detection circuit 27 detects the frame number and determines that the preamble PA2 has ended,
Preamble end signal EOP is raised to logic level H.

Therefore, from this point on, the output of the global filter 22 is selected by the multiplexer 23, and the read data RD corresponding to the frame data area FFD2 is
The signal is applied to the demodulation circuit 29 via the demultiplexer 41. Further, the AND circuit 42 becomes operable.

Therefore, the frame detection signal FDD1, which is output by the frame synchronization detection circuit 25 after detecting the frame synchronization signal FSI in the frame data area FFD2, is output to the next stage circuit via the AND circuit 42 as the frame synchronization detection signal DPI). At the same time, data DAT is output from the demodulation circuit 29 in accordance with this output timing.

In this way, in this embodiment, one frame synchronization detection circuit 25 detects the frame synchronization in the preamble PA2 and the frame data area FFD2, so the configuration of the reading section can be simplified by narrowing down to the embodiment described above. Become.

As described above, when reading data, the sector is determined based on the sector address SA recorded in the preamble PA, so there is no need to detect the sector address SA recorded in the preformat area.

Therefore, the data area can be accessed regardless of the error occurrence status in the preformat area.

Therefore, sector address 5A is stored in the preformat area.
There is no need to record a plurality of trs and take measures to increase the reliability of this portion, and as a result, the recording efficiency of the optical disc can be improved.

Also, the bit rate when recording the preamble,
Since the bit rate is changed when recording the frame data area, it prevents inconveniences such as when the frame data in the frame data area has the same pattern as the sector address and frame number, it will be mistakenly determined as a preamble. can do.

Furthermore, since the preamble bit rate is set to a negative integer of the frame data area bit rate,
The reliability of frame synchronization detection in the preamble is improved, and as a result, the number of frame synchronization signals, frame synchronization numbers, and sector addresses recorded in the preamble can be reduced, and therefore, the storage efficiency of the optical disc can be improved.

Naturally, it may become impossible to detect the sector address etc. due to an error occurring in the preamble, but in such a case, the frame data cannot be detected properly in any case. may be treated as a bad sector.

Furthermore, the arrangement order of the sector address and frame number in the preamble may be reversed. Furthermore, the frame numbers may be arranged in the order of FNo-FNn.

Furthermore, the configuration of the bit synchronization circuit used in the reading section is not limited to that shown in FIG. 4, and any circuit that performs the same function may be used. Example sentence lf, an analog PLL circuit can be applied.

[Effects] As described above, according to the present invention, a plurality of frame synchronization signals, number information for identifying the frame synchronization signals, and sector addresses for identifying sectors are recorded in the preamble of the data area. When reading data, the sector is identified from the sector address recorded in this preamble, so even if a data error occurs in the preformat area, the sector can be reliably identified and the data can be read.

Furthermore, since data is recorded with the bit rate of the preamble set to an integer of the bit rate of the data recording area, the preamble and the data recording area can be reliably identified in the data area.

[Brief explanation of the drawing]

FIG. 1(a) is a signal arrangement diagram showing a preamble according to an embodiment of the present invention, FIG. 1(b) is a signal arrangement diagram showing a frame data area according to an embodiment of the invention, and FIG. is a block diagram showing the signal generation @ position that generates the signals shown in FIGS. 1(a) and (b), and FIG. 3 is the same as that shown in FIG. 1(a).
Figure 4 is a block diagram showing an example of a bit synchronization circuit, and Figures 5 (a) to (f) are shown in Figure 4. Waveform diagrams for explaining the operation of the shown circuit, FIGS. 6(a) to (d)
) is a waveform diagram for explaining the operation of the circuit shown in FIG. 4, FIGS. 7(a) to (f) are waveform diagrams for explaining the operation of the circuit shown in FIG. 4, and FIG. (a) is a signal arrangement diagram showing a preamble according to another embodiment of the present invention;
b) is a signal arrangement diagram showing a frame data area according to another embodiment of the present invention, and FIG.
), FIG. 10 is a block diagram showing a signal generator for generating the signals shown in FIGS. 8(a) and 8(b), and FIG.
Figure (a) is a signal layout diagram showing an example of the recording format of an optical disc, and Figure (b) is a signal layout diagram showing an example of the sector format. 1... Bit synchronization signal generation circuit, 2, 11.23...
- Multiplexer, 3, 6... Frame synchronization signal generation circuit, 4... Sector address generation circuit, 5... Frame number generation circuit, 8... Clock generator, 9...
Modulation circuit, 21.22...Low pass filter, 24.
...Bit synchronization circuit, 25.28...Frame synchronization detection circuit, 26...Sector address detection circuit, 29...
- Demodulation circuit, 41... Demultiplexer, 42...
AND circuit. Figure 2 Figure 3 Figure 5 Figure '$7 Figure 9 Figure 70 ra 4 ζ-N-

Claims (2)

[Claims] (1) In a data recording and reproducing method in which a preformat area indicating the start of a sector is followed by a preamble for matching circuit conditions and multiple data frames separated by a frame synchronization signal with a sharp autocorrelation pattern. , the preamble is formed by arranging the frame synchronization signal, a plurality of number information for identifying the frame synchronization signal, and a plurality of sector addresses for identifying the sector, and the preamble is combined with the bit synchronization signal and the plurality of data. In addition to recording at a bit rate that is an integer fraction of the bit rate at which the frame is recorded,
A data recording and reproducing method characterized in that when reading data, a sector is identified from a sector address recorded in the preamble. (2) The data recording and reproducing method as set forth in claim 1, wherein the frame synchronization signal arranged in the data frame and the frame synchronization signal arranged in the preamble have different patterns.