JPS61292193A - Display unit - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a frame memory used for image processing and a display device thereof.

(Conventional technology) Frame memory, which has been common knowledge in television broadcasting technology, has been expensive due to its huge memory capacity.
It used to be limited to professional use, but due to the integration and cost reduction of semiconductors in recent years, it has become widely used in general. Some have even appeared that can be used also as frame memory.

An example of a display device that digitizes the above-mentioned externally input video signal, stores it in a video RAM, and displays it will be explained based on FIG.

FIG. 3 is a block diagram thereof. In the figure, numeral 1 denotes a video display control circuit which generates timing pulses for the entire system. 2 is an external synchronization circuit, which synchronizes with the horizontal and vertical synchronization signals of the input external video signal.
A video display control circuit generates a clock that is the basis for generating internal timing pulses. 3 is a color demodulation circuit for the input video signal, 4 is an analog-to-digital conversion circuit (hereinafter referred to as Ar converter), and 5 is a color bus interface, which connects whether or not to output the output of the AD converter 4 to the internal color bus. It is a control gate. 6' is a video RAM, 7 is a color palette and digital-to-analog conversion circuit (hereinafter abbreviated as DA converter),
This is the part that visualizes the color information output to the color bus.

The operation of the display device configured as described above will be explained. First, an external synchronization circuit 2 generates horizontal and vertical synchronization signals synchronized with the input video signal and a basic clock for display such as a dot clock. This is collectively referred to as an external synchronization timing signal 8, and serves as a reference timing signal for the video display control circuit 1. Methods for generating a signal synchronized with a video signal include methods such as a phase-locked loop (PT, L) and a gated oscillator. On the other hand, the brightness and color information in the input video signal is reproduced into three primary colors of RG and B by the color demodulation circuit 3, and
is converted into a digital signal at the pixel sampling rate and output to the external color bus 9.

First, the external video input is stored in the video RAM 6'. In this case, the external color bus 9 connects to the internal color bus 10 (and thus controls the color bus interface 5). As a result, the digitized video signal is directly connected to the data input/output terminal of the video RAM 6°. Since the horizontal/vertical refresh counter address 11 is supplied with an address matching the external synchronizing signal, by applying the write signal 12, digitized data is sequentially stored in the video RAM 6'. By repeating this for one frame, digitization of one screen of video signals is completed.

Conversely, in order to read the stored data, by controlling the color bus interface 5, the internal color bus 1
0 and external color bus 9, and video RAM 6'
This can be done by setting the read/write signal given to read mode.

Here, the color data 1 to DA converter 7 have the function of accessing the color palette according to the dot clock from the data on the color bus ``2'' and converting the output from DA to output, so that the video RAMB' Data on the color path can be displayed whether in write mode or read mode.

When the video display control circuit 1 instructs the digitization mode, the system of FIG.
Stop the AM read state and start inputting data from the color path. At this time, the color bus interface 5 drives the internal color bus 10. The input color data appears as it is at the RGB output terminal and is simultaneously stored in the video RAM 6' designated by address 11. By repeating this while the digitization mode continues and then returning to the display mode, input from the color path is inhibited.

Reference product: Yamaha MSX display LSI, part number/V
9938゜ (Problem to be solved by the invention) In the above configuration, the signal to be digitized -ζ- is in frame units, and a small area of a part of the already digitized image is divided into another It has the disadvantage that it is not possible to perform image editing such as replacing it with a video signal.

SUMMARY OF THE INVENTION An object of the present invention is to provide a display device that overcomes the drawbacks of the conventional art and allows easy editing of digitized images by superimposing screens by replacing part of the image with another image. .

(Means for Solving the Problems) A display device of the present invention is a display device having a function of digitizing an input video signal. A read/write control circuit controls the writing or reading of other video RAMs based on the data results output from the video RAM; It is equipped with a selection circuit for selecting one of them.

(Function) According to the configuration described in "-", the present invention provides video processing when a part of video RAM data in which one frame of an external video signal is digitized and stored is replaced with a newly input video signal. It can display the RAM status and actually replace some of its data.

(Example) An example of the present invention will be described based on FIGS. 1 and 2.

FIG. 1 is a block diagram of a display device of the present invention.

In this figure, the same parts as in FIG. 3 are given the same numbers, and the explanation thereof will be omitted. In Figure 1, 13 is the second
14 is a multiplexer, 15 is a color decoder, 16 is a color decode output signal, 17 is a video RAM select signal, and 18 is a read/write control circuit.

The capture of one frame of the external video signal is performed by the same operation as described in the conventional example. At this time, lead/
The write control circuit 18 operates to ignore the decode output signal 16, and the video dear press control circuit 1 operates to ignore the decode output signal 16.
The multiplexer 14 is switched so that the internal color path 10 and the data bus of the first video RAM 6 are directly connected.

The captured video RAM data is displayed by keeping the switching direction of the multiplexer 14 unchanged, turning off the color path interface 5, and setting the control signal to the first video RAM 6 in read mode.

Next, the second video RAM 13, which is provided to switch the output data of the first video RAM 6 pixel by pixel and has the same number of pixels as the first video RAM 6, will be explained. Second
The purpose of the video RAM 13 is only to generate a binary switching signal, and any minimum binary image is sufficient.This has a binary two-dimensional digital filter function and will be referred to as a template hereinafter. The multiplexer 14 switches the select signal 17 in order to write and read the template pattern into the second video RAM]3. 2nd video R
The data to be written to AM13 is output from the video display control circuit l, and is sequentially written to the second video RAM13. Since the written pattern is output on the color path 10, it passes through the color palette and DA converter 7 and becomes RGB output, so it can be confirmed visually, so it is possible to create any template pattern interactively with a human. I can do it.

The key point of the present invention is that the read/write control signal 18 of the first video RAM 6 is generated for each pixel using the above template data.
and to control the output of the color path interface 5.

The operation will be explained based on FIG. This figure is a timing chart showing a state in which the first video RAM data and the external color bus are switched by template output.

The multiplexer 14 is switched to the first video RAMB side, and digitized data of the external video signal is always output to the external color path 9. The color decoder 15 decodes the second video RAM data output for each pixel (dot clock), and if the color decode output signal 16 is 0゛, it will be ``°° switching request'', a
When the distance is 1 m, use normal read mode. When the color decoded output signal 16 is “°]°1, the first video R
AM6 data is read and displayed. These are A and B shown in FIG. At this time, the external color bus 9 is disconnected. Therefore, E and F in the figure are discarded. On the other hand, when the color decode output signal 16 becomes II O@, access to the first video RAM 6 is prohibited and the external color bus 9 is connected to the internal color bus 10. As a result, data C is not accessed in FIG. 2, and G is output to the internal color bus 10 and appears as display data. FIG. 2 shows how the first video RAM read/write control circuit 18 further generates a write signal at this time, and the data existing on the internal color path at that time, that is, G, is stored in the first video RAM 6. It shows.

Therefore, during the period in which the output data of the second video RAM 13 generates a color decoded output value of 0, the first video RAM 6 is in the write mode and is replaced with the input video signal. By repeating this for one frame, an image is created in which only the area where the template is ON is replaced with newly input video input data.

Although we have shown here that a write signal is always generated when the color decode output is O, it is also possible to make the first video RAM 6 not accessed during the same period, and in this case, the video RAM is updated. There is no display, only the replacement display.

(Effects of the Invention) According to the present invention, in a display device having a function of digitizing an input video signal, one or more video RAMs among a plurality of video RAMs accessed in synchronization with this video signal. A control circuit that controls writing or continuous output control signals for other video RAMs based on the content of data output from the 1000, and a data bus between the video RAM and the color palette and output control between the digitized data and the color palette. By providing a circuit to perform this, there is an effect that a part of an image can be replaced with another image and the screen can be edited.

[Brief explanation of drawings]

FIG. 1 is a block diagram of a display device according to an embodiment of the present invention, FIG. 2 is a timing chart thereof, and FIG. 3 is a block diagram of a conventional display device. ■...Video display control circuit, 2...
External synchronization circuit, 3... Color demodulation circuit, 4... Analog-digital conversion circuit, 5... Color path interface, 6... First video RAM, 7.
...Color palette and digital-to-analog conversion circuit, 8...External synchronization timing signal, 9...
External color pass, 10... Internal color pass, 11...
・Horizontal/vertical refresh counter address, 12...
Read/write signal, 13...Second video RAM, 1
4... Multiplexer, 15... Color decoder, 16... Color decode output signal, 17...
Video RAM select signal, 18... Read/write control circuit.

Claims (1)

[Claims] In a display device having a function of digitizing an input video signal, the video random access memory (hereinafter abbreviated as video RAM) that is accessed in synchronization with the video signal is output from one or more video RAMs. A read/write control circuit that controls writing or reading of other video RAMs based on the data results, and selecting either video RAM output or digitized output as input data to the color palette based on the data results. A display device comprising a selection circuit.