JPH02270488A - Digital picture signal processing unit - Google Patents

Abstract

PURPOSE:To facilitate the conversion among standard systems such as NTSC, PAL and SECAM by adding a simple addition circuit means to an IC for a digital picture signal processing and applying interleaving or interpolation of a scanning line for several lines. CONSTITUTION:A PAL system video signal as an input video signal is given from an input terminal 18 and in the case of the normal processing outputting a PAL system video signal from an output terminal 17, an additional circuit 9 outputs a control signal from a memory control IC. 3 to picture memories 1, 2 as it is without giving any change (additional circuit does not function). When the PAL system video signal inputted to the video signal input terminal 16 is outputted from a video output terminal 17 as the NTSC system video signal, the additional circuit 9 reads the PAL system video signal written in the picture memories 1, 2 and the content of an instruction code (IRi: IR1-IR5), a row address (RAi:RA1-RA5) and a column address (CAi:CA1-CA5) is replaced and the signal is read while one line is skipped for 8 lines.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a digital image signal processing device having a standard format conversion function.

[Conventional technology]

NTSC is the standard format for television signals.

Although there are systems such as PAL and SECAM, there is no known conventional technology for converting between these standard systems or from one system to another as a function of a VTR.

For example, “Nikkei Electronics J 1” published by Nikkei BP.
986.10.20. (no 406).

P195-214 As described in "Home VTR with built-in field memory to improve noise bars and skew distortion in search mode", the VTR has built-in field memory to perform skewless search.

Noiseless search, strobe effect (multi-screen).

There are some that allow special modes such as mosaic effects and solarization effects, but they are not equipped with standard conversion functions.

[Problem to be solved by the invention]

A VTR according to the above-mentioned conventional technology, for example, NTSC system V
TR"i'For example, if you try to record/play back a PAL or SECAM television signal (video signal),
A malfunction occurs and normal images cannot be obtained.

An object of the present invention is to provide a digital image signal processing device suitable for application to a VTR, etc., which can perform format conversion between a plurality of standard formats or from one standard format to another with a simple configuration. Our goal is to provide the following.

[Means to solve the problem]

The above object is to provide a VTR with a field memory or a frame memory (hereinafter referred to as an image memory means), and to thin out scanning lines in a memory control means that controls the image memory means.

Alternatively, this can be achieved by providing an additional circuit having a function of complementing the scanning line, and replacing the memory control data by manipulating a part of the control signal of the memory control means.

[Effect]

The memory control means is one for the image memory means.
Memory control data is sent every horizontal period to control writing/reading of video signals.

The additional circuit means controls updating of the write/read addresses of the image memory means by exchanging part of this control data.

This allows scanning lines to be thinned out at regular intervals.

Alternatively, perform interpolation to match the number of scanning lines of the conversion method.

〔Example〕

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram showing the configuration of an embodiment of a digital image signal processing apparatus according to the present invention, in which 100 is an image memory means, l is an image memory for luminance signals constituting the image memory means, and 2 is an image memory for image signals. An image memory for color signals constituting the memory means, 3 a memory control IC (memory control means), 4.5 an analog-to-digital converter (
6, 7.8 are digital-to-analog converters (hereinafter referred to as D/A), 9 is an additional circuit means (hereinafter referred to as A/D);
10 is a decoder, 11 is a band pass filter (BPF), 12 is a low pass filter (LPF), and 13 is a multiplexer (MPX).
, 14 is an encoder, 15 is a mixer, 16 is a video signal input terminal, and 17 is a video signal output terminal.

In such a configuration, first, a normal operation of processing a video signal of a certain system in various processing modes using an image memory and outputting it as a video signal of the same system will be described.

In the figure, a video signal input from a video input terminal 16 is applied to an LPF 12 and BPFII.

The LPF 12 separates and takes out the luminance signal Y from the input signal and supplies it to the A/D 4. Further, the BPFll separates and extracts the color signal C from the input signal and supplies it to the decoder 10.

The decoder 10 converts the color signal into a color difference signal (RY).

. This point sequential signal is A/D
5, it is converted into a digital signal and supplied to the image memory 2.

On the other hand, the output of the A/D 4 is supplied to the image memory 1.

The image memory 1.2 writes and reads out the input luminance signal 0 color signal under the control of the memory control IC 3.

The luminance signal read from the image memory 1 is converted into an analog signal Y by the D/A 6 and applied to the mixer 15.

On the other hand, the color signals read from the image memory 2 are analog color difference signals (R-Y) at D/AT, D/, and A8, respectively.
, (B-Y) and provided to the encoder 14. The encoder 14 outputs a color difference signal (R-Y) and a color difference signal (B
A color signal C is created from the color signal C from -Y) and is supplied to the mixer 15. The output of mixer 15 is output from video signal output terminal 17.

In this processing process, the memory control IC 3 performs signal processing corresponding to various modes that use the image memory 1.2, and performs signal processing corresponding to various modes that utilize the image memory 1.2, such as the above-mentioned skewless search, noiseless search, strobe effect (multi-screen), mosaic effect,
Performs memory control to execute special modes such as solarization effects.

That is, in the case of normal processing in which a PAL video signal is given as an input video signal from the input terminal 16 and a PAL video signal is output from the output terminal 17, the additional circuit 9 does not perform any processing on the control signal from the memory control IC 3. The image is output to the image memory 1.2 as is without any changes (the additional circuit does not function).

Next, a case of format conversion operation in which the format of the input video signal and the format of the output video signal are made different will be described.

In the case of this system conversion operation, the additional circuit 9 processes various control signals from the memory control IC 3 and supplies them to the image memories 1 and 2, thereby realizing the system conversion.

FIG. 2 is an explanatory diagram of the image memory control operation according to the present invention.

The figure shows instruction codes (IRi: IRI to IR5) output from the memory control IC3 in FIG.
Part of the timing of the signals, row address (RAi: RAI to RA5) signal, column address (CAi: CAI to CA5) signal, instruction strobe signal/column address strobe signal, row address strobe signal/instruction enable signal will be explained. It is a diagram.

As an example, if the video signal input to the video input terminal 16 in FIG. .2, write the NTSC video signal as is, and when reading, as shown in Figure 2, control signals of command strobe/column address strobe (IR3/CAS) and row address strobe/instruction enable (RAS/IRE) are used. control data IR
i, RA i, CA i are provided to the image memory.

That is, the instruction code (IRi: IRI to IR5) and the row address (RAi:
RAI to RA5), column address (CAi: CAL to CA
Replace the contents of 5). As a result, the video signal converted from the NTSC system to the PAL system is sent to the output terminal 17.
obtained from.

This enables conversion from the NTSC system to the PAL system.

Also, the PAL video signal input to the video signal input terminal 16 is converted into an NTSC video signal to the video output terminal 17.
When outputting from the image memory 1.2, the additional circuit 9
When reading the PAL video signal written in the
RAi:RAI~RA5), column address (CAi:CA
The contents of I to CA5) are replaced so that one line is skipped every six lines and read out.

This makes it possible to convert from the PAL system to the NTSC system.

According to this embodiment, a format conversion function can be provided as an additional function without changing an IC having a conventional digital image processing function.

The only components added to the image memory means are a timing generator for replacing control data, a replacement circuit, and a line number counting circuit, and the additional circuit can be configured with a small-scale circuit.

Furthermore, since a commercially available general-purpose IC can be used as the memory control IC, there is no need to develop a dedicated IC, and the functions of the present invention can be realized at a low cost.

FIG. 3 is a block diagram illustrating another embodiment of the present invention, in which the same reference numerals as in FIG. 1 correspond to the same parts.

The difference between this embodiment and the previous embodiment is that when the operation of the additional circuit 9 reads out the video signal from the image memory 1.2, the instruction code (IRr: rR1 to IR5) and the row address (
RAi:RA1-RA5), column address (CAt:C
Instead of replacing the data of AI to CA5), when writing the video signal to the image memory 13 and image memory 2,
By controlling the count enable signal of the row address counter of the memory write system using the additional circuit 9,
In particular, when converting from a PAL video signal to an NTSC video signal, writing is prohibited once every 6 lines, and N
The format conversion is performed by reading in TSC mode.

According to this embodiment, the circuit scale can be further reduced than the configuration of the previous embodiment.

FIG. 4 is a block diagram of the detailed configuration of the additional circuit means in the present invention, in which 18 is a multiplexer, 19 is a replacement data setting circuit, 20 is a replacement data selection circuit, and 2
1 is a pulse generation circuit, 22 is a counter, and the same reference numerals as in FIGS. 1 to 3 correspond to the same parts and the same signals.

In the figure, control data (II?1 to II?5) from the memory control IC is applied to a multiplexer 1B, and is replaced with a signal from a replacement data setting circuit 19, thereby performing replacement.

Here, in the data to be replaced (IRI to IR5), only the necessary bits selected in advance in the replacement data selection circuit 20 are replaced with data from the replacement data setting circuit (that is, among the data switches SW of the multiplexer 18 , only the data switches corresponding to the required bits work).

The pulse generation circuit 21 generates a clock signal, a horizontal synchronization signal (
I(D), instruction strobe signal (IRS/CAS)
, a column address strobe/write/read enable signal (RAS/IRE) and a counter 22 that divides 110 pulses by 176 to generate an instruction code replacement pulse.
A row address replacement pulse is generated and supplied to the replacement data selection circuit 20.

As described above, system conversion is realized by replacing part of the memory control data sent in the format shown in FIG. 2.

Here, the data that replaces the control data is a control that stops writing once every 6 lines during scan line thinning processing (PAL-NTSC conversion), or shifts the read line down by 1 line once every 6 lines. Processing to replace and send data and interpolate scanning lines (NTSC
-PAL conversion), the same data as the previous line is written once in every 6 lines, or the control data for reading the same line twice is replaced once every 6 lines and sent to the image memory.

FIG. 5 is a configuration diagram showing an example of a specific configuration of the additional circuit means according to the present invention, in which the same symbols as in FIGS. 1 to 4 correspond to the same parts, 23 is a flip-flop, 24 is a monomulti-byte It's a break. The memory control IC is, for example, M65011FP (manufactured by Mitsubishi Electric Corporation).
, the image memory uses M5MC500L. Also,
The counter 22 constituting the additional circuit is 74HC162,
? The /L/multiplexer 18 uses a 7411C157, and the pulse generating circuit 21 is composed of a monomulti-by-break 24 and a flip-flop 23. The replacement data setting circuit 19 and the replacement data selection circuit 20 are not particularly shown in FIG. 5, and are supported by wiring.

Further, FIG. 6 is a timing chart explaining the operation of FIG. 5, in which SOE is a serial data output permission signal of the image memory, RHD is a read horizontal synchronization signal, and IRS is a timing chart for explaining the operation of FIG.
/CAS is instruction strobe/row address strobe, I
R5/A5 is the instruction code 1 line address.

The 5th bit of column address data is shown.

In FIG. 5 and FIG. 6, IR5/A5 to IR7 of the control data from the memory control IC3 are shown here.
/A7 is replaced, and by replacing the data at the instruction code position shown in Figure 6, IR5/A5 is set to low level @L" once every 6 lines, and IR6/A6 is set to high level.
By setting IR7/A7 to low level "L", the signal of the 5th line is sent to the image memory 10 every 6 lines.
By reading twice from 0, the NTSC signal is converted to a PAL signal.

FIG. 7 is a block diagram showing the other side of the specific structure of the additional circuit means according to the present invention, in which 3 is a memory control IC;
2 is a counter (for example, 74HC162), and OK
E is a memory write-related row address count enable signal input, and is used to prevent the write address to be updated to the image memory 100 (not to be set to the value of the next line) if it is set to low level.

In this case, the counter 22, which is an additional circuit, sets the signal OKB to "L" every six lines of the input video signal, so that the write line is not updated.

WVD is a memory write system vertical synchronization signal and is used to reset the counter 22.

WHO is a horizontal synchronization signal for the memory write system, and is used for the frequency division operation of the counter 22.

Such a configuration enables format conversion between PAL and NTSC.

In the configuration of FIG. 7, the multiplexer 1 in FIG.
8 becomes unnecessary, and the scale of the additional circuit means can be reduced to further simplify the configuration.

FIG. 8 is a configuration diagram of a memory control IC which is a memory control means in the present invention, where ■ is an image memory, 3 is a memory control IC, and 25 is a write/read strobe signal and a write/read enable for the image memory 100. 26 is a write/read control circuit that generates a signal; 26 is an address control circuit that generates a write/read address for the image memory 100; 27 is a write/read control circuit 25;
28 is a timing generation circuit that generates timing pulses using a reference clock from a clock generation circuit 29, and 29 is a reference for the memory control IC. This is a clock generation circuit that generates a clock.

The memory control IC described above and the additional circuit means of the present invention are designed to provide write/read control signals (
IR5/CAS, RAS/IRE, etc.) and control data in the form shown in FIG. 2 are supplied to the image memory to realize still images, digital through images, picture-in-picture images, multi-strobe images, etc.

As mentioned above, the additional circuit for this memory control IC replaces the control data so that the output signal of the 6th line is read out twice the data of the 5th line when converting from NTSC to PAL, and also converts the output signal from PAL to NTSC. During conversion, the above control data is replaced to prohibit writing the input signal of the 6th line to the image memory when writing to or reading from the image memory, or to prohibit reading of the 6th line data written to the image memory. It works like this. This replacement mode is performed by setting the level of IR5/A5 at the falling edge of the IR3/CAS signal (instruction code position) in FIG. 6 to the "H level" or "L" level.

〔Effect of the invention〕

As explained above, according to the present invention, by adding a simple additional circuit means to an IC for digital image signal processing and performing scanning line thinning or interpolation every few lines, NTS
It can convert between standard systems such as C, PAL, and SECAM, and can be used as a general-purpose IC for digital image signal processing.
Since C is used and the scale of the additional circuit is small, it is possible to shorten the development period and provide a digital image signal processing device with excellent functions, such as realizing the required functions at a low price.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing the configuration of an embodiment of a digital image signal processing device according to the present invention, FIG. 2 is an explanatory diagram of an image memory control operation according to the present invention, and FIG. 3 is a block diagram showing another embodiment of the present invention. 4 is a block diagram showing a detailed configuration of the additional circuit means according to the present invention, FIG. 5 is a block diagram showing an example of a specific configuration of the additional circuit means according to the present invention,
FIG. 6 is a timing chart explaining the operation of FIG. 5, FIG. 7 is a block diagram showing the other side of the specific configuration of the additional circuit means according to the present invention, and FIG. 8 is a memory control means according to the present invention. FIG. 2 is a configuration diagram of a memory control IC. 1... Image memory for luminance signal, 2... Image memory for color signal, 3... Memory control IC, 4
, 5...Analog-to-digital converter (A/D),
6,7.8...Digital-to-analog converter (D/A
), 9...Additional circuit means, 10...Decoder, 11...Band pass filter (BPF), 12
...Low pass filter (LPF), 13...
Multiplexer (MPX), 14... Encoder, 15... Mixer, 16... Video signal input terminal, 17... Video signal output terminal. Figure 2 (RAi) (CAL) Figure 4 Figure 5 Figure 6 Figure 7 Figure 8

Claims (1)

[Claims] 1. A digital image comprising an analog-to-digital conversion means, an image memory means, a memory control means, and a digital-to-analog conversion means, which processes and outputs an input video signal via the image memory. In the signal processing device, an additional circuit means having a function of replacing the control signal given from the memory control means to the image memory means is provided, and the additional circuit means controls the predetermined scanning line of the video signal input/output to the image memory means. A digital image signal processing device that performs format conversion between different formats or from one format to another by thinning out or complementing predetermined scanning lines. 2. The digital image signal processing device according to claim 1, wherein the additional circuit means is provided in the memory control means, so that a system conversion function and another digital image signal processing function can be selected. 3. In claim 1 or 2, the additional circuit means is comprised of a control signal switching circuit composed of a counter and a gate circuit, and when converting from PAL system to NTSC system, the memory control means is connected every 6 lines. By controlling or replacing the memory control data, writing to the image memory means is prohibited, or updating of the write line address is stopped and scanning lines are thinned out, once every 5 lines when converting from the NTSC system to the PAL system. A digital image signal processing apparatus characterized in that scanning lines are interpolated by replacing memory control data given from the memory control means to the image memory means.