JPS5967587A - Color overlapped graphic generator - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION (1) Description of the field to which the invention pertains This invention relates to an apparatus for writing information into an image memory using a computer or the like and displaying a color image on a raster scanning display according to the contents of the image memory. (2) Description of conventional technology Figure 1 shows an example of a conventional optical display device, and 1 in the figure is a computer C.
PU, 2 is an image memory IM, 3 is a D/A converter, and 4 is a display CRT. Conventional devices of this type
As shown in the figure, the image memory 2 and the display 4 are directly connected using the D/A converter 3, and the color is displayed according to the value of each pixel in the image memory 2. When trying to display a color area, it is necessary to generate all pixels in the color area using a computer,
The disadvantages are that the burden on the computer increases, or that moving figures cannot be displayed due to the slow processing speed of the computer. Alternatively, as used in the present invention, information on only the boundary part of the color area is created by a computer and stored in a memory, and the stored information is read out in rask scanning order, and information on the boundary pixel from the boundary pixel of the color area to the next boundary pixel is read out in rask scanning order. Many methods have been used to reduce the burden on computers by filling the space between them with a certain color tone to display the color area as a solid figure, but the devices that have been announced so far can display There are disadvantages in terms of expression, such as limited areas such as trapezoids and triangles, inability to display areas with a width of one pixel, and inability to overlap areas.

(8) Object of the Invention In order to eliminate these drawbacks, the present invention stores information on the outline of a color area in an image memory, and at the same time as reading it, performs a filling process that is possible up to a width of at least 1 pixel and performs the color By controlling display priority between areas,
The present invention is a device configured to be able to display a color area of any shape in real time while reducing the burden on a computer.The device will be described in detail below with reference to the drawings.

(4) Explanation of the structure and operation of the invention FIG. 2 shows an example of the structure of the device of the invention, and 5 is a superimposed figure-less crushing circuit O.
FF, 6 is a look amplifier table LUT which converts the output pattern of the superimposed figure filling circuit 5 into a color tone, and 7 is a synchronizing signal generator CLK used to read out the contents of the image memory 2 and display them on the CRT 4.

Next, although the pixel depth of the 0 image memory 2 for explaining this operation is arbitrary, the following description will be made assuming an 8-bit depth. If the depth is 8 bits, 7 pits are used to store the area number of the color area (a priority number may be stored instead of the area number), and the remaining 01 bits are used to store the color area in the raster scanning direction. If so, is the pixel on the left side of the color area (a set code is given to the pixel), or is it on the right side or a pixel in a one-pixel wide color area (the pixel is given a set code)? give a reset sign)
(The set code and reset code are hereinafter collectively referred to as set and reset codes.)

The area number and the set/reset code are
1 and written to the boundary line portion of the color area in the image memory 2. The contents of the image memory 2 are read out in the rask scanning direction using a clock generated by a synchronizing signal generator 7, and sent to the superimposed figure filling circuit 5.

The superimposed figure filling circuit 5 uses the signal read out from the image memory 2 to determine which of the color areas is in a state to be displayed, and further determines which of the color areas in the state to be displayed has display priority. By generating the area number of the color area with the highest degree of color, an image is generated in which the color area is filled in from the image memory 2 in which only the boundary line portion is written, and the image is passed to the lookup table 6.

The lookup tape 6 converts the area number into color information, and further generates a color image on the display 4 through the D/A converter 3. Next, the circuit and operation of the superimposed figure filling circuit 50 will be explained in detail.

FIG. 3 is a circuit diagram of the superimposed figure filling circuit 50, in which reference numeral 8 denotes a distributor DST, 9, which divides the 8-bit input signal into a 1-bit set/reset code and a 7-bit area number.
P-LUTI of -1 and P-LUT2 of 9-2 are priority lookup tables, and P-LUTI converts display priority from area number to hail priority number, P-LUTI
LUT2 conversely performs conversion from the priority number to the area and number.

The P-LUTI is unnecessary when the data stored in the image memory 2 is not the area number but the priority number. Further, the P-LUT 2 is unnecessary when the input signal to the look amplifier table 60 is the priority number instead of the area number.

10 is a decoder DEC that develops a 7-bit signal into a 128-level 1-pit signal; 11 is a set-reset signal distributor S/R that divides the 1-bit set-reset code obtained from the distributor 8 into a set signal and a reset signal;
SHo of C,l 2,SH,1,.

...5H127 is a signal holder that holds or releases the signal at level 1 of 128 levels using the output of the decoder 10 and the set signal reset signal, and 13 is a signal holder that holds or releases the signal at level 1@ of 128 levels.
A number is assigned to the output of the signal holder 12 of fl, and the signal is
”, convert the highest number in the above output to binary 7.
This is a priority encoder PEC that outputs bits.

The operation will be explained below. Priority lookup table 9
-19-2 is composed of a RAM, in which data referenced by the CPU 1 is written, and the area number and priority number are converted. This is done to ensure consistency with other circuits since the signal holder 12 and priority encoder 13 operate based on the priority number.

An example of the operation of the decoder 10 will be shown below. In other words, a 7-bit binary input is r0OOIIIOJ (IO base 14).
When 128 level output S i-7 (0≦7≦12y
), the 14th 1-bit signal output 5g-14 is set to ``0''.
” to “1”. The output 5f-74 of the decoder IO is the corresponding 111i! of the 128 signal holders 12! il
(in this case, it is SH, 4), and the set signal is sent to
It is used in conjunction with a reset signal to operate the signal holder.

The set/reset signal distributor 11 has an input with a cent sign (
The set signal is sent to the signal holder 12 as "1" when the code is "l", and the reset signal is sent as rlJ when the code is a reset code (supposed to be "0").

The set/reset signal distributor 1'l is comprised of the circuit shown in FIG. 4, and performs the operations described above. In the figure, S represents the cent signal and r represents the reset signal.

The signal holder 12 is composed of a circuit shown in FIG. 5(α). In the figure, 14 is an SR flip-flop circuit.

As shown in the timing chart of FIG. 5(b), this operation centers the flip-flop 14 when Bit-i and S are rlJ, and resets the flip-flop 14 when By-; and γ are rlJ. . CLH4j
A line clear signal sent from the CPU1, for example rlJ during the horizontal retrace period of rask scanning, resets the flip-flops 14 in all signal holders. 5v again
-7 and r are 1, the flip-flop 14 is not only reset, but also ORed with the Q output of the flip-flop, and the result of the OR operation is set to 5O-7-, and the signal holder SH , 4.

Therefore, if the signal read from the image memory is the area number fi that is converted to the priority number I, the period from the time when "fJ and set code" is read to the time when [fI and reset code] is read and "fJ and reset code", the output 80-7 of one of the signal holders 5H7- is set to "1".

Therefore, when different area numbers and set codes are successively read out from the image memory 2, at a certain point the outputs (SO- a, 5o-b, 5o-J
becomes rlJ at the same time. This indicates that the respective areas are overlapping at that point in time, and the priority encoder 13 operates to find a priority number that can be converted to an area number with the highest display priority among these overlapping areas. be.

Figure 6 shows the terminal configuration of the priority encoder 13, and Figure 7 is a timing chart showing an example of its operation. In some cases, this may be reversed.

Next, the operation shown in FIG. 7 will be explained. The priority encoder 13 selects the 128f-specific A word 5o-7 (0≦I≦12
7), the signals that are "1" are compared and the maximum value of number J is output in binary 7 bits. In the figure, at time 1x, 8[]-127, S 0-125.5O-1,5O
-0 is rlJ and therefore 127 ('11111 in binary)
11”).The priority lookup table 90P-1, UT2 outputs the priority encoder 1.
The priority number obtained in step 3 is converted into an area number and output from the superimposed figure filling circuit 5.

FIGS. 8(a) and 8(b) are examples of the operation of the superimposed figure filling circuit 5, in which (a) is the input and (b) is the output. 15 in the diagram
is a pixel at the boundary of each color area, and the symbol B of the pixel is
/S (others in the figure are A/R, B/R, and C/S.

In C/R, B represents the area number of the color area, S represents the cent code (Similarly, AXC represents the area number, and R represents the reset code). Further, 16, 17, and 18 are color areas distinguished by area numbers A, B, and C, respectively. Here, each color area has a higher light display priority in the order of A, B, and C]~(
A>B>C) In the pixels where the valley color areas overlap, filling is performed so that the color area with a high display priority is displayed, and the pattern shown in FIG. 8(b) is obtained. The pattern is displayed on a display 4 in a desired color tone through a color lookup table 6 and a D/Ai converter 3.

(5) Description of Effects As explained above, in the apparatus of the present invention, the CPU performs generation processing only on pixels at the boundary of the color area to be displayed, and the other areas are filled in and overlaid by hardware. In order to process
Color images can be displayed while reducing the burden on U. In particular, by accurately assigning set/reset codes, it is possible to display any shape, and the ability is higher than that of conventional devices of this type. Furthermore, as the burden on the CPU has been reduced, it has become possible to create and display moving figures such as moving images using relatively inexpensive equipment, and terminal equipment that uses still image communication via narrowband transmission lines has become possible. It has the advantage that it can be used in fields such as, and facilitates the provision of videos.

[Brief explanation of drawings]

FIG. 1 is a block diagram of a conventional image light display device, FIG. 2 is a block diagram of an embodiment of the present invention, FIG. 3 is a block diagram of a superimposed figure filling circuit in the embodiment of FIG. 2, and FIG. Figures 8 through 8 are explanatory diagrams of detailed circuits and operations of the superimposed figure filling circuit. In the figures, 1 is a CPU, 2 is an image memory, 3 is a D/A converter, 4 is a display, and 5 is a superimposed figure Coloring circuit, 6
is a lookup table, 7 is a synchronization signal generator, 8 is a data distributor, 9-1 and 9-2 are priority lookup tables, 10 is a decoder, 11 is a set/reset signal distributor, 12 is a signal holder, 13 is a priority encoder, 14 is a flip-flop circuit, 15 is a color area boundary pixel, and 16, 17, and 18 are color areas A and B. Represents C. Patent Applicant Nippon Telegraph and Telephone Public Corporation Patent Attorney Mori 1) Hiroe PL/ CLK Ashi 3
m1 sai4@I5closedf6kan

Claims (1)

[Claims] (1) In a device for displaying a figure having a plurality of color regions with defined display priorities on a display,
An image memory for storing a display priority number of the color area and a set/reset code indicating a distinction between the left and right ends of the color area is provided at an address corresponding to the boundary line of the color area, and the image memory is arranged in a certain direction. a circuit for raster scanning and sequential reading, and decoding a display priority number from the read signal; and a circuit for holding or canceling the decoded signal according to the set/reset code signal to fill the color area in the direction of the raster scanning power. It is equipped with a circuit that outputs the maximum value of the display priority number among the held decoded signals and converts it into a turn signal, and a circuit that converts the obtained turn signal into a color signal and displays it on the display. A color superimposed figure generation device characterized in that: (2) assigning area numbers to the plurality of color areas, storing the area numbers of the color areas and the set/reset code in the image memory; The color superimposition system according to claim 1, further comprising a circuit immediately before the decoding circuit for converting an area number of a signal read out by rask scanning into a display priority number of a color area. Figure generator. (8) Immediately after the circuit that distinguishes the color of the color area by area number, outputs the maximum value of the display priority number, and converts it into a pattern signal, the display priority number is assigned to the area of the color area. A color superimposed figure generating device according to item 1 of the claimed scope of the patent, characterized in that it includes a circuit that converts the area number into a color signal of the color area, and further includes a circuit that converts the area number into a color signal of the color area. A circuit that distinguishes the display priority and color of a color area by area number, and converts the area number into a display priority number.
Claims 1, 2, and 3 each include a circuit that converts a display priority number into an area number, and a circuit that converts an area number into a color signal of a color area.
The color superimposed figure generator described in Section 1.