JPS61288585A - Method for fetching video of itv camera - Google Patents

Abstract

PURPOSE:To store a video in a video region in a memory without fail even when the pulse width is fluctuated while a delay time of a video signal of an ITV camera is neglected by generating a memory address signal and a memory write signal from the leading of a blank signal. CONSTITUTION:A blank signal (c) is extracted from a composite video signal (j) by a blank signal extraction circuit 6 and given to a memory timing genera tor 2. The memory timing generator 2 generates the memory address signal (g) and the memory write signal (h) from the leading of the blank signal (c) to form a memory fetch effective area M2. Further, a shift clock signal (e) and a load signal (f) are generated and given to a serial input/parallel output shift register 4. Since they are extracted from the composite video signal (j), no delay time is caused. Thus, the video fetch region V2 in the composite video signal (j) is coincident with the memory fetch effective region M2 without fail and the full video region is stored in memory 5.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention is applicable to IT used for pattern recognition, shape recognition, etc.
The present invention relates to a method of storing video signals in a memory in a V camera.

[Conventional technology]

Figure 3 shows a video capture device for explaining the conventional ITV camera video capture method, and Figure 4 shows a conventional TT camera.
The timing of capturing images of the V camera is shown. The following will explain using these figures. The horizontal synchronization signal a and the vertical synchronization signal b (not shown) shown in Fig. 4 (al) are input from the synchronization signal generator 1 to the IT camera as external synchronization signals. do,
As shown in FIG. 4(C), the internal blank signal BLI is
, generates a horizontal synchronization signal a1. Therefore, Fig. 4 (bl
The blank signal C from the synchronization signal generator 1 shown in FIG. 4 and the composite video signal j shown in FIG. When a signal is taken into memory, the memory timing generator 2 generally uses the blank signal C from the synchronization signal generator 1 as shown in FIG. 4 (14).
), a memory address signal g and a memory write signal are generated to form a memory capture valid area M1, and this memory capture valid area M1 is delayed by ΔT from the composite video signal j shown in FIG. 4(C). generate time. Therefore, as shown in FIG. 4 (C1, (d)), the memory capture effective area M1
If there is an image outside the image capture area ■1 shown in FIG. 4 (al), it is impossible to store that part of the image in the memory. In other words, FIG. 4 (C1, !d) An area VN in which video cannot be captured occurs as shown in FIG.

As shown in FIG. 4(C), the binarization circuit 3 converts the composite video signal j to a certain binarization circuit threshold level TH.
The signal is cut at I to generate a binary output signal d shown in FIG. 4(d). This binarized output signal d is input to a serial input parallel output shift register 4, converted into serial to parallel by a shift clock signal e and a load signal f output from a memory timing generator 2, and is sent to a memory 5 as a data signal i.
, and are sequentially stored in the memory at the address of the memory address signal g.

[Problem that the invention seeks to solve]

As shown in FIG. 4 (C1, (e)), the synchronizing signal generator 1
The memory address signal g and memory write signal generated by the blank signal C from ゜ inevitably generate a delay time of ΔT with the blank signal from the ITV camera, so images outside the effective memory capture area Ml cannot be captured. It becomes impossible. Therefore, in a system in which the remaining area excluding the blank signal C is used as a memory capture area, there is a problem in that images that cannot be captured occur.

The present invention has been made in view of these points, and its purpose is to operate a memory timing generator using a blank signal extracted from a blank signal extraction circuit in order to eliminate areas where video cannot be captured. The object of the present invention is to obtain a video capture method that uses the entire video area as an effective memory capture area.

[Means for solving problems]

To achieve this object, the present invention extracts a blank signal from a video signal from an ITV camera, and generates a memory address signal and a memory write signal from the rising edge of this blank signal.

[Effect]

In the present invention, even if the pulse width varies, the image within the image area is always stored in the memory.

〔Example〕

FIG. 1 shows a video capture device for explaining an embodiment of the ITV camera video capture method according to the present invention, and FIG. 2 shows the ITV camera video capture timing. The synchronizing signal generator 1 shown in FIG. 1(a) generates a horizontal synchronizing signal a as in the conventional case.

Outputs vertical synchronization signal to ITV camera. Figure 1 (b
1, a blank signal C shown in FIG. 2 (C1) is extracted by a blank signal extraction circuit 6 from a composite video signal j shown in FIG.

The memory timing generator 2 generates a memory address signal g and a memory write signal shown in FIG. 2(d) from the rise of the blank signal C to form a memory capture effective area M2. The memory timing generator 2 also generates a shift clock signal e and a load signal f synchronized with the blank signal C, and supplies them to the serial input parallel output shift register 4.

Blank signal C extracted from composite video signal j
Since the memory address signal g and the memory write signal are extracted, the delay time ΔT shown in FIG. 4 does not occur. Therefore, the video capture area 4v2 in the composite video signal j in FIG.

The operation of the binarization circuit 3 shown in FIG. 1(b) is the same as the conventional one, and the composite video signal j is cut at a certain binarization circuit threshold level TH2 shown in FIG. ) outputs the binarized output signal d shown in FIG.

Since this embodiment focuses on the method of capturing video into memory, the memory read timing and other bus interfaces are omitted.

[Effects of the Invention] As described above, the present invention extracts a blank signal of a video signal from an ITV camera, and generates a memory address signal from the rising edge of this blank signal.

By generating a memory write signal, the delay time of the ITV camera's video signal can be ignored, and even if the pulse width changes during the blank signal generation process within the ITV camera, the video in the video area can always be stored in the memory. effective.

[Brief explanation of the drawing]

FIG. 1 is a system diagram showing a video capture device for explaining an embodiment of the video capture method for an ITV camera according to the present invention, FIG. 2 is a waveform diagram for explaining its operation, and FIG. 3 is a conventional FIG. 4 is a system diagram showing a video capture device for explaining a video capture method of an ITV camera, and a waveform diagram for explaining its operation. 1...Synchronization signal generator, 2...Memory timing generator, 3...Binarization circuit, 4...Series input parallel output shift register, 5...Memory, 6 ...
・Blank signal extraction circuit.

Claims (1)

[Claims] A method for capturing video from an ITV camera, characterized in that a blank signal of a composite video signal from the ITV camera is extracted, and a memory address signal and a memory write signal are generated from the rising edge of this blank signal.
How to capture video from a TV camera.