JPS61288495A - Manufacture of multilayer circuit board - Google Patents

Manufacture of multilayer circuit board

Info

Publication number
JPS61288495A
JPS61288495A JP12998385A JP12998385A JPS61288495A JP S61288495 A JPS61288495 A JP S61288495A JP 12998385 A JP12998385 A JP 12998385A JP 12998385 A JP12998385 A JP 12998385A JP S61288495 A JPS61288495 A JP S61288495A
Authority
JP
Japan
Prior art keywords
hole
layer
circuit board
wiring layer
multilayer circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP12998385A
Other languages
Japanese (ja)
Inventor
博 舘野
白畑 功
秀夫 関口
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Furukawa Electric Co Ltd
Original Assignee
Furukawa Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Furukawa Electric Co Ltd filed Critical Furukawa Electric Co Ltd
Priority to JP12998385A priority Critical patent/JPS61288495A/en
Publication of JPS61288495A publication Critical patent/JPS61288495A/en
Pending legal-status Critical Current

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  • Production Of Multi-Layered Print Wiring Board (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。
(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 この発明は多層回路基板の製造方法に関するものである
DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method for manufacturing a multilayer circuit board.

〔従来の技術〕[Conventional technology]

アルミニウム等の金属基板上に絶縁層を介して多層に配
線層を設けた多層回路基板において、該配線層間の導通
を行う方法の一つとしてし所謂スルーホールによるもの
がある。
In a multilayer circuit board in which multiple wiring layers are provided on a metal substrate such as aluminum with insulating layers interposed therebetween, one method for establishing electrical conduction between the wiring layers is by using so-called through holes.

即ち第4図の如く、予め透孔(!l)を設けたアルミニ
ウム基板O1の両面に絶縁層(ta allを介して銅
箔(11(1mを積層しく同図ayb)p次に前記透孔
(111の部分に銅箔を貫くスルーホール(14)を穿
け(同図C)、以下該スルーホール内を化学メッキ又は
電解メ・νキにより金属メッキ層を形成すると共に銅ペ
ースト等を埋め込み導通させるのである。又他の方法と
して、第5図の如く、金属基板(11の一面に絶縁層(
laを介して導電ペースト(11(11・・・を絶縁層
(1乃(la・・・を介して夫々所望のパターンに印刷
積層し、該導電ペーストが各回路を予め決められた部分
にて導通するようにしたものがある。
That is, as shown in Fig. 4, a copper foil (11 (1 m) is laminated on both sides of an aluminum substrate O1, in which through holes (!l) have been formed in advance, via an insulating layer (ta all), and then the through holes are (Drill a through hole (14) through the copper foil at the part 111 (C in the same figure), and then form a metal plating layer inside the through hole by chemical plating or electrolytic plating, and fill it with copper paste etc. to make it conductive. As another method, as shown in FIG. 5, an insulating layer (
A conductive paste (11 (11...) is printed and laminated in a desired pattern via an insulating layer (1) (la...), and the conductive paste connects each circuit at a predetermined portion. There are some that are designed to conduct.

〔発明が解決しようとする問題点〕[Problem that the invention seeks to solve]

上記各種方法には夫々特長があるが、ただ、(i) 上
記スルーホール方法においては、アルミニウム板などの
金属製基1反を用いた本来の狙い、即ちその優れた放熱
性、加工性及び剛性が例えば基板透孔設置、両面絶縁層
の存在等により損われる恐れがあり、今後主流になるこ
とが考えられるリードレスIC部品の取付がはんだ印刷
法理外の場合困難になる、 (iil他方、上記印刷積層による方法は、導電材料に
樹脂バインダーが用いられていることからソノ導電性が
概ね低く、半田付けが困難になるために、第2層以上は
全てメッキによる回路補助を要し、該メッキ時の湿式処
理が製品品質を不安定化する恐れがある、 などの問題があった。
Each of the above-mentioned methods has its own features, but (i) the above-mentioned through-hole method achieves the original aim of using a metal substrate such as an aluminum plate, namely, its excellent heat dissipation, workability, and rigidity. For example, there is a risk of damage due to the installation of through holes on the board, the presence of double-sided insulating layers, etc., and it will be difficult to install leadless IC components, which are expected to become mainstream in the future, if solder printing is not legal. In the printed lamination method, since a resin binder is used as the conductive material, the conductivity is generally low and soldering is difficult. There were problems such as the possibility that the wet processing at the time could destabilize product quality.

〔間廟点を解決するための手段〕[Means for solving the mamyo point]

ここに発明者等はかかる問題を解決すべく鋭意検討を重
ねた結果この発明を完成したのである。
The inventors have completed this invention as a result of intensive studies to solve these problems.

即ち本発明は、アルミニウム、鉄等の金属基板上に設け
られた絶縁層上の、絶縁層を介して二層以上の導体配線
層を設けた多層回路基板を得るに際し、上記導体配線層
の形成を金属箔の積層又は所望の方法による配線パター
ン化にて行い、得られた多層配線層の所望の位置に上部
より最下層配線層に達して終る孔を穿け、鎖孔に導電体
埋込み又はメッキによる導体層着あるいはこれら両者の
併用にて各配線層間の導通を行うようにしたことを特徴
とする多層回路基板の製造方法である。
That is, the present invention provides a multilayer circuit board in which two or more conductive wiring layers are provided on an insulating layer provided on a metal substrate such as aluminum or iron, with the insulating layer interposed therebetween. This is done by laminating metal foil or patterning the wiring by a desired method, and then holes are made at desired positions in the resulting multilayer wiring layer, starting from the top and ending at the lowest wiring layer, and the chain holes are filled with conductors or plated. This method of manufacturing a multilayer circuit board is characterized in that conduction between each wiring layer is achieved by depositing a conductor layer using the above method or by using both of these methods in combination.

〔作 用〕[For production]

この発明においては、金属基板上に2層以上の配線層を
設け、最上層から最下層に達する位置にて終る孔を穿け
、鎖孔に導電体を埋め層間導通を行うようにしたので、
上記金属製基板本来の放熱性、剛性等が損われない。
In this invention, two or more wiring layers are provided on a metal substrate, a hole is made from the top layer to the bottom layer, and a conductor is filled in the chain hole to provide interlayer conduction.
The heat dissipation properties, rigidity, etc. inherent to the metal substrate are not impaired.

又半田付性も維持され、しかも品質の不安定化−を招く
ことも殆んどない。
In addition, solderability is maintained, and quality instability is hardly caused.

〔実施例〕〔Example〕

以下図面によりこの発明の詳細な説明する。 The present invention will be explained in detail below with reference to the drawings.

第1図(a)において(1)はアルミニウム等の金属基
板とその上面に第1の絶縁層(2a)を介して第1の鋼
箔配線層(3a)及び第2の絶縁層(2a)を介して第
2の銅箔配線層(3b)を常法の如く積層する。
In FIG. 1(a), (1) is a metal substrate made of aluminum or the like, and a first steel foil wiring layer (3a) and a second insulating layer (2a) are formed on the upper surface of the substrate via a first insulating layer (2a). A second copper foil wiring layer (3b) is laminated via a conventional method.

次に第1図(blのように、上記第1の配線層(2a)
に届くまで上部より所望径の精密孔穿けを行い孔(4)
を形成する。
Next, as shown in FIG. 1 (bl), the first wiring layer (2a)
Drill a precision hole of the desired diameter from the top until it reaches hole (4).
form.

この孔(4)の形成は実際にはエンドミル又はルータ−
ドリル又は、レーザー光を用い次のようにして上述の第
1の配線層(2a)にて終る孔(4)を得る。
This hole (4) is actually formed using an end mill or router.
A hole (4) terminating in the first wiring layer (2a) described above is obtained using a drill or a laser beam in the following manner.

即ち・NCドリルマシンを使用し、 (i)上記第1の配線層(3b)とドリル間に微弱電圧
を印加しておき、孔穿は時の両者の接触時を開始点とし
てドリル下降量の制御をNC装置にて行なうことにより
孔の深さを決める、 (ii)金属基板(1)の下面から第1層の配線層(3
a)の高さをドリル本体のNC装置に記憶させ、この記
憶量によりドリルの下降停止点を制御して孔の深さを決
める、 次に第1図(elのように、鎖孔(4)に金属導体(5
)を埋込むか又はメッキにより導体を付着させ再記線層
(3a) (3b)の導通を行う。
In other words, use an NC drill machine, (i) apply a weak voltage between the first wiring layer (3b) and the drill, and drill the hole by adjusting the descending amount of the drill starting from the point of contact between the two. The depth of the hole is determined by controlling with an NC device. (ii) The first wiring layer (3) is
The height of a) is stored in the NC device of the drill body, and the depth of the hole is determined by controlling the descending stop point of the drill using this stored amount. Next, as shown in Figure 1 (el), the height of the chain hole (4 ) to the metal conductor (5
) is embedded or a conductor is attached by plating to make the rewriting layers (3a) and (3b) conductive.

第2図は本発明の他の実施例を示すものである。FIG. 2 shows another embodiment of the invention.

先づ第1図aの如く基板(1)の上述した導通用孔に対
応する位置にこれより稍広く孔(6)を穿け、この孔(
6)に絶縁材料(7)を埋め込み基板(1)と平滑に仕
上げ加工する。
First, as shown in Figure 1a, drill a hole (6) slightly wider than the hole (6) in the substrate (1) at a position corresponding to the above-mentioned conduction hole.
6) Embed the insulating material (7) and finish it smooth with the substrate (1).

次に上記実施例と同様にして同図(b)のように二層の
配線層を設ける。
Next, in the same manner as in the above embodiment, two wiring layers are provided as shown in FIG. 3(b).

そして上記絶縁体埋込部(7)に正確に位置させて同様
に孔(4)を穿け、これに導電体(5)を埋め再記線層
(3a) (3b)の導通を行う。
Then, a hole (4) is made in the same way, accurately positioned in the insulator buried portion (7), and a conductor (5) is filled in the hole to establish conduction between the rewriting layers (3a) and (3b).

この方法では上記導通孔の位置精度はかなり高く求めら
れるがその深さについてはややゆるく孔穿は用ドリルは
上記理外のものも適時使用し得る。
In this method, the positional accuracy of the through hole is required to be quite high, but the depth is somewhat loose, and a drill other than the above-mentioned drill may be used as appropriate.

上記導電体として導電ペーストを用いる場合は常法の如
く真空炉中でのエアー抜き及び焼成等を行う。
When a conductive paste is used as the above-mentioned conductor, air is removed and fired in a vacuum furnace as usual.

別法として第3図の如く、上記第2の配線層(3b)に
前もってエツチングにより、バイヤホールが必要な位置
上に穴をあけておき(同図a)、次にその穴の中心をね
らって真上よりレーザー光(YAGレーザ−0rCO2
レーザー等)にて第1の配線層3(a)に届くまでの穴
を加工し、その位置を反射光量の変化等にて制御するこ
とも可能である(同図b)。
Alternatively, as shown in Figure 3, a hole is previously etched in the second wiring layer (3b) at the position where a via hole is required (Figure 3a), and then the center of the hole is aimed. Laser light (YAG laser - 0rCO2
It is also possible to form a hole that reaches the first wiring layer 3(a) using a laser (eg, laser), and then control its position by changing the amount of reflected light, etc. (FIG. 2(b)).

す下両例共に常法のように以後の2層目パターン形成、
エツチングレジスト及び保護処理等の作業を行い製品化
する。
In both cases, the subsequent second layer pattern formation is carried out as usual.
Work such as etching resist and protection processing is performed to commercialize the product.

〔発明の効果〕〔Effect of the invention〕

本発明は上記説明で明らかなように、二層以上の導体配
線層を設けた多層回路基板を得るに際して上記導体配線
層の形成を金属箔の積層又は所望の方法による配線パタ
ーン化にて行い、上層配線層から最下層配線層に達して
終る孔を穿け、鎖孔に導電体埋込み又はメッキによる導
体層着あるいはこれら両者の併用にて各配線層間の導通
を行うようにしたので、上記金属基板の放熱性は充分保
持されると共に、その剛性が損われることがなく、更に
製品の各種特性を低下させる恐れも少い等上記の問題を
略解消し得る。
As is clear from the above description, the present invention provides a multilayer circuit board having two or more conductor wiring layers, in which the conductor wiring layers are formed by laminating metal foils or by patterning the wiring by a desired method. A hole is made from the upper wiring layer to the lowest wiring layer, and conduction between each wiring layer is achieved by burying a conductor in the chain hole, depositing a conductor layer by plating, or using a combination of both. The heat dissipation properties of the material are sufficiently maintained, the rigidity is not impaired, and there is little risk of deterioration of various properties of the product, so that the above-mentioned problems can be almost eliminated.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図、第2図及び第3図は本発明方法の実施例の夫々
工程図、第4図、第5図は夫々従来の方法の説明図であ
る。 1・・・基板、2m、2b・=−絶側L3 a、3b−
配線層、4・・・孔、5・・・導電体。 第1図   第2図 第3m   第4図 第5図 団ただiル1゜
1, 2 and 3 are process diagrams of an embodiment of the method of the present invention, and FIGS. 4 and 5 are explanatory diagrams of a conventional method, respectively. 1... Board, 2m, 2b・=-absolute side L3 a, 3b-
Wiring layer, 4...hole, 5...conductor. Figure 1 Figure 2 Figure 3m Figure 4 Figure 5 Group only 1゜

Claims (1)

【特許請求の範囲】[Claims]  アルミニウム、鉄等の金属基板上に設けられた絶縁層
上に、絶縁層を介して二層以上の導体配線層を設けた多
層回路基板を得るに際し、上記導体配線層の形成を金属
箔の積層又は、所望の方法による配線パターン化にて行
い、得られた多層配線層の所望の位置に上部より最下層
配線層に達して終る孔を穿け、該孔に導電体埋込み又は
メッキによる導体層着あるいはこれら両者の併用にて各
配線層間の導通を行うようにしたことを特徴とする多層
回路基板の製造方法。
When obtaining a multilayer circuit board in which two or more conductive wiring layers are provided on an insulating layer provided on a metal substrate such as aluminum or iron with an insulating layer in between, the formation of the conductive wiring layer is performed by laminating metal foils. Alternatively, wiring patterning may be performed by a desired method, and a hole may be formed at a desired position in the resulting multilayer wiring layer from the top to the bottom wiring layer, and a conductor may be embedded in the hole or a conductor layer may be attached by plating. Alternatively, a method for manufacturing a multilayer circuit board characterized in that conduction between each wiring layer is achieved by using both of these in combination.
JP12998385A 1985-06-17 1985-06-17 Manufacture of multilayer circuit board Pending JPS61288495A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP12998385A JPS61288495A (en) 1985-06-17 1985-06-17 Manufacture of multilayer circuit board

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP12998385A JPS61288495A (en) 1985-06-17 1985-06-17 Manufacture of multilayer circuit board

Publications (1)

Publication Number Publication Date
JPS61288495A true JPS61288495A (en) 1986-12-18

Family

ID=15023259

Family Applications (1)

Application Number Title Priority Date Filing Date
JP12998385A Pending JPS61288495A (en) 1985-06-17 1985-06-17 Manufacture of multilayer circuit board

Country Status (1)

Country Link
JP (1) JPS61288495A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61294896A (en) * 1985-06-24 1986-12-25 株式会社日立製作所 Manufacture of multilayer printed circuit board
JPH036096A (en) * 1989-06-02 1991-01-11 Matsushita Electric Works Ltd Circuit board

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61294896A (en) * 1985-06-24 1986-12-25 株式会社日立製作所 Manufacture of multilayer printed circuit board
JPH036096A (en) * 1989-06-02 1991-01-11 Matsushita Electric Works Ltd Circuit board

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