JPS61286932A - Access abnormality detecting circuit - Google Patents

Abstract

PURPOSE:To detect the failure of an address circuit and the misselection of a storage circuit in a system for controlling execution by an address counter by storing a code word corresponding to the value of an address in the storage device. CONSTITUTION:A code word corresponding to the value of an address has been previously stored in the storage device 4. When the address is continuously changed, an output A1 of an address storing circuit 3 is added by +1 in an arithmetic circuit 1 and the added signal is inputted and stored to/in the circuit 3 through a selecting circuit 2 under the control of a signal C1. Simultaneously, the output A1 is inputted to an encoding circuit 7 through a selecting circuit 6 under the control of the signal C1 and the output of the circuit 7 is stored in a code storing circuit 8. When the address is discontinuously changed, a new address A2 is stored in the circuit 3 and a value subtracted by '1' by an arithmetic circuit 5 is inputted and stored to/in the circuit 7. A code word CD1 outputted from the storage device 4 is compared with an output CD2 from the circuit 8 by a code comparator 9 to obtain an output ER as failure information.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Application of the Invention] The present invention reads a program from a storage circuit and executes it using the output of an address circuit. This is a failure detection circuit suitable for a 10-gram control system.

[Background of the invention]

A method using a parity prediction method for detecting a failure in an address circuit is known. However, in a program control system, it is necessary not only to detect a failure in the address circuit, but also to detect that a storage device has been selected incorrectly. This issue was not considered.

In addition, related to this type of device.

For example, Japanese Patent Application Laid-Open No. 56-2049 can be mentioned.

[Purpose of the invention]

An object of the present invention is to provide a method for detecting a failure in an address circuit or a storage device selection circuit during system execution in a system in which a program is stored in a storage device and its execution is managed by an address counter.

[Summary of the invention]

In the present invention, code words corresponding to address values are stored in advance in a storage device in order to detect failures in the address circuit and storage device. If the output of the address circuit is encoded by an encoding circuit and the value is compared with the code word output from the storage device, address circuit failures and incorrect selection of the storage device can be particularly detected.

[Embodiments of the invention]

An embodiment of the present invention will be described below with reference to FIG.

A storage device 4 that stores code words used for programs and failure detection, an address storage circuit 3 that stores addresses to be output to the storage device, and an output A1 of the address storage circuit.
1, a selection port @2 which selects the output of the arithmetic circuit 1 and a new address A2 when the address changes discontinuously and transmits it to the address storage circuit 3. Arithmetic circuit for decrementing address A2 by 5. When the address changes continuously and when the address changes discontinuously, the address storage circuit 3
A selection circuit 6 which selects the output A1 of the output A1 and the output of the arithmetic circuit 5 and transmits the same to the encoding circuit, an encoding circuit 7 which encodes the output of the selection circuit 6, and a code storage circuit 8 which stores the output of the encoding circuit 7. It is composed of a code comparison circuit 9 that compares the output CD2 of the code storage circuit 8 and the code output CDI of the storage device 4.

The storage device 4 stores in advance a code word corresponding to the value of the address (. The value of the address (N-1) is encoded and stored at the address N. However, the code word corresponding to the value of the address is stored in advance. stores the code word corresponding to the value of the final address of the storage device.

When the address changes continuously, the output A1 of the address storage circuit 3 is incremented by 1 in the arithmetic circuit 1, and is inputted to the address storage circuit 3 through the selection circuit 2 under the control of the C1 signal and stored by the C2 signal. In parallel with the above, the address A1 is input to the encoding circuit 7 through the selection circuit 6 under the control of the C1 signal, and the output of the encoding circuit 7 is stored in the code storage circuit 8 according to the C2 signal. When the address changes discontinuously, a new address A2 is stored in the address storage circuit 3 through the selection circuit 2 under the control of the C1 signal. The value subtracted by 1 from the new address A2 by the arithmetic circuit 5 is input to the encoding circuit 7 through the selection circuit 6 under the control of the C1 signal, and the output of the encoding circuit 7 is stored in the code storage circuit 8 by the C2 signal. .

The code word CDI output from the storage device and the output CDI of the code storage circuit 8 are determined by the output A1 of the address storage circuit 3.
are compared in the code comparison circuit 9, and an output ER is obtained as failure information.

In this embodiment, the address storage circuit 3. Encoding circuit 7
etc., the code output C from the storage device 4
Since the values of DI and the output CDI of the code storage circuit 8 do not match, it is possible to detect that a failure has occurred.

〔Effect of the invention〕

According to the present invention, during program execution, the address W! that is managing the program execution! r. Failures in the storage device that stores programs can be detected, which has the effect of preventing system failures due to abnormalities in the program execution order.

C2...memory timing signal, A1...address, Part II! 1

Claims (1)

[Claims] 1. In a system consisting of an address counter that manages program execution and a storage device that stores the program, access abnormality detection is characterized in that a circuit that encodes the address and a code word corresponding to the address are stored in the storage device in advance. circuit.