JPS61283159A - Semiconductor device and manufacture thereof - Google Patents
Semiconductor device and manufacture thereofInfo
- Publication number
- JPS61283159A JPS61283159A JP60125412A JP12541285A JPS61283159A JP S61283159 A JPS61283159 A JP S61283159A JP 60125412 A JP60125412 A JP 60125412A JP 12541285 A JP12541285 A JP 12541285A JP S61283159 A JPS61283159 A JP S61283159A
- Authority
- JP
- Japan
- Prior art keywords
- well layer
- layer
- region
- well
- conductivity type
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 24
- 238000004519 manufacturing process Methods 0.000 title claims description 8
- 239000012535 impurity Substances 0.000 claims abstract description 24
- 239000000758 substrate Substances 0.000 claims abstract description 14
- 150000002500 ions Chemical class 0.000 claims abstract description 3
- 238000009792 diffusion process Methods 0.000 claims description 11
- 239000010410 layer Substances 0.000 abstract description 52
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 abstract description 5
- 229910052782 aluminium Inorganic materials 0.000 abstract description 5
- 239000011229 interlayer Substances 0.000 abstract description 4
- 229920002120 photoresistant polymer Polymers 0.000 abstract description 4
- 229910052796 boron Inorganic materials 0.000 abstract 1
- -1 boron ions Chemical class 0.000 abstract 1
- 230000000295 complement effect Effects 0.000 description 5
- 238000000034 method Methods 0.000 description 4
- 230000000694 effects Effects 0.000 description 3
- 238000002955 isolation Methods 0.000 description 3
- 230000010354 integration Effects 0.000 description 2
- 238000005468 ion implantation Methods 0.000 description 2
- 230000003321 amplification Effects 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 238000002347 injection Methods 0.000 description 1
- 239000007924 injection Substances 0.000 description 1
- 238000003199 nucleic acid amplification method Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
- H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
- H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
- H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
- H01L27/0921—Means for preventing a bipolar, e.g. thyristor, action between the different transistor regions, e.g. Latchup prevention
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Element Separation (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は半導体装置及びその製造方法に関し、特に信頼
性上重要な耐う、チア、ブ性の向上をはかった相補型半
導体装置及びその製造方法に関する。[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a semiconductor device and a method for manufacturing the same, and in particular to a complementary semiconductor device and its manufacturing method that improve the resistance, resistance, and resistance, which are important for reliability. Regarding the method.
従来、相補型半導体装置においては、外部からの雑音等
により訪起されるラッチアップ現象対策として数々の手
段がとられおり、第２図に従来例の一例を示丈りエル層
や基板の電位が、雑音電流の注入等により変動しにくく
するために、第２図中に示すよ５に電位固定用の電極を
設けることにより、耐うッチア、グ性を向上させてきた
。第２図において、１１はＮ型半導体基板、１２はＰウ
ェル層、１３は素子分離絶縁膜、１４はゲート絶縁膜、
１５はゲート電極、１６はＮ拡散層、１７＋
はＰ拡散層、１８は層間絶縁膜、１９はコンタクト部、
２０はアルミニウム電極である。Conventionally, in complementary semiconductor devices, a number of measures have been taken to counter the latch-up phenomenon caused by external noise, etc. Figure 2 shows an example of a conventional example. However, in order to make it less likely to fluctuate due to the injection of noise current, etc., a potential fixing electrode is provided at 5 as shown in FIG. 2, thereby improving resistance to cha and g. In FIG. 2, 11 is an N-type semiconductor substrate, 12 is a P-well layer, 13 is an element isolation insulating film, 14 is a gate insulating film,
15 is a gate electrode, 16 is an N diffusion layer, 17+ is a P diffusion layer, 18 is an interlayer insulating film, 19 is a contact part,
20 is an aluminum electrode.
上述した従来方法においては、電位固定用の電極は、ウ
ェル層や、基板に数多く設けなければ、耐ラツチアツプ
性の向上は期待できないため、電位固定用電極部の面積
が非常に大きくなり、集積化には、向かないばかりでな
く、配線が複雑になるためにレイアウトの面からも不利
益でおるという欠点がある。In the conventional method described above, unless a large number of potential fixing electrodes are provided in the well layer or the substrate, improvement in latch resistance cannot be expected, so the area of the potential fixing electrode part becomes extremely large, making it difficult to integrate. Not only is it unsuitable, but it also has the disadvantage of complicating the wiring, which is disadvantageous in terms of layout.
本発明は、従来の欠点を除去し、集積度をさげることな
く、配線も複雑化せず、かつトランジスタ及びドレイン
領域の接合容量ｔ−Ｓげることなく、耐う、チア、プ性
を向上させた半導体装置及びその製造方法を提供するこ
とを目的とする。The present invention eliminates the drawbacks of the conventional technology and improves resistance to chipping and leakage without reducing the degree of integration, complicating wiring, and increasing the junction capacitance t-S of the transistor and drain regions. An object of the present invention is to provide a semiconductor device and a method for manufacturing the same.
本発明の第１の発明の半導体装置は、一導電型の半導体
基板の所定領域に逆導電型の不純物の拡表面から該ウェ
ル層側面部を含み該ウェル層より深く、かつ該ウェル層
と同一導電型で該ウェル層より高い不純物濃度を有する
不純物領域とを含んで構成される。A semiconductor device according to a first aspect of the present invention includes a side surface of the well layer from a surface expansion of an impurity of an opposite conductivity type in a predetermined region of a semiconductor substrate of one conductivity type, which is deeper than the well layer and is the same as the well layer. and an impurity region having a conductivity type and a higher impurity concentration than the well layer.
また、本発明の第２の発明の半導体装置の製造方法は、
一導電型の半導体基板に逆導電型のウェル層を形成する
工程と、該ウェル層を形成した前記半導体基板上に形成
したマスクの開孔部を通し前記ウェル層表面から該ウェ
ル層側面部を含み該ウェル層より深く、かつ該クエ／Ｌ
／ｌｉ１と同一導電型で該ウェル層より高い不純物濃度
を有する不純物領域を形成する工程とを含んで構成され
る。Further, the method for manufacturing a semiconductor device according to the second invention of the present invention includes:
A step of forming a well layer of an opposite conductivity type on a semiconductor substrate of one conductivity type; deeper than the well layer and containing the que/L
/li1 and forming an impurity region having the same conductivity type as the well layer and having a higher impurity concentration than the well layer.
次に、本発明の実施例について、図面を参照して説明す
る。Next, embodiments of the present invention will be described with reference to the drawings.
第１図（ａｌ〜（ｅ）は本発明の一実施例を説明するた
めに工程順に示した断面図、第１図（０は第１図（ｅ）
の平面図である。Figures 1 (al to (e) are cross-sectional views shown in the order of steps to explain one embodiment of the present invention, Figure 1 (0 is Figure 1 (e)
FIG.
まず、本実施例の製造方法を説明する。第１図（ａｌに
示すように、Ｎ型半導体基板１０１に従来の製法により
Ｐウェル層領域を選択的に形成する。First, the manufacturing method of this example will be explained. As shown in FIG. 1 (al), a P well layer region is selectively formed on an N type semiconductor substrate 101 by a conventional manufacturing method.
次に、第１図（ｂ）に示すように、フォトレジストをマ
スクにして、Ｐ型不純物であるホク素のイオン注入を行
い、Ｐウェル階領域の中心部より濃いＰ型不純物領域１
０４をＰウェル層１０２より深く形成する。なお上記工
程のホトレジストのマスク開孔部は図示の如くＰウェル
の接合部の側面にイオン注入領域が接するように開孔し
たが側面部を内部に含む位置に設けても差支えない。Next, as shown in FIG. 1(b), using a photoresist as a mask, ion implantation of hoxine, which is a P-type impurity, is performed, and the P-type impurity region 1 is denser than the center of the P-well region.
04 is formed deeper than the P well layer 102. Although the openings in the photoresist mask in the above step were opened so that the ion implantation region was in contact with the side surface of the P-well junction as shown in the figure, they may be provided at a position that includes the side surface inside.
次に、第１図（Ｃ）に示すように、素子分離絶縁層１０
５を形成する。Next, as shown in FIG. 1(C), an element isolation insulating layer 10
form 5.
次に、第１図（ｄｌに示すように、ゲート絶縁膜１０６
を形成し、さらにゲート電極１０７を形成したのち、ト
ランジスタのソースΦドレイン領域や電位固定電極用の
拡散層であるＮ 層１０８゜Ｐ十層１０９を形成する。Next, as shown in FIG. 1 (dl), the gate insulating film 106
After forming a gate electrode 107, an N layer 108 and a P layer 109, which are diffusion layers for the source and drain regions of the transistor and the potential fixing electrode, are formed.
最後に、第１図（ｅ）に示すように層間絶縁膜１１０を
形成したのち、コンタクト部１１１を選択的に開孔し、
アルミニウム電極１１２を形成することにより本発明を
適用した相補型半導体装置が得られる。Finally, as shown in FIG. 1(e), after forming an interlayer insulating film 110, contact portions 111 are selectively opened.
By forming the aluminum electrode 112, a complementary semiconductor device to which the present invention is applied can be obtained.
第１図（０は完成した第１図（ｅ）に示す一実施例の模
式的平面図であり、Ｎ型半導体基板１０１の所定領域に
Ｐ型不純物の拡散により形成されたＰ型りエル層１０２
と、ウェル層の側面部を含みウェル層より深く、かつウ
ェル層と同一導電型のＰ型でウェル層より高い不純物濃
度を有する不純物領域１０４を含んで本実施例の主要部
は構成され、上記領域の形成後ウェル層内にＮ拡散層１
０８゜ゲート絶縁膜１０６．ゲート電極１０７より構成
されるＮｆｉＭＯ８）ランジスタと、Ｐ拡散層１０９と
ゲート絶縁膜、ゲート電極より構成されるＰ型ＭＯＳト
ランジスタと、電位固定用拡散層と、これら拡散層に形
成したアルミニウム電極とを含むことにより一実施例の
相補型半導体装置が構成されている。FIG. 1 (0 is a schematic plan view of the completed embodiment shown in FIG. 1(e)), in which a P-type reel layer is formed in a predetermined region of an N-type semiconductor substrate 101 by diffusion of P-type impurities. 102
The main part of the present embodiment includes an impurity region 104 that includes the side surface of the well layer, is deeper than the well layer, is P-type of the same conductivity type as the well layer, and has a higher impurity concentration than the well layer. After forming the region, N diffusion layer 1 is formed in the well layer.
08°Gate insulating film 106. An NfiMO8) transistor composed of a gate electrode 107, a P-type MOS transistor composed of a P diffusion layer 109, a gate insulating film, and a gate electrode, a potential fixing diffusion layer, and an aluminum electrode formed on these diffusion layers. A complementary semiconductor device of one embodiment is constructed by including the above.
なお、本実施例ではウェル層の側面部全部に高濃度不純
物領域を形成したがラッチアップ現象を起し易い一部側
面に形成しても効果のあることは説明するまでもない。In this embodiment, the high concentration impurity region is formed on the entire side surface of the well layer, but needless to say, it is also effective to form it on a portion of the side surface where latch-up is likely to occur.
本発明は、以上説明したように、半導体基板とウェル層
領域との接合領域で、ウェル層の側面部のすくなくとも
一部に、ウェル層より深く、ウェルと同じ導電型の不純
物のイオン打ち込みによりウェル層領域の中心部より高
い不純物濃度層を形成することにより、集積度を下げず
、かつ、トランジスタのソース及びドレイン領域の接合
容ｉｔを上げる仁となく、耐ラツチアツプ性を向上させ
る効果がある。As explained above, the present invention provides a well layer by implanting impurity ions of the same conductivity type as the well, deeper than the well layer, into at least a part of the side surface of the well layer in the junction region between the semiconductor substrate and the well layer region. By forming a layer with a higher impurity concentration than the center of the layer region, there is an effect of improving the latch-up resistance without lowering the degree of integration and without increasing the junction capacitance of the source and drain regions of the transistor.
ウェルの側面部や、底面部のすくなくとも一部を高濃反
不純物層とするのは、ウニＡ［’ｔ−ベース／＆
とするバイポーラトランジスタの電流増幅率を底下させ
ることになり、かつ、ウェル層の抵抗を小さくする効果
かめるために、耐ラツチアツプ性の向上には非常に有効
である。Making at least part of the side and bottom portions of the well a highly concentrated anti-impurity layer will lower the current amplification factor of the bipolar transistor using Uuni A['t-base/&; Since it has the effect of reducing the resistance of the layer, it is very effective in improving latch-up resistance.
第１図（ａ）〜（ｅ）は本発明の一実施例を説明するた
めに工程順に示した断面図、第１図（ｆ）は第１図ｔｅ
ｌの模式的平面図、第２図は従来の相補型半導体装置の
断面図である。
１１ 、 ｌ Ｏ１−−−・−・Ｎ型半導体基板、１２
，１０２・・・・・・Ｐウェル層、１３，１０５・・・
・・・素子分離絶縁層、１４，１０６・・・・・・ゲー
ト絶縁膜、１５，１０７＋
・・・・・・ゲート１！極、１６，１０８・・・・・・
Ｎ 拡散層、１７ 、１０９・・−・−・Ｐ拡散層、１
８．ｌｌｏ・川・・層間絶縁膜、１９，１１１・・・・
・・コンタクト部、２０．１１２・・・・・・アルミニ
クムｔ＆、１０３・・・・・・フォトレジスト、１０４
・・・・・・高濃度Ｐ型不純物領域。
代理人 弁理士 内 原 晋、、′’；”：”、
７．、之１・１１２，７：
＼、−
８１図FIGS. 1(a) to 1(e) are cross-sectional views shown in the order of steps to explain one embodiment of the present invention, and FIG. 1(f) is a cross-sectional view of FIG.
FIG. 2 is a cross-sectional view of a conventional complementary semiconductor device. 11, l O1---N-type semiconductor substrate, 12
, 102... P well layer, 13, 105...
...Element isolation insulating layer, 14,106...Gate insulating film, 15,107+...Gate 1! pole, 16,108...
N diffusion layer, 17, 109...P diffusion layer, 1
8. llo・kawa・interlayer insulating film, 19,111・・・・
...Contact part, 20.112...Aluminum T&, 103...Photoresist, 104
...Highly concentrated P-type impurity region. Agent: Susumu Uchihara, patent attorney, ``;”:”,
7. , No. 1, 112, 7: \, - Figure 81
Claims (2)
純物の拡散により形成された逆導電型ウェル層と、該ウ
ェル層と前記半導体基板との少なくとも一部の接合部で
前記ウェル層表面から該ウェル層側面部を含み該ウェル
層より深く、かつ該ウェル層と同一導電型で該ウェル層
より高い不純物濃度を有する不純物領域とを含むことを
特徴とする半導体装置。(1) A well layer of a reverse conductivity type formed by diffusion of impurities of a reverse conductivity type in a predetermined region of a semiconductor substrate of one conductivity type; What is claimed is: 1. A semiconductor device comprising: an impurity region that extends from the surface, includes a side surface of the well layer, is deeper than the well layer, has the same conductivity type as the well layer, and has a higher impurity concentration than the well layer.
成する工程と、該ウェル層を形成した前記半導体基板上
に形成したマスクの開孔部を通して前記ウェル層と同一
導電型の不純物をイオン注入し前記ウェル層と前記半導
体基板との少なくとも一部の接合部で前記ウェル層表面
から該ウェル層側面部を含み該ウェル層より深く、かつ
該ウェル層と同一導電型で該ウェル層より高い不純物濃
度を有する不純物領域を形成する工程とを含むことを特
徴とする半導体装置の製造方法。(2) A step of forming a well layer of an opposite conductivity type on a semiconductor substrate of one conductivity type, and introducing an impurity of the same conductivity type as the well layer through an opening of a mask formed on the semiconductor substrate on which the well layer is formed. ions are implanted into at least a portion of the junction between the well layer and the semiconductor substrate, and the well layer extends from the surface of the well layer to the side surface of the well layer, is deeper than the well layer, and is of the same conductivity type as the well layer. 1. A method of manufacturing a semiconductor device, comprising: forming an impurity region having a higher impurity concentration.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP60125412A JPS61283159A (en) | 1985-06-10 | 1985-06-10 | Semiconductor device and manufacture thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP60125412A JPS61283159A (en) | 1985-06-10 | 1985-06-10 | Semiconductor device and manufacture thereof |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS61283159A true JPS61283159A (en) | 1986-12-13 |
Family
ID=14909464
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP60125412A Pending JPS61283159A (en) | 1985-06-10 | 1985-06-10 | Semiconductor device and manufacture thereof |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS61283159A (en) |
-
1985
- 1985-06-10 JP JP60125412A patent/JPS61283159A/en active Pending
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