JPS61283131A - Manufacture of semiconductor integrated circuit substrate - Google Patents
Manufacture of semiconductor integrated circuit substrateInfo
- Publication number
- JPS61283131A JPS61283131A JP12437985A JP12437985A JPS61283131A JP S61283131 A JPS61283131 A JP S61283131A JP 12437985 A JP12437985 A JP 12437985A JP 12437985 A JP12437985 A JP 12437985A JP S61283131 A JPS61283131 A JP S61283131A
- Authority
- JP
- Japan
- Prior art keywords
- substrate
- porous
- oxide
- layer
- oxidation
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
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- Local Oxidation Of Silicon (AREA)
- Element Separation (AREA)
- Formation Of Insulating Films (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は、集積回路の素子領域となる単結晶半導体領域
が多孔質Si酸化物によって絶縁分離された構造を有す
る半導体集積回路基板において反りの少ない基板の形成
法に関するものである。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention is directed to the prevention of warpage in a semiconductor integrated circuit substrate having a structure in which a single crystal semiconductor region serving as an element region of an integrated circuit is insulated and isolated by a porous Si oxide. The present invention relates to a method for forming a small number of substrates.
多孔質Si酸化物を使用したこの種の集積回路基板に要
求される条件としては、基板の反りはできるかぎり少な
く、かつ用いる多孔質Si酸化物のエッチレートは単結
晶Siの熱酸化膜(以後、熱酸化膜とのみ称する)と同
等であることが製造プロセス上重要である。The conditions required for this type of integrated circuit board using porous Si oxide are that the warpage of the board is as small as possible, and that the etch rate of the porous Si oxide used is the same as that of a single-crystal Si thermal oxide film (hereinafter referred to as , thermal oxide film) is important in the manufacturing process.
単結晶Si層を多孔質Si酸化物で完全に絶縁分離する
には、単結晶Si膜の幅の最低的172の厚さの多孔質
Si酸化物を形成しなければならない。通常の集積回路
パターンとして使用されるl〇−幅の単結晶Si層を絶
縁分離するには5〜7−の多孔質Si酸化物が必要であ
る。In order to completely insulate the single crystal Si layer with porous Si oxide, the porous Si oxide must be formed to have a thickness that is at least 172 times the width of the single crystal Si film. A 5- to 7-porous Si oxide is required to insulate a l〇-wide single crystal Si layer used as a typical integrated circuit pattern.
° 〔発明が解決しようとする問題点〕Si基板の片面
にこのような厚い多孔質Si酸化物を形成すると応力に
よってSi基板には反りが生ずる。[Problems to be Solved by the Invention] When such a thick porous Si oxide is formed on one side of a Si substrate, the Si substrate will warp due to stress.
第2図は、弗酸濃度40vt、%、化成電流密度28m
A / antの条件で7pの多孔質Si層を形成し
、ウェット酸素雰囲気中、1050℃で酸化したときの
直径4インチSi基板の反りを示す。Figure 2 shows a hydrofluoric acid concentration of 40vt% and a chemical current density of 28m.
This figure shows the warpage of a 4-inch diameter Si substrate when a 7p porous Si layer is formed under A/ant conditions and oxidized at 1050°C in a wet oxygen atmosphere.
図から明らかなように、酸化時間が長くなるにつれてS
i基板の反りは大きくなっていく。反りが1100℃1
以上では微細パターンの形成、均一な各種薄膜の形成が
困難であり集積回路プロセスには使用することができな
い。As is clear from the figure, as the oxidation time increases, S
The warpage of the i-board becomes larger. Warpage is 1100℃1
With the above method, it is difficult to form fine patterns and various uniform thin films, and it cannot be used for integrated circuit processes.
しかし、反りを抑えるため、酸化時間を短くすると多孔
質Si酸化物は収縮による緻密化が進まず、緩衝弗酸液
等によるエッチレートは熱酸化膜に比べ非常に大きくな
り、やはり集積回路プロセスには使用できないという問
題があった。However, if the oxidation time is shortened in order to suppress warping, the porous Si oxide will not become denser due to shrinkage, and the etch rate with buffered hydrofluoric acid will be much higher than that of thermal oxide film, which is still difficult to achieve in the integrated circuit process. The problem was that it could not be used.
また、酸化温度を1000℃以下にするとSi基板の反
りは抑えられるが、温度が低いため酸化時間を長くして
も、1050℃における酸化時間が短いときと同様に多
孔質Si酸化物のエッチレートは大きく、集積回路プロ
セスでは使用できなかった。In addition, if the oxidation temperature is set to 1000°C or less, the warping of the Si substrate can be suppressed, but even if the oxidation time is increased because the temperature is low, the etch rate of the porous Si oxide is the same as when the oxidation time is short at 1050°C. were too large to be used in integrated circuit processes.
このように、半導体基板の反りが小さく、かつ多孔質S
i酸化物のエッチレートを熱酸化膜の値と同等にする酸
化方法はこれまでなかった。In this way, the warpage of the semiconductor substrate is small and the porous S
Until now, there has been no oxidation method that makes the etch rate of i-oxide equivalent to that of a thermal oxide film.
本発明はこのような従来の問題点を解決するもので、多
孔質Si酸化物からの応力を緩和して半導体基板の反り
を低減し、かつ多孔質5iN1化物のエッチレートを熱
酸化膜と同等にした絶縁分離基板を提供するものである
。The present invention solves these conventional problems by alleviating the stress from the porous Si oxide, reducing the warpage of the semiconductor substrate, and making the etch rate of the porous 5iN1 oxide equivalent to that of a thermal oxide film. The present invention provides an insulating isolation substrate with a
上記の問題点を解決するために、本発明は、半導体基板
上に島状の単結晶半導体領域および多孔質Si層を形成
し、該多孔質Si層を酸化して多孔質Si酸化物を形成
し、該多孔質Si酸化物によって上記単結晶半導体領域
の側面および底面の一部または全部を分離する工程を含
む半導体集積回路基板の製造方法において、上記半導体
基板に転位を発生させた後、上記多孔質Si酸化物が流
動しうる酸化条件で上記多孔質Si層を酸化することを
特徴とする。In order to solve the above problems, the present invention forms an island-shaped single crystal semiconductor region and a porous Si layer on a semiconductor substrate, and oxidizes the porous Si layer to form a porous Si oxide. In the method for manufacturing a semiconductor integrated circuit substrate including the step of isolating part or all of the side and bottom surfaces of the single crystal semiconductor region using the porous Si oxide, after generating dislocations in the semiconductor substrate, The method is characterized in that the porous Si layer is oxidized under oxidizing conditions that allow the porous Si oxide to flow.
本発明は、まず、半導体基板に転位を発生させた後、多
孔質Si層を酸化することによって、該酸化時に上記基
板に生じた転位によって多孔質Si酸化層から受ける応
力を相殺し半導体基板の反りを減少させることができる
とともに、酸化時間を十分様ることができるので、多孔
質Si酸化物の収縮による緻密化を進ませ、多孔質Si
酸化物のエッチレートを熱酸化膜のエッチレートとほぼ
同じにすることができる。The present invention first generates dislocations in a semiconductor substrate, and then oxidizes the porous Si layer, thereby canceling out the stress received from the porous Si oxide layer due to the dislocations generated in the substrate during the oxidation. In addition to reducing warpage, the oxidation time can be varied sufficiently, which promotes densification due to shrinkage of porous Si oxide and
The etch rate of the oxide can be made almost the same as the etch rate of the thermal oxide film.
以下本発明の実施例について説明する。 Examples of the present invention will be described below.
第1図(a)〜(f)は、Si基板上に単結晶Si層が
多孔質Si酸化物によって完全に分離された構造を形成
する工程を示す。FIGS. 1(a) to 1(f) show the process of forming a structure on a Si substrate in which a single crystal Si layer is completely separated by a porous Si oxide.
まず、第1図(a)に示すように、cz−p型、比抵抗
3〜5Ω・c+++Si基板101上に耐酸化性膜10
2、例えば窒化シリコン膜をCVD技術により堆積し、
さらに耐酸化性膜102上にレジスト103を塗布し、
リングラフィ技術によって選択的にレジスト103を除
去する。First, as shown in FIG. 1(a), an oxidation-resistant film 10 is deposited on a cz-p type, resistivity 3-5Ω, c+++ Si substrate 101.
2. For example, deposit a silicon nitride film by CVD technology,
Further, a resist 103 is applied on the oxidation-resistant film 102,
The resist 103 is selectively removed using a phosphorography technique.
次に、第1図(b)に示すように、レジスト103をマ
スクに耐酸化性膜102をエツチングする。Next, as shown in FIG. 1(b), the oxidation-resistant film 102 is etched using the resist 103 as a mask.
次に、第1図(c)に示すように、3族不純物、例えば
ホウ素を拡散技術、またはイオン注入技術を用いて耐酸
化性膜102が除去されたSi基板領域101へ注入し
、高濃度p型Si領域104を形成する。Next, as shown in FIG. 1(c), a group III impurity, such as boron, is implanted into the Si substrate region 101 from which the oxidation-resistant film 102 has been removed using a diffusion technique or an ion implantation technique. A p-type Si region 104 is formed.
次に、第1図(d)に示すように、レジスト103を除
去した後、5族不純物例えばヒ素、または水素原子をS
i基板101ヘイオン注入し、耐酸化性膜102の下の
みn型Si領域105を形成する。Next, as shown in FIG. 1(d), after removing the resist 103, Group 5 impurities such as arsenic or hydrogen atoms are removed by S
Hay ions are implanted into the i-substrate 101 to form an n-type Si region 105 only under the oxidation-resistant film 102.
次に、第1図(e)に示すように、弗酸中で陽極化成処
理、例えば弗酸濃度40wt、%、電流密度30mA/
aJの条件でSi基板101を多孔質5il106に変
えながらn型Si層105とSi基板101とを多孔質
Si層106で完全に分離する。Next, as shown in FIG. 1(e), anodization treatment is performed in hydrofluoric acid, for example, at a hydrofluoric acid concentration of 40 wt.% and a current density of 30 mA/%.
The n-type Si layer 105 and the Si substrate 101 are completely separated by the porous Si layer 106 while changing the Si substrate 101 to a porous 5il 106 under the condition of aJ.
次に、第1図(f)に示すように、多孔質Si層106
を酸化して多孔質Si酸化層107に変える。Next, as shown in FIG. 1(f), the porous Si layer 106
is oxidized to form a porous Si oxide layer 107.
このとき、−吹酸化の条件はSi基板101に転位を生
じさせるような酸化条件で行う。Si基板101の片面
に7//I11の多孔質Si酸化層107が形成される
と、多孔質Si酸化層107とSi基板101の熱膨張
係数の違いによりSi基板101は多孔質Si酸化層1
07側を凸にして反る。多孔質Siが多孔質Si酸化物
に変わるとき膨張あるいは収縮する。その変化は多孔質
Si層の密度や酸化条件で様々である。多孔質Si酸化
物が流動によって収縮するときにSi基板に転位を発生
させる。Si基板101に転位を発生させることにより
多孔質Si酸化層107から受ける応力を相殺しSi基
板101の反りを減少させることができる。At this time, the -blowing oxidation conditions are such as to cause dislocations in the Si substrate 101. When the porous Si oxide layer 107 of 7//I11 is formed on one side of the Si substrate 101, the Si substrate 101 becomes the porous Si oxide layer 1 due to the difference in thermal expansion coefficient between the porous Si oxide layer 107 and the Si substrate
Make the 07 side convex and warp. When porous Si changes to porous Si oxide, it expands or contracts. The change varies depending on the density of the porous Si layer and oxidation conditions. When the porous Si oxide contracts due to flow, dislocations are generated in the Si substrate. By generating dislocations in the Si substrate 101, the stress received from the porous Si oxide layer 107 can be offset and warpage of the Si substrate 101 can be reduced.
第3図は、常圧ウェット酸素雰囲気中で一次酸化を行っ
た場合の温度と時間の関係を示し、酸化条件の有効範囲
を示す。FIG. 3 shows the relationship between temperature and time when primary oxidation is performed in a normal pressure wet oxygen atmosphere, and shows the effective range of oxidation conditions.
(1)の領域は酸化温度が950℃以下であり多孔質S
i酸化膜は流動を起こさない。そのために、81基板に
は転位が入りに<<(1)の領域は不適当である。(3
)の領域は多孔質Si酸化膜が流動を起こす温度領域で
あるが酸化時間が短いために流動量が少なく転位の発生
量も少ない。従って、酸化条件としてはやはり不適当で
ある。(4)の領域は一次酸化でSi基板は凹側へ大き
く反ってしまうため不適当である。従って、−次酸化と
して有効な範囲は(2)の領域となる。本実施例は多孔
質Siの密度がL 、 Og / cm’の場合であり
多孔質Siの密度を変化させたとき、おのおのの領域の
境界が変化することは言うまでもない。次に、多孔質S
i酸化物107が流動を起こすような酸化条件、例えば
、常圧ウェット酸素雰囲気中でl050℃、50分から
100分程度の酸化を行う。この酸化を二次酸化と呼ぶ
。二次酸化により多孔質Si酸化物は緻密化し、その膜
質は熱酸化膜とほぼ等しくなる。In the region (1), the oxidation temperature is 950°C or less, and the porous S
i Oxide film does not cause flow. Therefore, the region <<(1) is inappropriate because the 81 substrate contains dislocations. (3
) is a temperature range in which the porous Si oxide film begins to flow, but since the oxidation time is short, the amount of flow is small and the amount of dislocations generated is also small. Therefore, the oxidation conditions are still inappropriate. Region (4) is inappropriate because the Si substrate is largely warped toward the concave side due to primary oxidation. Therefore, the effective range for -second oxidation is the region (2). In this example, the density of porous Si is L, Og/cm', and it goes without saying that when the density of porous Si is changed, the boundaries of each region change. Next, porous S
Oxidation is performed under oxidation conditions that cause the i-oxide 107 to flow, for example, in a normal pressure wet oxygen atmosphere at 1050° C. for about 50 to 100 minutes. This oxidation is called secondary oxidation. The porous Si oxide becomes dense due to the secondary oxidation, and its film quality becomes almost the same as that of a thermal oxide film.
第4図は、二次酸化時間と二次酸化によるSi基板10
1の反りの関係を示す。図において、Δは一次酸化の温
度が1000°C1時間が100分、Oは1000℃、
200分、Xは900℃、100分である。Δ、Oにお
いては、−次酸化で入った転位が応力を吸収するため反
りの変化は二次酸化時間に依存せず一定となる。−吹酸
化時間が長いほどSi基板lO1に発生する転位量は多
い。その結果、二次酸化時の応力緩和量も大きく、二次
酸化後の反りの変化は小さくなる。すなわち、Δよりも
0の方が一次酸化時間が長いので反りは小さい。図の中
に一次酸化条件が900℃、100分の場合のSi基板
101の反りの変化も示した。この酸化条件は第3図に
示す(1)の領域であり多孔質Si酸化物107の流動
が起きないためSi基板101に転位はほとんど発生し
ない。次の二次酸化でSi基板lotに転位が入るため
、反りの変化は第2図とほぼ等しくなり反りは増大して
いる。本実施例では多孔質Si層の酸化は常圧酸化で行
ったが高圧酸化および希釈酸化にも適用できることは言
うまでもない。FIG. 4 shows the secondary oxidation time and the Si substrate 10 due to secondary oxidation.
1 shows the warpage relationship. In the figure, Δ is the primary oxidation temperature of 1000°C 1 hour 100 minutes, O is 1000°C,
200 minutes, X is 900°C, 100 minutes. At Δ and O, the dislocations introduced during the -secondary oxidation absorb stress, so the change in warpage remains constant regardless of the time of the second oxidation. - The longer the blowing oxidation time, the more dislocations occur in the Si substrate lO1. As a result, the amount of stress relaxation during secondary oxidation is also large, and the change in warpage after secondary oxidation is small. That is, since the primary oxidation time is longer for 0 than for Δ, the warpage is smaller. The figure also shows the change in warpage of the Si substrate 101 when the primary oxidation conditions were 900° C. for 100 minutes. This oxidation condition is in the region (1) shown in FIG. 3, and since the porous Si oxide 107 does not flow, almost no dislocations occur in the Si substrate 101. Since dislocations are introduced into the Si substrate lot in the subsequent secondary oxidation, the change in warpage is almost the same as in FIG. 2, and the warpage is increasing. In this example, the porous Si layer was oxidized by normal pressure oxidation, but it goes without saying that high pressure oxidation and diluted oxidation can also be applied.
その後、温めた燐酸等で窒化シリコン膜102を除去し
、露出した単結晶Si層105上に素子を作製する。Thereafter, the silicon nitride film 102 is removed using warmed phosphoric acid or the like, and a device is fabricated on the exposed single crystal Si layer 105.
なお、上記実施例では、酸化することによって半導体基
板に転位を発生させたが、他の方法により転位を発生さ
せてもよいことはいうまでもない。In the above embodiment, dislocations were generated in the semiconductor substrate by oxidation, but it goes without saying that other methods may be used to generate dislocations.
また、上記実施例では、多孔質Si層の酸化はウェット
酸化により行ったが、ドライ酸化により行ってもよい。Furthermore, in the above embodiments, the porous Si layer was oxidized by wet oxidation, but dry oxidation may also be used.
以上説明したように、本発明は、半導体基板に転位を発
生させた後、多孔質Si酸化物が流動する酸化条件で多
孔質Si層を酸化することにより、半導体基板の反りを
大幅に減少し、かつ多孔質Si酸化物のエッチレートを
熱酸化膜のエッチレートとほぼ同じにすることができ、
さらにSi基板の反りの低減によって多孔質Si酸化物
で分離された単結晶半導体層の結晶性が向上する、等の
顕著な効果を得ることができる。As explained above, the present invention significantly reduces warpage of the semiconductor substrate by generating dislocations in the semiconductor substrate and then oxidizing the porous Si layer under oxidizing conditions in which porous Si oxide flows. , and the etch rate of the porous Si oxide can be made almost the same as the etch rate of the thermal oxide film,
Furthermore, remarkable effects such as improved crystallinity of single crystal semiconductor layers separated by porous Si oxide can be obtained by reducing warpage of the Si substrate.
第1図(a)〜(f)は多孔質Si酸化物によって単結
晶Si島がSi基板から絶縁分離された摺造を有する本
発明の集積回路基板の製造方法の一実施例の工程を示す
図、第2図は多孔質Si層を1050℃で酸化した時の
酸化時間とSi基板の反りの関係を示す図、第3図は常
圧ウェット酸素雰囲気中で一次酸化を行った場合の温度
と時間の関係を示す図、第4図は二次酸化時間と二次酸
化によるSi基板の反りの関係を示す図である。
101・・・p型Si基板 102・・・耐酸化性
膜103・・・レジスト 104・・・p型窩
濃度Si領域lO5・・・分離されたn型Si層
106・・・多孔質Si層 107・・・多孔質S
i酸化物才2図
JP3図
一;欠酸イ巴月り度 (°C)FIGS. 1(a) to 1(f) show steps of an embodiment of the method for manufacturing an integrated circuit board of the present invention having a sliding structure in which single-crystal Si islands are insulated and separated from a Si substrate by porous Si oxide. Figure 2 shows the relationship between oxidation time and warpage of the Si substrate when a porous Si layer is oxidized at 1050°C, and Figure 3 shows the temperature when primary oxidation is performed in a normal pressure wet oxygen atmosphere. FIG. 4 is a diagram showing the relationship between secondary oxidation time and warpage of the Si substrate due to secondary oxidation. DESCRIPTION OF SYMBOLS 101... P-type Si substrate 102... Oxidation-resistant film 103... Resist 104... P-type cavity concentration Si region 1O5... Separated n-type Si layer 106... Porous Si layer 107...Porous S
i Oxide 2 Figure JP3 Figure 1; Oxygen deficiency (°C)
Claims (1)
i層を形成し、該多孔質Si層を酸化して多孔質Si酸
化物を形成し、該多孔質Si酸化物によって上記単結晶
半導体領域の側面および底面の一部または全部を分離す
る工程を含む半導体集積回路基板の製造方法において、
上記半導体基板に転位を発生させた後、上記多孔質Si
酸化物が流動しうる酸化条件で上記多孔質Si層を酸化
することを特徴とする半導体集積回路基板の製造方法。Island-shaped single crystal semiconductor regions and porous S on a semiconductor substrate
forming an i-layer, oxidizing the porous Si layer to form a porous Si oxide, and separating part or all of the side and bottom surfaces of the single crystal semiconductor region by the porous Si oxide; In a method of manufacturing a semiconductor integrated circuit board including,
After generating dislocations in the semiconductor substrate, the porous Si
A method for manufacturing a semiconductor integrated circuit board, characterized in that the porous Si layer is oxidized under oxidizing conditions that allow the oxide to flow.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP12437985A JPS61283131A (en) | 1985-06-10 | 1985-06-10 | Manufacture of semiconductor integrated circuit substrate |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP12437985A JPS61283131A (en) | 1985-06-10 | 1985-06-10 | Manufacture of semiconductor integrated circuit substrate |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS61283131A true JPS61283131A (en) | 1986-12-13 |
Family
ID=14883947
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP12437985A Pending JPS61283131A (en) | 1985-06-10 | 1985-06-10 | Manufacture of semiconductor integrated circuit substrate |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS61283131A (en) |
Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS4991586A (en) * | 1972-12-29 | 1974-09-02 | ||
JPS5354973A (en) * | 1976-10-29 | 1978-05-18 | Matsushita Electric Ind Co Ltd | Semiconductor device and its production |
-
1985
- 1985-06-10 JP JP12437985A patent/JPS61283131A/en active Pending
Patent Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS4991586A (en) * | 1972-12-29 | 1974-09-02 | ||
JPS5354973A (en) * | 1976-10-29 | 1978-05-18 | Matsushita Electric Ind Co Ltd | Semiconductor device and its production |
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