JPS6127639A - Formation of oxide film pattern of semiconductor element - Google Patents
Formation of oxide film pattern of semiconductor elementInfo
- Publication number
- JPS6127639A JPS6127639A JP9473085A JP9473085A JPS6127639A JP S6127639 A JPS6127639 A JP S6127639A JP 9473085 A JP9473085 A JP 9473085A JP 9473085 A JP9473085 A JP 9473085A JP S6127639 A JPS6127639 A JP S6127639A
- Authority
- JP
- Japan
- Prior art keywords
- oxide film
- oxidizing agent
- substrate
- film pattern
- temperature
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Formation Of Insulating Films (AREA)
Abstract
Description
【発明の詳細な説明】
本発明は半導体素子の酸化膜パターン形成方法に関する
。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for forming an oxide film pattern of a semiconductor device.
半導体素子の製造における、従来のウエノ・−プロセス
では、第1図aに示すように、シリコン基板の上に全面
、シリコン酸化膜2を形成し、その上部に感光性樹脂3
(以下、フォトレジストという。)を塗布し、第1図す
のフォトマスク4を乗せて露光、現像し、1i11[m
cのフォトレジスト・;ターン5を得る。次に、上記フ
ォトレジスしくターン6をエツチングマスクニジ、上記
シリコン酸化膜2を、例えば、弗酸系のエツチング液で
部分的にエツチングした後、上記フォトレジストノ<タ
ー76を除去し、目的とした、第1図dの配化膜パター
ン6を間接的に得る方法が用いられているしかしながら
、これらの方法では、次のような欠点がある。すなわち
、フォトエツチング工程が入るため、プロセスが複雑か
つ、長くなり、フォトエノチ工程において、異物による
ピンホール。In the conventional Ueno process for manufacturing semiconductor devices, as shown in FIG.
(hereinafter referred to as photoresist), placed the photomask 4 shown in Figure 1, exposed and developed, 1i11 [m
Obtain photoresist c; turn 5. Next, the photoresist pattern 76 is etched using an etching mask, and the silicon oxide film 2 is partially etched using, for example, a hydrofluoric acid-based etching solution, and the photoresist pattern 76 is removed. However, these methods have the following drawbacks. In other words, since a photoetching process is involved, the process becomes complicated and long, and pinholes caused by foreign matter occur during the photoetching process.
ハンドリングミス、装置による)きターンくずれ等のた
め、欠陥が犬きく、かつ又、半導体表面が、フォトレジ
スト、現像液、エツチング液等に接するため汚染されや
すく、マスク合せの精度、あるいは、被エツチング材料
のサイドエツチング等により、微細加工が難しい。Defects are likely to occur due to handling errors, chipping (due to equipment), etc. Furthermore, the semiconductor surface is easily contaminated because it comes into contact with photoresist, developer, etching solution, etc., and the accuracy of mask alignment or etching target is affected. Microfabrication is difficult due to side etching of the material.
本発明は、上記の従来力a、の欠点に鑑み発明されたも
ので、酸化剤を塗布した半導体基板上にエネルギービー
ムを走査しながら照射し、上記エネルギービームの照射
の有無に応じて、上記半導体基板表面の一部を選択的に
酸化し酸化膜パターンを形成することを特徴とした半導
体素子の酸化膜パターン形成方法である。The present invention was invented in view of the above-mentioned drawbacks of the conventional method a, in which an energy beam is scanned and irradiated onto a semiconductor substrate coated with an oxidizing agent, and depending on whether or not the energy beam is irradiated, the This is a method for forming an oxide film pattern for a semiconductor element, characterized by selectively oxidizing a part of the surface of a semiconductor substrate to form an oxide film pattern.
本発明はフォトマスクやフォトレジストを用いず、従っ
て、従来からのフォトエッチング工程ヲ全く用いず、直
接半導体基板上に任意のパターンを高能率に形成する方
法である。The present invention is a method for forming an arbitrary pattern directly on a semiconductor substrate with high efficiency, without using a photomask or photoresist, and therefore without using any conventional photoetching process.
以下、エネルギービームとして電子ビームを用いた実施
例により図面を用いて本発明を説明する。The present invention will be described below with reference to the drawings and an example in which an electron beam is used as the energy beam.
第2図に示すように、シリコン基板11を、内部ヒータ
ー12であらかじめある一定の温度まで昇温しておき、
ブランキングユニット13を通過してくる電子ビーム1
4を、走査コイル15を用いて走査し、上記シリコン基
板11表面にほぼ垂直に、目的としたパターン通りにエ
ネルギー照射することにより、パターン部の反応を進め
、゛上記シリコン基板111−に、直接、任意の酸化膜
パターンを形成できる。As shown in FIG. 2, the silicon substrate 11 is heated to a certain temperature in advance by an internal heater 12,
Electron beam 1 passing through blanking unit 13
4 is scanned using the scanning coil 15 and irradiated with energy almost perpendicularly to the surface of the silicon substrate 11 according to the intended pattern, thereby advancing the reaction of the patterned portion. , any oxide film pattern can be formed.
さらに、具体的実施例を説明すると、第3図の方法は、
シリコン基板31表面に酸化剤ペースト、たとえば二酸
化鉛(Pb02)33を数十ミクロン塗布し、200〜
250’Cまで昇温しておき、電子ビーム34を選択的
に照射し、照射された部分の酸化剤33とシリコン基板
31を(2PbO2+5i−2PbO+5IO2)の如
く反応せしめ、さらに未反応酸化剤を除去してシリコン
基板31上に選択的にシリコン酸化膜パターン32を得
るものである。Furthermore, to explain a specific example, the method shown in FIG.
An oxidizing agent paste, for example, lead dioxide (Pb02) 33, is applied to the surface of the silicon substrate 31 to a thickness of several tens of microns, and
The temperature is raised to 250'C, the electron beam 34 is selectively irradiated, the oxidizing agent 33 in the irradiated area reacts with the silicon substrate 31 as (2PbO2+5i-2PbO+5IO2), and unreacted oxidizing agent is removed. Then, a silicon oxide film pattern 32 is selectively formed on a silicon substrate 31.
この実施例の方法は装置内を真空にしておいても、酸化
反応を生じせしめることが出来、電子ビーム34の効率
が良く、またビームがしぼり易くなるため微細パターン
を得たい様な場合に特に有効である。The method of this embodiment allows the oxidation reaction to occur even if the inside of the apparatus is kept in a vacuum, and the efficiency of the electron beam 34 is high.The method of this embodiment also makes it easier to narrow down the beam, so it is particularly useful when obtaining a fine pattern. It is valid.
さらにまた、基板31表面がある程度昇温されているた
め、電子ビームのエネルギー量は、その分、昇温してい
ない場合に比べて少くできるので、ビームをより細く絞
ることができ、近年進歩しているLSI製造用に用いる
と微細パターンの形成に大きな効果がある。Furthermore, since the surface of the substrate 31 has been heated to a certain extent, the energy amount of the electron beam can be reduced by that amount compared to the case where the temperature has not been increased. When used for LSI manufacturing, it has a great effect on the formation of fine patterns.
一方、エネルギー強度を同じにすれば、照射“時間を大
幅に短縮できるので、量産効果大なるものである。On the other hand, if the energy intensity is kept the same, the irradiation time can be significantly shortened, which is highly effective for mass production.
なお、この場合、酸化剤塗膜中にドーパントとなる不純
物、例えば、P)i3.P2O6等を微量含有させてお
けば局部的に不純物拡散が行なえることも明らかである
。さらに、また、選択酸化膜をエツチングすることによ
り基板を選択的にエツチングすることも可能である。In this case, an impurity serving as a dopant, such as P)i3. It is also clear that if a small amount of P2O6 or the like is contained, impurity diffusion can be carried out locally. Furthermore, it is also possible to selectively etch the substrate by etching the selective oxide film.
以上の説明より明らかな通り、本発明は、従来のウェハ
ープロセスに比して、大巾に工程の短縮ができるし、フ
ォトマスクもいらないし、工程短縮による薬品処理が少
なく、従ってシリコン基板の汚染も少なくなり、微細加
工が容易となり、さらに、シリコン基板全体を、100
0℃以上に昇温しないので、シリコン基板表面での欠陥
が発生しないし、さらに直接半導体基板を酸化できるた
め、非常に平坦な酸化膜パターンが得られるの°で、V
LSI製造における微細パターン形成が容易となるなど
の利点を有する。なお、本実施例では、電子ビームを用
いた場合を示したが、電子ビームに限定されるものでは
なく、例えば、レーザービーム、陽インビーム等、集光
して局所的にエネルギーを与えることができる。エネル
ギービームであれば、どれを用いても同じ効果が得られ
る。As is clear from the above explanation, the present invention can significantly shorten the process compared to the conventional wafer process, does not require a photomask, and requires less chemical treatment due to the shortened process, resulting in contamination of the silicon substrate. This makes microfabrication easier, and furthermore, the entire silicon substrate can be
Since the temperature does not rise above 0°C, defects do not occur on the silicon substrate surface, and since the semiconductor substrate can be directly oxidized, a very flat oxide film pattern can be obtained.
It has advantages such as facilitating the formation of fine patterns in LSI manufacturing. Although this example shows the case where an electron beam is used, it is not limited to the electron beam. For example, it is possible to use a laser beam, positive beam, etc., which can be focused to locally give energy. can. The same effect can be achieved no matter which energy beam you use.
第1図a〜dは従来のフォトエツチング工程の説明図、
第2図は本発明に用いる電子ビーム照射2図の入部の拡
大図である。
31・・・・・・7リコン基板、34・・・・・・電子
ビーム、32・・・・・・シリコン酸化膜パターン。′
代理人の氏名 弁理士 中 尾 敏 男 ほか1名第1
図
第2図
第3図Figures 1a to 1d are explanatory diagrams of the conventional photoetching process;
FIG. 2 is an enlarged view of the entrance of the electron beam irradiation diagram 2 used in the present invention. 31...7 recon board, 34...electron beam, 32...silicon oxide film pattern. ′
Name of agent: Patent attorney Toshio Nakao and 1 other person No. 1
Figure 2 Figure 3
Claims (3)
酸化剤を塗布した半導体基板表面をほぼ垂直な方向より
エネルギービームで選択的に照射し、上記エネルギービ
ームの照射有無に応じて、上記半導体基板表面の一部を
選択的に酸化する工程を有することを特徴とした半導体
素子の酸化膜パターン形成方法。(1) A step of applying an oxidizing agent to the surface of the semiconductor substrate, selectively irradiating the surface of the semiconductor substrate coated with the oxidizing agent with an energy beam from a substantially perpendicular direction, and depending on whether or not the energy beam is irradiated, 1. A method for forming an oxide film pattern for a semiconductor element, comprising a step of selectively oxidizing a part of the surface of a semiconductor substrate.
め所定の温度に加熱しておくことを特徴とした特許請求
の範囲第1項記載の半導体素子の酸化膜パターン形成方
法。(2) A method for forming an oxide film pattern on a semiconductor element according to claim 1, wherein the semiconductor substrate is heated to a predetermined temperature in advance during energy beam irradiation.
を特徴とした特許請求の範囲第1項記載の半導体素子の
酸化膜パターン形成方法。(3) A method for forming an oxide film pattern on a semiconductor device according to claim 1, characterized in that an electron beam is used as the energy beam.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP9473085A JPS6127639A (en) | 1985-05-02 | 1985-05-02 | Formation of oxide film pattern of semiconductor element |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP9473085A JPS6127639A (en) | 1985-05-02 | 1985-05-02 | Formation of oxide film pattern of semiconductor element |
Related Parent Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP4507376A Division JPS52128065A (en) | 1976-04-20 | 1976-04-20 | Pattern formation of semiconductor element |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS6127639A true JPS6127639A (en) | 1986-02-07 |
JPS6129139B2 JPS6129139B2 (en) | 1986-07-04 |
Family
ID=14118229
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP9473085A Granted JPS6127639A (en) | 1985-05-02 | 1985-05-02 | Formation of oxide film pattern of semiconductor element |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS6127639A (en) |
-
1985
- 1985-05-02 JP JP9473085A patent/JPS6127639A/en active Granted
Also Published As
Publication number | Publication date |
---|---|
JPS6129139B2 (en) | 1986-07-04 |
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