JPS61276374A - Thin film transistor device and manufacture thereof - Google Patents
Thin film transistor device and manufacture thereofInfo
- Publication number
- JPS61276374A JPS61276374A JP60118520A JP11852085A JPS61276374A JP S61276374 A JPS61276374 A JP S61276374A JP 60118520 A JP60118520 A JP 60118520A JP 11852085 A JP11852085 A JP 11852085A JP S61276374 A JPS61276374 A JP S61276374A
- Authority
- JP
- Japan
- Prior art keywords
- electrode
- conductive film
- thin film
- film
- specific
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000010409 thin film Substances 0.000 title claims abstract description 42
- 238000004519 manufacturing process Methods 0.000 title claims description 14
- 239000010408 film Substances 0.000 claims abstract description 122
- 239000004065 semiconductor Substances 0.000 claims abstract description 34
- 239000000758 substrate Substances 0.000 claims abstract description 14
- 238000000034 method Methods 0.000 claims abstract description 7
- 238000000151 deposition Methods 0.000 claims description 4
- 238000009413 insulation Methods 0.000 abstract description 4
- 230000000873 masking effect Effects 0.000 abstract 2
- 238000010276 construction Methods 0.000 abstract 1
- 230000003247 decreasing effect Effects 0.000 abstract 1
- 229910052751 metal Inorganic materials 0.000 description 8
- 239000002184 metal Substances 0.000 description 8
- 239000004020 conductor Substances 0.000 description 5
- 238000005530 etching Methods 0.000 description 4
- 239000004973 liquid crystal related substance Substances 0.000 description 4
- 229910052782 aluminium Inorganic materials 0.000 description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 2
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 1
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- 101100214488 Solanum lycopersicum TFT2 gene Proteins 0.000 description 1
- 210000001015 abdomen Anatomy 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 229910052796 boron Inorganic materials 0.000 description 1
- 239000003990 capacitor Substances 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 239000010931 gold Substances 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 239000011159 matrix material Substances 0.000 description 1
- 230000003287 optical effect Effects 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- 239000010453 quartz Substances 0.000 description 1
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N silicon dioxide Inorganic materials O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
- 238000003860 storage Methods 0.000 description 1
- OFIYHXOOOISSDN-UHFFFAOYSA-N tellanylidenegallium Chemical compound [Te]=[Ga] OFIYHXOOOISSDN-UHFFFAOYSA-N 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
Landscapes
- Liquid Crystal (AREA)
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
Abstract
Description
【発明の詳細な説明】
〈産業上の利用分野〉
本発明は、非晶質シリコンＣａ−８４）や多結晶シリコ
ン（Ｐ−８ｚ）等の半導体薄ａｔ用いた絶縁ゲート型の
薄膜トランジスタ（ＴＦ’Ｔ）装！とその製造方法に関
する。Detailed Description of the Invention <Industrial Application Field> The present invention relates to an insulated gate thin film transistor (TF' T) Dressing! and its manufacturing method.
〈発明の概要〉
Ｐｉｆｉ基板上に第１導電膜によるゲート電極と特定電
極（例えば画素電極〕を形成後、事次ゲート絶縁膜、高
抵抗半導体薄膜、低抵抗半導体薄膜を含む第２導電膜を
堆積し、次に第２導電膜、高抵抗半導体薄膜、ゲート絶
縁膜をほぼ同一形状の島状領域として残す。その際、前
記特定便域とこの島状領域に重畳部分を設けておく。第
８導電膜を堆積後選択工゛ツチしさらに露出した第２導
電ａｔ選択除去して、ソース電極及びドレイン電極を形
成すると共に、前記重畳部分の側面を通して第８導電膜
を用いソース電極またはドレイン電極と特定電極との間
の配線を行う。以上によって形成されたτＩＦＴは、製
造工程が簡単でかっ、外部取り出し電極を第８導電腹で
行なえる利点をもつ。<Summary of the Invention> After forming a gate electrode and a specific electrode (for example, a pixel electrode) using a first conductive film on a Pifi substrate, a second conductive film including a gate insulating film, a high resistance semiconductor thin film, and a low resistance semiconductor thin film is formed. The second conductive film, the high-resistance semiconductor thin film, and the gate insulating film are deposited and then left as an island-like region having approximately the same shape.At this time, an overlapping portion is provided between the specific region and this island-like region. After depositing an eighth conductive film, selectively remove the exposed second conductive film to form a source electrode and a drain electrode, and use an eighth conductive film to pass through the side surface of the overlapping portion to form a source electrode or a drain electrode. The τIFT formed as described above has the advantage that the manufacturing process is simple and that the external lead electrode can be formed at the eighth conductive node.
く従来の技術〉
ＴＰＴは液晶表示装置の画素スイッチ等に用いられてい
る。液晶表示装置の大面積化や、低コスト化のためＴＰ
Ｔの製造工程は簡単化されつつあるが、問題点も多い。BACKGROUND ART TPT is used in pixel switches of liquid crystal display devices and the like. TP to increase the area of liquid crystal display devices and reduce costs
Although the T manufacturing process is becoming simpler, there are still many problems.
第２図には液晶我示装置用ＴＦＴ基板の単位画素構造の
従来例を示した。この例においてＴＰＴは絶縁基板１上
に設けられ、ゲート電極２、ゲート絶縁膜８、高抵抗半
導体薄Ｊ［Ｉ４、低抵抗半導体薄ｇを含む第２導電膜１
５ 、１６及び第８導電膜５，２６から成るドレイン電
極５とソース電極６から形成されている。特定電極７で
ある画素電極はゲート電極２と同時に設けられるが、ゲ
ート絶縁膜３に開孔したコンタクトホール１３ｔ−介し
て第８導電膜あでソース電極６と接続されている。この
構造例は最低４回のマスク工程を必要とし、必ずしも少
ない工程数ではない。FIG. 2 shows a conventional example of a unit pixel structure of a TFT substrate for a liquid crystal display device. In this example, the TPT is provided on an insulating substrate 1, and a second conductive film 1 including a gate electrode 2, a gate insulating film 8, a high resistance semiconductor thin film J[I4, and a low resistance semiconductor thin film 1]
A drain electrode 5 and a source electrode 6 are formed of conductive films 5 and 16 and an eighth conductive film 5 and 26. The pixel electrode, which is the specific electrode 7, is provided at the same time as the gate electrode 2, and is connected to the source electrode 6 through the eighth conductive film through a contact hole 13t formed in the gate insulating film 3. This example structure requires at least four mask steps, which is not necessarily a small number of steps.
一方、第８図に示した単位画素の他の従来構造例では、
第２図の例における第８導電膜で特定電極（画素電極）
７も形成したものであり、８回のマスク工程で製作でき
る。しかし、一般的に画素電極はＩＴＯ等の透明導電ｇ
ｔ−用いるので、ドレイン電極用第３導電膜１５も同等
を−になる。そのためドレイン配線の抵抗を低くできな
い問題がある。さらに、外部取り出し電極も透明導電膜
になるのでワイアポンディングがむすがしい問題もある
。また、特定電極７が他のＴＰＴのゲート電極であると
き即ち、Ｔ１Ｆ’！’論理集積回路等には、本工程例は
適用できない欠点もある。On the other hand, in another conventional structure example of the unit pixel shown in FIG.
A specific electrode (pixel electrode) in the eighth conductive film in the example of FIG.
7 is also formed, and can be manufactured by eight mask steps. However, generally the pixel electrode is made of transparent conductive material such as ITO.
Since t- is used, the third conductive film 15 for the drain electrode also becomes -. Therefore, there is a problem that the resistance of the drain wiring cannot be lowered. Furthermore, since the external lead-out electrode is also a transparent conductive film, wire bonding is difficult. Further, when the specific electrode 7 is the gate electrode of another TPT, that is, T1F'! 'Logic integrated circuits and the like have some drawbacks that this process example cannot be applied to.
〈発明が解決しようとする問題点〉
本発明は叙上の問題点であるα）畏造工程が多い（第２
図］、■他ＴＰＴとの相互配線がしにくい（第８図］、
■）ソース、ドレイン配線を低抵抗にできない（第８図
）等を解決すべくなされた１本発明の目的は、製造工程
が少な（、ＴＦＴ同志の相互配線がしやすく、配線抵抗
を低減化でき、るＴＦＴの構造及びその製造方法を提供
することである。<Problems to be solved by the invention> The present invention solves the above-mentioned problems α) Many manufacturing steps (Second)
Figure], ■Difficult to interconnect with other TPTs (Figure 8),
■) The purpose of the present invention was to solve the problem of not being able to make the source and drain wiring low in resistance (Figure 8). It is an object of the present invention to provide a TFT structure and a method for manufacturing the same.
く問題点を解決するための手段〉
本発明によるＴＩＩ′Ｔ装置は、絶縁基板上の第１導電
膜によるゲート電極と特定電極と、順次形成されたゲー
ト絶縁膜、高抵抗半導体薄膜腹と、前１半導体薄膜上に
接する低抵抗半導体薄膜を含む第２導電良及びその上の
第３導電膜によるソース電極とドレイン電極とから成る
。少なく兵馬抵抗半導体薄膜とゲート絶Ｒ膜がほぼ同一
形状の島状領域として形成されかつ島状領域は特定電極
と重畳部を有する。ソースまたはドレイン電極と特定電
極の間の配線は、第８導電膜により重畳部分の島状頭載
上及び側面を通してなされている。特定電極には画素電
極または他ＴＩＦＴのゲート電極が相当する。Means for Solving the Problems> The TII'T device according to the present invention includes a gate electrode and a specific electrode made of a first conductive film on an insulating substrate, a gate insulating film, a high-resistance semiconductor thin film belly formed in sequence, It consists of a second conductive film including a low resistance semiconductor thin film in contact with the first semiconductor thin film, and a source electrode and a drain electrode formed of a third conductive film thereon. At least the Terracotta resistance semiconductor thin film and the gate insulation film are formed as island-like regions having substantially the same shape, and the island-like regions have overlapping portions with the specific electrodes. Wiring between the source or drain electrode and the specific electrode is provided through the island-shaped head and side surface of the overlapping portion using the eighth conductive film. The specific electrode corresponds to a pixel electrode or a gate electrode of another TIFT.
〈作用〉
上記の様に本発明によれば、特定電極上のゲート絶縁膜
の開孔は、島状領域を形成することによってなされるの
で、第２図の従来例よりマスク工程は１回減少でき、最
低８回のマスク工程でτＦＴ装置が製作できる。前記重
畳部分を設けることにより、第８導電膜による特定電極
への配線の大部分は第２導電渓と冗長配線できる。ま九
、島状領域形成時には基板表面が損傷を受けやすいが、
この重畳部分により第８導電属の配線が損傷部分全通ら
なくても済む利点がある。<Operation> As described above, according to the present invention, holes in the gate insulating film on specific electrodes are formed by forming island-like regions, so the number of mask steps is reduced by one compared to the conventional example shown in FIG. Therefore, a τFT device can be manufactured with at least 8 mask steps. By providing the overlapping portion, most of the wiring to the specific electrode by the eighth conductive film can be redundant wiring with the second conductive valley. Nine, the substrate surface is easily damaged when forming island-like regions;
This overlapping portion has the advantage that the eighth conductive metal wiring does not have to pass through the entire damaged area.
画素電極等の材料に制限のある特定電極には第１導電膜
を用いるため、第８導電膜はソース、ドレイン電極だけ
でなく配線や外部取り出し電極にも用いられ、゛抵抗低
減やボンディングが容易になる。Since the first conductive film is used for specific electrodes with limited materials such as pixel electrodes, the eighth conductive film is used not only for source and drain electrodes but also for wiring and external electrodes, making it easy to reduce resistance and bond. become.
〈実施例〉
α、実施例１ ＴＦＴ断面 （第１図〕第１図には本発
明によるＴＰＴの断面図を示す。Ｔ１では、ガラス等の
絶縁基板１上に設けられた第１導電膜によるゲート電極
２、特定電極７と、ゲート電極２上に設けたゲート絶縁
膜８、高抵抗半導体薄膜４と、高抵抗半導体薄膜４の表
面に接する低抵抗半導体薄膜１５ 、１６ （第２導電
膜〕及び第８導電膜５１局から成るドレイン電極６とソ
ース電極６とから形成されている。少なく兵馬抵抗半導
体薄膜４とゲート絶縁膜８は、特定電極７と重畳部分２
０を有する島状領域１０にほぼ同一形状に形成され、ソ
ース電極６と特定電極７は第８導電膜あにより重畳部分
２Ｏｆ：通って配線接続されている。<Example> α, Example 1 TFT cross section (Fig. 1) Fig. 1 shows a cross-sectional view of the TPT according to the present invention. Gate electrode 2, specific electrode 7, gate insulating film 8 provided on gate electrode 2, high resistance semiconductor thin film 4, and low resistance semiconductor thin films 15 and 16 in contact with the surface of high resistance semiconductor thin film 4 (second conductive film). and an eighth conductive film 51. At least the Terracotta resistance semiconductor thin film 4 and the gate insulating film 8 are formed of the specific electrode 7 and the overlapping portion 2.
The source electrode 6 and the specific electrode 7 are connected by wiring through the overlapping portion 2Of: of the eighth conductive film.
特定電極７が画素電極のときには工ＴＯ等の透明導電膜
を第１導電膜として用いる。後述の様に、第１導電膜は
透明導電膜と金属等不透明導電膜ノ多層膜でもよい。ゲ
ート絶縁膜８は８ｓＮ２＋膜やＢｉｂｒ８膜等が、高抵
抗半導体薄膜４には、α−日４：ＩＩ膜、α−日ｊ：Ｉ
Ｆ膜、Ｐ−日ｉ膜等が、第２導電［１５，１６にはリン
やボロンを県別した前記の半導体膜が用いられる。第２
導電膜１５ 、１６は低抵抗半導体膜と金属の多層膜ヲ
選ぶこともできる。第８導電膜５，２６は金属膜で通常
ムＬ、Ａ藝、Ｎｉ等が用いられる。When the specific electrode 7 is a pixel electrode, a transparent conductive film such as TO is used as the first conductive film. As described later, the first conductive film may be a multilayer film of a transparent conductive film and an opaque conductive film such as a metal. The gate insulating film 8 is made of 8sN2+ film, Bibr8 film, etc., and the high resistance semiconductor thin film 4 is made of α-day 4:II film, α-dayj:I film, etc.
F film, P-day i film, etc. are used for the second conductivity [15, 16] The above-mentioned semiconductor film containing phosphorus or boron is used. Second
The conductive films 15 and 16 may be a multilayer film of a low resistance semiconductor film and a metal. The eighth conductive films 5 and 26 are metal films, and are usually made of aluminum, aluminum, Ni, or the like.
この例では、特に重畳部分ｍ側の第２導電膜１６は島状
領域１０とほぼ同じ端部を有しているが、第８導電膜％
の下部に同じ形状に作ることもできる。In this example, in particular, the second conductive film 16 on the side of the overlapping portion m has almost the same end as the island region 10, but the eighth conductive film 16
It can also be made in the same shape at the bottom of the .
ｂ、実施例２ 単位画素部 （第４図ン第４図には液晶
表示用ＴＰＴ基板の単位画素を例にとった本発明の製造
工程例を示す、第４図Ｇ）はガラス、石英等の絶縁基板
１上に工’Ｉ’ｏ、５ｆｓＯ３等の透明な第１導電膜で
ゲート電極２、特定電ＩＭ（画素電極）７を形成した断
面である。第４図の）は、ゲート絶縁膜３、高抵抗半導
体薄膜４、第２導電腹８を連続して堆積した状態を示す
♂例えハ、ケ−）絶縁膜８に８４Ｎｚ［’ｊ０．２μ、
半導体薄膜４にα−ｓ＜：ａ膜ｔ−５００ム、第２導電
Ｈ８に外＋、−ｓ６：ｎ凪を１００Ａ、連続してガラス
−ｔｏ’ｌＤや光ＯＶＤ等で堆積する。第４図り嫁、選
択エッチにより第１導電膜８、半導体薄膜４、ゲート絶
縁膜８から成る島状領域１０を形成したもので、島状領
域１０と特定電極７は重畳部分２０ｔ−有している。選
択エッチは、ドライエッチ、ウェットエッチ等金用い、
島状領域７の側面が少なく共逆テーバ状にならない様、
望ましくはなだらかになる種条件を選ぶ。第４図のは１
、Ａｔ、Ａｔ７’ｕｏ ＊”Ｌ／’ｒ等の金属（多層膜
〕である第８導電［２５，２６を堆積し、選択エッチし
てドレイン及びソース電極５．６を形成し、完成した断
面を示す。この際、第３導電膜の選択エッチ後露出した
第２導［ｆｆ８も選択除去し、ドレイン及びソース電極
５，６を第８導電股５．あど第２導電ｆｉ１５．１６の
２層で設けている。また、ソース電極６は重畳部分２０
ｔ−介して第８導′ｆＩＬ膜％で特定電極７と接続され
ている。b, Example 2 The unit pixel portion (Fig. 4 shows an example of the manufacturing process of the present invention taking a unit pixel of a TPT substrate for liquid crystal display as an example, Fig. 4G) is made of glass, quartz, etc. This is a cross section in which a gate electrode 2 and a specific electrode IM (pixel electrode) 7 are formed on an insulating substrate 1 using a transparent first conductive film such as I'O or 5fsO3. 4) shows a state in which a gate insulating film 3, a high-resistance semiconductor thin film 4, and a second conductive film 8 are successively deposited.
A film of α-s<:a film t-500m is deposited on the semiconductor thin film 4, and a film of 100A is deposited on the second conductive layer H8 by glass-to'ld or optical OVD. In the fourth step, an island-like region 10 consisting of the first conductive film 8, semiconductor thin film 4, and gate insulating film 8 is formed by selective etching, and the island-like region 10 and the specific electrode 7 have an overlapping portion 20t-. There is. Selective etching uses gold, such as dry etching and wet etching.
The side surfaces of the island-like region 7 are small so that they do not become inverted tapered.
Preferably, choose seed conditions that are gentle. Figure 4 is 1
, At, At7'uo *"L/'r, etc., are deposited to form the eighth conductor [25, 26], which is a metal (multilayer film), and selectively etched to form the drain and source electrodes 5.6. At this time, after selectively etching the third conductive film, the exposed second conductive film [ff8 is also selectively removed, and the drain and source electrodes 5 and 6 are formed into two layers of the eighth conductive layer 5, the second conductive film 15 and 16. In addition, the source electrode 6 is provided in the overlapping portion 20.
It is connected to the specific electrode 7 through the eighth conductor'fIL film %.
この単位画素をマトリクス状に配し九宍示装置において
、ゲート電極２の端部は第８導電、嗅と直接接触できる
ので、ゲートの外部取り出し電極も第３導電膜を用いる
ことができ、ボンディング等が容易である。In a display device in which these unit pixels are arranged in a matrix, the end of the gate electrode 2 can be directly contacted with the eighth conductive layer, so the third conductive film can also be used as the external electrode of the gate, and bonding etc. is easy.
Ｃ０実施例８ 単位画素部 （第５図〕第５図では本発
明の製造工程の他の実施例を説明する。第５図６）は、
第１導電膜によるゲート電極２、特定電極７を形成後、
ゲート絶縁膜８、高抵抗半導体薄膜４、第２導電農８を
堆積した状態である。ここで第１導電膜は、透明導電膜
１２ 、１７と金属等の不透明導電膜ｎ、２７の多層膜
が用いられ、第２導電膜８には例えばル＋低抵抗半導体
薄膜１８と金属膜四の多層ａｔ用いている。第５図＠）
中には同時に他行のゲート電極配線１０２が透明導電膜
１１２と不透明導電膜１２２の多層で設けた例を示して
いる。第５図Ｃｂ）では、ゲート電極２上に島状領域１
０ヲ他行のゲート電極配線１０２上にも同様な島状領域
２１０を形成した状態を示す。各島状領域１０ 、２１
０は特定電極７と重畳部分を有している。次に第８導電
腹を堆積後、選択エッチし、さらに露出した嬉２導電膜
８及び特定電極７の不透明導電、嘆２７ｔ−除去して完
成した模様を第５図ω）に示した。この際、島状領域２
１０上にも特定電極７に接する第８導＠膜２２６ｔ−残
し、他行のゲート電極配線１０２との間に電荷保持容量
を形成している。C0 Example 8 Unit pixel section (Fig. 5) In Fig. 5, another example of the manufacturing process of the present invention will be explained. Fig. 5 6)
After forming the gate electrode 2 and specific electrode 7 using the first conductive film,
This is a state in which a gate insulating film 8, a high-resistance semiconductor thin film 4, and a second conductive film 8 are deposited. Here, the first conductive film is a multilayer film consisting of transparent conductive films 12 and 17 and opaque conductive films n and 27 made of metal, etc., and the second conductive film 8 is, for example, a metal film consisting of a low-resistance semiconductor thin film 18 and a metal film. Multi-layer AT is used. Figure 5 @)
An example is shown in which the gate electrode wirings 102 in other rows are provided with multiple layers of a transparent conductive film 112 and an opaque conductive film 122 at the same time. In FIG. 5Cb), an island region 1 is formed on the gate electrode 2.
0 shows a state in which a similar island region 210 is also formed on the gate electrode wiring 102 in the other row. Each island-like region 10, 21
0 has an overlapping portion with the specific electrode 7. Next, after depositing the eighth conductive layer, selective etching was performed, and the exposed conductive film 8 and the opaque conductive layer 27t of the specific electrode 7 were removed, and the completed pattern is shown in FIG. 5 ω). At this time, the island area 2
An eighth conductive film 226t is also left on the specific electrode 7 to form a charge storage capacitor between it and the gate electrode wiring 102 of the other row.
この例では、第１導電膜及び第２導電αを多層、嗅にす
ることにより配線やコンタクト抵抗の低減が図れる。In this example, wiring and contact resistance can be reduced by forming the first conductive film and the second conductive film in multiple layers.
ｄ、実施例４ ＴＦＴ接続部 （第６図）８６図には
、本発明を２つのＴＦ’Ｔの接続に適用した例を示し、
第６図ら）はその平面図、第６図（ｂ）は第６図６）の
Ａ−ＡＩ線に沿った断面図である。集積＠路の場合しば
しばソースまたはドレイン電極を他のＴＦ’ｌ’のゲー
ト電極に接続する場合があり、それを例として示した。d. Example 4 TFT connection part (Fig. 6) Fig. 86 shows an example in which the present invention is applied to the connection of two TF'Ts,
6) is a plan view thereof, and FIG. 6(b) is a sectional view taken along the line A-AI in FIG. 6(6). In the case of integrated circuits, the source or drain electrode is often connected to the gate electrode of another TF'l', and this is shown as an example.
’ｒｐ’ｒ１のソース電極６はＴＦＴ２のゲート電極１
０２に島状領域１０の重畳部分田の上及び側面を介して
第８導電戻がで接続されている。この例では特定電極が
他のゲート電極１０２に相当する。を九、ＴＦＴＩ及び
’Ｉ’ｌ！”１’２のドレイン電極５，１０５等の主電
極の延在部も島状領域１０ 、１１０上に形成した例も
同時に示した。この様にすることで島状領域１０゜１１
０形成時の露出基板損傷部を通らずに配線できる利点が
ある。The source electrode 6 of 'rp'r1 is the gate electrode 1 of TFT2
02 is connected to the eighth conductive return via the top and side surface of the overlapping field of the island region 10. In this example, the specific electrode corresponds to another gate electrode 102. Nine, TFTI and 'I'l! An example in which the extended portions of the main electrodes such as the drain electrodes 5 and 105 of 1'2 are also formed on the island-like regions 10 and 110 is also shown at the same time.
There is an advantage that wiring can be done without passing through the exposed damaged part of the substrate during 0 formation.
く効果〉
以上述べた如く、本発明によるＴＰＴ装置は最低８回の
マスク工程で製造でき、低コスト化が実現できる。配線
抵抗の低減や外部接続も容易になるため、特性の良いＴ
ＰＴ装置が信頼性高く得られる利点も有する。さらに、
本発明の製造方法によれば、ゲート絶縁膜、高抵抗半導
体薄膜、第２導１！膜を大気に触れさず′ことなく連続
して堆積できるので、小さなコンタクト抵抗で特性のそ
ろったＴＰＴ装置を容易に製造できる長所も有する。Effects> As described above, the TPT device according to the present invention can be manufactured with at least eight mask steps, and cost reduction can be realized. Since wiring resistance can be reduced and external connections can be easily made, T
Another advantage is that the PT device can be obtained with high reliability. moreover,
According to the manufacturing method of the present invention, the gate insulating film, the high resistance semiconductor thin film, the second conductor 1! Since the film can be deposited continuously without being exposed to the atmosphere, it also has the advantage that TPT devices with small contact resistance and uniform characteristics can be easily manufactured.
本発明を主にα−８ｉｔａｔ例に説明してきたが、Ｐ−
Ｂｉでも他の半導体薄膜にも適用できる。Although the present invention has been mainly explained using the α-8itat example,
It can be applied to Bi or other semiconductor thin films.
また半導体薄膜としてレーザ等ビーム了ニールしたもの
も用いられ、本発明の適用範囲は極めて広い。Furthermore, a semiconductor thin film that has been annealed with a laser beam or the like can also be used, and the scope of application of the present invention is extremely wide.
第１図は本発明による’Ｉ’ＸＦＴ断面図、第２図及び
第８図はそれぞれ従来のＴＦＴの断面図、第４図６）〜
（イ）は本発明による製造工程順に沿った断面図、第５
図（へ）〜（ｃ）は本発明の他の製造方法の工程順断面
図、第６図６）はＴＩＦＴの接続に本発明を適用した場
合の平面図、第６図の）は第６図６）のＡ−人１線に沿
った断面図である。
１０．基板 ２０．ゲート電極 ８１．ゲート絶縁膜
４０．・高抵抗半導体薄膜 ５ 、 、 ）’レイン電
極 ６０．ソース電極 ７０．特定電極 ８、１５ 、
１６ 、 、第２導を膜 ２５，２６．、第８導電膜１
０島状領域 １００重畳部分 以上智遣二経順に
沿つ斥単１Ｌ画素喧面図
第４図
第５図Figure 1 is a cross-sectional view of 'I'XFT according to the present invention, Figures 2 and 8 are cross-sectional views of conventional TFTs, and Figure 46
(a) is a sectional view along the manufacturing process order according to the present invention,
Figures (f) to (c) are step-by-step sectional views of another manufacturing method of the present invention, Figure 6) is a plan view when the present invention is applied to TIFT connection, and Figure 6) is a cross-sectional view of the process of another manufacturing method of the present invention. FIG. 6) is a sectional view taken along line A-Person 1 in FIG. 6). 10. Substrate 20. Gate electrode 81. gate insulation film
40.・High resistance semiconductor thin film 5, , )' rain electrode 60. Source electrode 70. Specific electrode 8, 15,
16., 2nd conductor film 25,26. , eighth conductive film 1
0 island-like area 100 overlapping parts Single 1L pixel surface diagram along the above order of wisdom and two meridians Figure 4 Figure 5
Claims (6)
によるゲート電極と、前記ゲート電極上に順次形成され
たゲート絶縁膜、高抵抗半導体薄膜と、前記半導体薄膜
上に設けられたソース電極とドレイン電極とから少なく
共成る薄膜トランジスタと前記第１導電膜による特定電
極とを少なく共含む装置において、前記ソース及びドレ
イン電極が前記高抵抗半導体薄膜に接する低抵抗半導体
薄膜を少なく共含む第２導電膜と該導電膜上の第８導電
膜より成り、前記ゲート絶縁膜及び高抵抗半導体薄膜が
ほぼ同一形状の島状領域として形成されると共に、前記
特定電極と前記島状領域に重畳部分を設け、前記ソース
電極もしくはドレイン電極と前記特定電極の間の配線は
前記第３導電膜により前記重畳部分の島状領域上及び側
面を通して形成されていることを特徴とする薄膜トラン
ジスタ装置。(1) an insulating substrate, a gate electrode formed of a first conductive film formed on the substrate, a gate insulating film sequentially formed on the gate electrode, a high-resistance semiconductor thin film, and a gate electrode formed on the semiconductor thin film; In the device, the thin film transistor includes at least a source electrode and a drain electrode, and a specific electrode made of the first conductive film, wherein the source and drain electrodes include at least a low resistance semiconductor thin film in contact with the high resistance semiconductor thin film. It consists of a second conductive film and an eighth conductive film on the conductive film, and the gate insulating film and the high-resistance semiconductor thin film are formed as island-like regions having approximately the same shape, and overlap the specific electrode and the island-like region. A thin film transistor device, wherein a wiring between the source electrode or the drain electrode and the specific electrode is formed by the third conductive film over an island-like region of the overlapping portion and through a side surface thereof.
含むことを特徴とする特許請求の範囲第１項記載の薄膜
トランジスタ装置。(2) The thin film transistor device according to claim 1, wherein at least a common portion of the first conductive film includes a transparent conductive film.
複数個配され、各画素電極に対応した前記薄膜トランジ
スタのソース電極と第３導電膜により接続されている特
許請求の範囲第１項または第２項記載の薄膜トランジス
タ装置。(3) One of the specific electrodes is a plurality of pixel electrodes arranged on the substrate and connected to the source electrode of the thin film transistor corresponding to each pixel electrode by a third conductive film. The thin film transistor device according to item 1 or 2.
ゲート電極であることを特徴とする特許請求の範囲第１
項から第３項までいずれか記載の薄膜トランジスタ装置
。(4) Claim 1, wherein the other type of specific electrode is a gate electrode of another thin film transistor.
3. The thin film transistor device according to any one of items 1 to 3.
極と該電極から離間した特定電極とを形成する第１工程
。 （ｂ）、ゲート絶縁膜、高抵抗半導体薄膜、低抵抗半導
体薄膜を少なく共含む第２導電膜を順次堆積する第２工
程。 （ｃ）、前記第２導電膜、高抵抗半導体薄膜、ゲート絶
縁膜を前記ゲート電極上に島状領域として形成すると共
に、前記島状領域に前記特定電極との重畳部分を設け他
の部分の特定電極を露出する第３工程。 （ｄ）、第３導電膜を堆積する第４工程。 （ｅ）、前記第３導電膜によりソース電極及びドレイン
電極の形状に選択エッチすると共に、ソース電極もしく
はドレイン電極の延在部が前記重畳部分の島状領域上及
び側面を通して特定電極に接触する様に形成する第５工
程。 （ｆ）、第５工程によつて露出した第２導電膜を選択除
去する第６工程。 より成る薄膜トランジスタの製造方法。(5) (a) A first step of forming a gate electrode made of a first conductive film and a specific electrode spaced apart from the gate electrode on the insulating substrate. (b) A second step of sequentially depositing a second conductive film including at least a gate insulating film, a high-resistance semiconductor thin film, and a low-resistance semiconductor thin film. (c) The second conductive film, the high-resistance semiconductor thin film, and the gate insulating film are formed as an island-like region on the gate electrode, and the island-like region is provided with a portion overlapping with the specific electrode and other portions are formed. Third step of exposing specific electrodes. (d), a fourth step of depositing a third conductive film. (e) The third conductive film is selectively etched into the shape of the source electrode and drain electrode, and the extended portion of the source electrode or drain electrode is brought into contact with the specific electrode through the island-like region and the side surface of the overlapping portion. The fifth step is to form. (f), a sixth step of selectively removing the second conductive film exposed in the fifth step; A method for manufacturing a thin film transistor comprising:
より形成されていることを特徴とする特許請求の範囲第
５項記載の薄膜トランジスタの製造方法。(6) The method for manufacturing a thin film transistor according to claim 5, wherein at least a common portion of the first conductive film is formed of a transparent conductive film.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP60118520A JPH077772B2 (en) | 1985-05-31 | 1985-05-31 | Thin film transistor device and manufacturing method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP60118520A JPH077772B2 (en) | 1985-05-31 | 1985-05-31 | Thin film transistor device and manufacturing method thereof |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS61276374A true JPS61276374A (en) | 1986-12-06 |
| JPH077772B2 JPH077772B2 (en) | 1995-01-30 |
Family
ID=14738651
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP60118520A Expired - Lifetime JPH077772B2 (en) | 1985-05-31 | 1985-05-31 | Thin film transistor device and manufacturing method thereof |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH077772B2 (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH022636A (en) * | 1988-06-16 | 1990-01-08 | Mitsubishi Electric Corp | Manufacture of thin film transistor array |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5825689A (en) * | 1981-08-07 | 1983-02-15 | 三洋電機株式会社 | Color liquid crystal display |
| JPS58112365A (en) * | 1981-12-26 | 1983-07-04 | Fujitsu Ltd | Manufacture of thin film transistor |
| JPS59149060A (en) * | 1983-02-15 | 1984-08-25 | Sharp Corp | Manufacture of thin-film transistor |
| JPS6151972A (en) * | 1984-08-22 | 1986-03-14 | Matsushita Electric Ind Co Ltd | Thin film transistor array and manufacture thereof |
-
1985
- 1985-05-31 JP JP60118520A patent/JPH077772B2/en not_active Expired - Lifetime
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5825689A (en) * | 1981-08-07 | 1983-02-15 | 三洋電機株式会社 | Color liquid crystal display |
| JPS58112365A (en) * | 1981-12-26 | 1983-07-04 | Fujitsu Ltd | Manufacture of thin film transistor |
| JPS59149060A (en) * | 1983-02-15 | 1984-08-25 | Sharp Corp | Manufacture of thin-film transistor |
| JPS6151972A (en) * | 1984-08-22 | 1986-03-14 | Matsushita Electric Ind Co Ltd | Thin film transistor array and manufacture thereof |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH022636A (en) * | 1988-06-16 | 1990-01-08 | Mitsubishi Electric Corp | Manufacture of thin film transistor array |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH077772B2 (en) | 1995-01-30 |
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