JPS61276226A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPS61276226A JPS61276226A JP60116384A JP11638485A JPS61276226A JP S61276226 A JPS61276226 A JP S61276226A JP 60116384 A JP60116384 A JP 60116384A JP 11638485 A JP11638485 A JP 11638485A JP S61276226 A JPS61276226 A JP S61276226A
- Authority
- JP
- Japan
- Prior art keywords
- oxide film
- silicon substrate
- silicon surface
- thermal oxidation
- silicon
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Abstract
Description
【発明の詳細な説明】
〔発明の技術分野〕
本発明は半導体装置の製造方法に係わ夛、たとえば立体
形状を有するシリコン基板上におけるMOSキャンミシ
タ製造方法に関する。DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a method for manufacturing a semiconductor device, and for example, to a method for manufacturing a MOS canister on a silicon substrate having a three-dimensional shape.
立体形状を有するシリコン表面上に熱酸化膜を形成した
際、シリコン表面上の凹部あるいは凸部においては酸化
膜厚が平坦部に比べ薄くなるという現象が見られる。こ
の原因は、シリコン表面の凹部あるいは凸部忙おいて、
熱酸化時に生じる応力の集中のため酸化速度がこの部分
で低下するからである。応力の集中は凹部あるいは凸部
の曲率半径の小さい程著しく、したがって薄膜化の糧度
も大きい。さらに凹部あるいは凸部では立体形状に帰因
する電界の集中が起こるためこの部分におけるFowl
er −Nordheim電流は著しく増え、酸化膜の
絶縁特性は悪くなる。When a thermal oxide film is formed on a silicon surface having a three-dimensional shape, a phenomenon is observed in which the oxide film is thinner in concave or convex parts of the silicon surface than in flat parts. The cause of this is due to the depressions or protrusions on the silicon surface.
This is because the oxidation rate decreases in this area due to the concentration of stress that occurs during thermal oxidation. The concentration of stress becomes more pronounced as the radius of curvature of the concave or convex portions becomes smaller, and therefore the possibility of thinning the film increases. Furthermore, in concave or convex parts, the electric field is concentrated due to the three-dimensional shape, so the Fowl in this part is
The er -Nordheim current increases significantly and the insulation properties of the oxide film deteriorate.
このことを溝堀りキャパシタの場合を用いて第4図(a
)〜(C)を参照して簡単に説明する。まず、第4図(
a)に示す如く比抵抗5〜50[ΩIll’fi−1コ
程度のP型(100)シリコン基板21を用意し、この
基板11の素子形成領域上にマスク材nを形成する。次
いで同図(b)に示す如くマスク材nをマスクとしてシ
リコン基板21を異方性エツチングし、例えば深さ2(
μm)程度の溝部乙を形成する。その後、同図(C)に
示す如く溝部乙に熱酸化によりゲート酸化膜飢およびゲ
ート電極δを形成し、溝堀りキャパシタが作成されるこ
と罠なる。This can be explained using the case of a trench-horizontal capacitor in Figure 4 (a).
) to (C) will be briefly explained. First, Figure 4 (
As shown in a), a P-type (100) silicon substrate 21 having a specific resistance of about 5 to 50 [ΩIll'fi-1 is prepared, and a mask material n is formed on the element formation region of this substrate 11. Next, as shown in FIG. 2(b), the silicon substrate 21 is anisotropically etched using the mask material n as a mask, for example, to a depth of 2 (
A groove B of approximately 1.0 μm is formed. Thereafter, as shown in FIG. 2C, a gate oxide film and a gate electrode δ are formed by thermal oxidation in the trench portion A, thereby creating a trench capacitor.
しかしながら、この種の従来方法にあっては次のような
問題があった。すなわち、前記ゲート酸化膜鴎を形成す
る際に、凸型コーナあ、および凹型コーナτにおいては
酸化速度が平坦部よυも遅くなるため、ゲート酸化[2
4においてコーナ部1617では膜厚が平坦部よりも薄
くなってしまう。さらに、コーナ部16 、17では電
界の集中も生じるため、ゲート酸化膜のFowler
−Nordhefm電流が増大し、絶縁特性は平置キャ
パシタの場合に比べて著しく低下する。However, this type of conventional method has the following problems. That is, when forming the gate oxide film, the oxidation rate is slower at the convex corners A and the concave corners τ than at the flat areas, so that the gate oxidation [2
4, the film thickness at the corner portion 1617 is thinner than that at the flat portion. Furthermore, since electric field concentration also occurs at the corner portions 16 and 17, the Fowler of the gate oxide film
-The Nordhefm current increases and the insulation properties are significantly degraded compared to the case of a flat capacitor.
本発明の目的は、立体形状を有するシリコン表面上に酸
化膜を形成した際に酸化膜の絶縁特性を向上させ、素子
の信傾性を高め得る半導体装置の製造方法を提供するこ
とにある。An object of the present invention is to provide a method for manufacturing a semiconductor device that can improve the insulating properties of an oxide film when it is formed on a silicon surface having a three-dimensional shape, thereby increasing the reliability of the device.
〔発明の概要)
本発明は立体形状を有するシリコン表面を一旦少くとも
900℃以上で熱酸化し、100λ以上500Å以下の
酸化膜を形成し、しかる後この酸化膜をエツチング除去
するか、あるいは一旦塩化水素を10チ以下含む酸化雰
囲気中で熱酸化し、酸化膜を形成し、しかる後この酸化
膜をエツチング除去することによってシリコン表面の形
状に丸みを持たせ、この後にシリコン表面を酸化した際
に酸化膜の局部的な薄膜化及び電界の集中を抑制する方
法である。[Summary of the Invention] The present invention involves thermally oxidizing a silicon surface having a three-dimensional shape at at least 900°C or higher to form an oxide film with a thickness of 100λ or more and 500Å or less, and then removing this oxide film by etching, or Thermal oxidation is performed in an oxidizing atmosphere containing less than 10% of hydrogen chloride to form an oxide film, and this oxide film is then removed by etching to give the silicon surface a rounded shape. This method suppresses the local thinning of the oxide film and the concentration of electric fields.
本発明によればシリコン表面上の立木形状に丸みを持た
せることができる。具体的に第2図(a)〜(C)及び
第3図(a)〜(C)にそれぞれ凹型コーナーと凸型コ
ーナーの場合について示した。第2図(a)に示した凹
型コーナ31を熱酸化すると、同図(1))に示す如く
酸化膜32が形成される。酸化時にコーナ部に生じる応
力の集中によってコーナ部の酸化速度が遅くなるため、
酸化膜32とシリコンの界面は丸みを帯びる′。′酸化
膜32をエツチング除去すると、同図(C)に示す如く
シリコン表面は丸みをもつ。一方第3図(a)に示した
凸型コーナ41をもつシリコン表面を熱酸化すると、同
図(b)に示す如く酸化膜42が形成される。酸化時に
はコーナ部では応力の集中が生じるが900℃以上では
酸化膜の粘性流のために応力の緩和の効果が働くことか
ら酸化速度の低下は防止される0したがって同図(b)
に示す如く酸化膜42とシリコンの界面は丸みを帯びる
。この効果は酸化剤中に10%以下の塩化水素が含まれ
ると更に促進される0酸化膜42をエツチング除去する
と同図(C)に示す如くシリコン表面は丸みをもつ。According to the present invention, the shape of trees on the silicon surface can be rounded. Specifically, FIGS. 2(a) to 3(C) and 3(a) to 3(C) show cases of concave corners and convex corners, respectively. When the concave corner 31 shown in FIG. 2(a) is thermally oxidized, an oxide film 32 is formed as shown in FIG. 2(1)). The concentration of stress that occurs at the corners during oxidation slows down the oxidation rate at the corners.
The interface between the oxide film 32 and silicon is rounded. 'When the oxide film 32 is removed by etching, the silicon surface becomes rounded as shown in FIG. On the other hand, when the silicon surface having the convex corners 41 shown in FIG. 3(a) is thermally oxidized, an oxide film 42 is formed as shown in FIG. 3(b). During oxidation, stress concentration occurs at the corners, but at temperatures above 900°C, the viscous flow of the oxide film has a stress-relieving effect, which prevents the oxidation rate from decreasing.
As shown in the figure, the interface between the oxide film 42 and silicon is rounded. This effect is further enhanced when the oxidizing agent contains hydrogen chloride in an amount of 10% or less. When the 0 oxide film 42 is removed by etching, the silicon surface becomes rounded as shown in FIG.
以上のようにして立体形状をもつシリコン表面に丸みを
もたせることによって、その後の酸化においては、酸化
膜の局部的な薄膜化および電界の集中を防ぐことができ
、酸化膜の絶縁特性は著しく向上する。By rounding the three-dimensional silicon surface as described above, it is possible to prevent local thinning of the oxide film and concentration of electric fields during subsequent oxidation, and the insulation properties of the oxide film are significantly improved. do.
第1図(a)〜(C)は本発明の一実施例に係わる溝堀
シキャパシタ製造工程断面図を示している。まず第1図
(→に示す如く比抵抗5〜50(0m)のP型(100
)シリコン基板(半導体基板)11を用意し、この基板
11上に酸化膜を0.8μm程度被着し、通常の写真食
刻工程を行うこと罠より、素子形成領域上の酸化膜を除
去してマスク材比を形成する。次に同図(b)に示す如
く同じマスク材羽を用いシリコン基板31 t−几IE
で垂直に2(μm)異方性エツチングして溝部13を形
成する。その後マスク材12を除去し、本製造方法を用
いて溝部13におけるコーナ部14 、15に丸みをも
たせる。すなわち、同図(C)に示す如く、−五酸化性
雰囲気中で900℃以上で熱酸化し、100Å以上50
0λ以下の酸化[16を形成した後これをエツチング除
去する。あるいは一旦10%以下の塩化水素を含む酸化
性雰囲気中で熱酸化し酸化膜16を形成した後これをエ
ツチング除去する。しかる後周知の方法によシ(d)に
示す如くゲート酸化膜17およびゲート電極18を形成
する。FIGS. 1A to 1C show cross-sectional views of the manufacturing process of a Mizohori capacitor according to an embodiment of the present invention. First, as shown in Figure 1 (→), P type (100
) A silicon substrate (semiconductor substrate) 11 is prepared, an oxide film of about 0.8 μm is deposited on this substrate 11, and the oxide film on the element formation area is removed by performing a normal photolithography process. to form the mask material ratio. Next, as shown in the same figure (b), using the same mask material blade, a silicon substrate 31 t-IE
The groove portion 13 is formed by anisotropic etching of 2 (μm) vertically. Thereafter, the mask material 12 is removed, and the corners 14 and 15 of the groove 13 are rounded using this manufacturing method. That is, as shown in FIG.
After forming oxidation [16] of 0λ or less, this is removed by etching. Alternatively, once the oxide film 16 is formed by thermal oxidation in an oxidizing atmosphere containing 10% or less hydrogen chloride, this is removed by etching. Thereafter, a gate oxide film 17 and a gate electrode 18 are formed by a well-known method as shown in FIG.
かくして本実施例によれば、溝堀シキャパシタにおいて
溝部のコーナ部を丸くすることができ、ゲート酸化膜の
コーナ部での薄膜化およびコーナ部での電界集中を防止
、し、素子の信頼性を向上させることができる。Thus, according to this embodiment, the corners of the trench in the trench-horizon capacitor can be rounded, which prevents the gate oxide film from becoming thinner at the corner and from concentrating the electric field at the corner, thereby improving the reliability of the device. can be improved.
なお本発明は上述した実施例に限定されるものではなく
、その要旨を逸脱しない範囲で種々に変化して実施でき
る。Note that the present invention is not limited to the embodiments described above, and can be implemented with various changes without departing from the gist thereof.
を丸める方法を示す断面図、第4図(→〜(C)は従来
の溝堀シキャパシタ全説明するための工程図である。FIG. 4 is a cross-sectional view showing a method of rounding the capacitor, and FIGS.
11 、21・・・シリコン基板(半導体基板)、12
、22・・・マスク材(シリコン酸化膜)、13 、
23・・・溝部、 16 、32 、42・・・酸
化膜、14 、26 、41・・・凸型コーナ、15
、27 、31・・・凹型コーナ、17 、24・・・
ゲート酸化膜、18,5・・・ゲート電極。11, 21... silicon substrate (semiconductor substrate), 12
, 22...mask material (silicon oxide film), 13,
23... Groove portion, 16, 32, 42... Oxide film, 14, 26, 41... Convex corner, 15
, 27 , 31 ... concave corner, 17 , 24 ...
Gate oxide film, 18,5...gate electrode.
代理人 弁理士 則 近 憲 佑(ほか1名)第1図 第2図 第3図Agent: Patent attorney: Kensuke Chika (and 1 other person) Figure 1 Figure 2 Figure 3
Claims (2)
り、一旦該シリコン表面を少くとも900℃以上で熱酸
化し100Å以上500Å以下の酸化膜を形成する工程
と、該酸化膜を除去する工程と、しかる後に前記シリコ
ン表面に所望の酸化膜を形成する工程とを具備したこと
を特徴とする半導体装置の製造方法。(1) When oxidizing a silicon surface having a three-dimensional shape, a step of thermally oxidizing the silicon surface at least at 900° C. or higher to form an oxide film with a thickness of 100 Å or more and 500 Å or less, and a step of removing the oxide film; A method of manufacturing a semiconductor device, comprising the step of: thereafter forming a desired oxide film on the silicon surface.
り、一旦該シリコン表面を10%以下の塩化水素を含む
酸化剤雰囲気中で熱酸化し酸化膜を形成する工程と、該
酸化膜を除去する工程と、しかる後に前記シリコン表面
に所望の酸化膜を形成する工程とを具備したことを特徴
とする半導体装置の製造方法。(2) When oxidizing a silicon surface having a three-dimensional shape, there is a step of thermally oxidizing the silicon surface in an oxidizing agent atmosphere containing 10% or less hydrogen chloride to form an oxide film, and a step of removing the oxide film. A method for manufacturing a semiconductor device, comprising the steps of: and then forming a desired oxide film on the silicon surface.
Priority Applications (4)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP60116384A JPS61276226A (en) | 1985-05-31 | 1985-05-31 | Manufacture of semiconductor device |
US06/866,310 US4735824A (en) | 1985-05-31 | 1986-05-23 | Method of manufacturing an MOS capacitor |
KR1019860004247A KR900000064B1 (en) | 1985-05-31 | 1986-05-29 | Method of manufacturing of capacity |
DE19863618128 DE3618128A1 (en) | 1985-05-31 | 1986-05-30 | METHOD FOR PRODUCING A MOS CONDENSER |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP60116384A JPS61276226A (en) | 1985-05-31 | 1985-05-31 | Manufacture of semiconductor device |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS61276226A true JPS61276226A (en) | 1986-12-06 |
Family
ID=14685678
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP60116384A Pending JPS61276226A (en) | 1985-05-31 | 1985-05-31 | Manufacture of semiconductor device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS61276226A (en) |
-
1985
- 1985-05-31 JP JP60116384A patent/JPS61276226A/en active Pending
Similar Documents
Publication | Publication Date | Title |
---|---|---|
JPS6220698B2 (en) | ||
JPS59119848A (en) | Manufacture of semiconductor device | |
JPH03145730A (en) | Manufacture of ic semiconductor device | |
JPS58202545A (en) | Manufacture of semiconductor device | |
JPH02277253A (en) | Manufacture of semiconductor device | |
JPS61276226A (en) | Manufacture of semiconductor device | |
JPS5956740A (en) | Manufacture of semiconductor device | |
JPS5850753A (en) | Manufacture of semiconductor device | |
JPS5812732B2 (en) | Manufacturing method for semiconductor devices | |
JPH03153031A (en) | Manufacture of semiconductor device | |
JPS62274665A (en) | Manufacture of semiconductor device | |
JPS6123363A (en) | Semiconductor device and manufacture of the same | |
JPH0680726B2 (en) | Method for manufacturing semiconductor device | |
JPS6139736B2 (en) | ||
JPH01187943A (en) | Manufacture of semiconductor device | |
JP2546651B2 (en) | Method of manufacturing bipolar transistor | |
JPS6164161A (en) | Semiconductor device and manufacture thereof | |
JPH08236475A (en) | Formation of contact window | |
JPS5963741A (en) | Manufacture of semiconductor device | |
JPS61152062A (en) | Manufacture of semiconductor device | |
JPS622664A (en) | Semiconductor memory device and manufacture thereof | |
JPS5910236A (en) | Fabrication of semiconductor device | |
JPH02135756A (en) | Manufacture of semiconductor device with trench isolation | |
JPS6247166A (en) | Manufacture of semiconductor device | |
JPS5968950A (en) | Manufacture of semiconductor device |