JPS61274335A - Method for testing wafer - Google Patents

Abstract

PURPOSE:To shorten the testing time by effecting the automatic measurement at efficient testing speed in the testing mode for the non-defective decision of devices by measuring and memorizing the variability of the factors of a device parameter of a digital LSI for each chip previously. CONSTITUTION:The propagation delay time tdp and the time for measurement of gain beta is extremely short and the propagation delay time tdp and gain betafor each chip 2 arranged on a wafer are previously measured and stored in a memory 5 provided with sufficient capacity. In the non-defective decision test for each chip 2, a difference between the contents previously stored in the memory 5 (values of tdp and beta) and the bus data sent from a control circuit 4 are calculated for each set chip by a calculation circuit 6 and the velocity of an oscillator 7 suitable for the delay time tdp and gain beta of each chip is determined. The modulated oscillation output of the oscillator 7 is given to the control circuit 4, which makes the testing speed of the chip to be measured variable for modulation and a digital LSI is measured automatically by preset ting the optimum condition in the testing mode.

Description

[Detailed Description of the Invention] [Technical Field] This invention relates to an automatic wafer testing method, and in particular, to efficiently execute wafer test throughput for digital LSI and quickly identify good and defective chips for each chip. Regarding the test method to determine the

<Summary of the Invention> In order to improve the efficiency of wafer testing, the present invention provides a method for improving the efficiency of wafer testing, in which the frequency margin in the test mode is different for each chip and each wafer when the test mode is tested at a faster speed than the actual usage state. In response to this, test conditions can be preset programmably for each chip, and in the actual test mode, the programmed test conditions are read out and the optimum test speed is automatically set and tested to determine whether the product is good or defective. Determine.

<Prior Art> Conventionally, semiconductor chips that have undergone a certain manufacturing process are automatically inspected to determine whether they are good or defective in the wafer state. Measurements at this time are usually performed under uniform test conditions.

<Problems to be Solved by the Invention> According to the above conventional wafer testing method, the LSI to be measured
Different test results are obtained due to variations in factors such as device parameters such as threshold voltage vth, gain, and contact resistance, depending on the characteristics of the semiconductor substrate itself and process conditions. In other words, even if the chip itself is a good chip, there are variations in each chip, so
When executed in the same test mode, a situation arises in which the chip is treated as if it were a defective chip, resulting in a significant loss of test reliability. In particular, the above-mentioned problems are likely to occur in digital LSIs in which a wafer test is performed in a faster test mode different from the user mode actually used in order to improve test efficiency.

In order to solve the above-mentioned problems with the conventional method, in wafer testing of digital LSIs that have completed the manufacturing process, among the factors that the device has as parameters, especially those closely related to the frequency margin, Each chip is picked up in advance and programmed into a storage device, and in the test mode, the contents of this program are read out to set optimum test conditions and automatically perform a wafer test.

Even when multiple chips are included in the same wafer and each has a different frequency margin, as in the general manufacturing process of semiconductor devices, the oscillation built into the digital circuit of each chip is By measuring the propagation delay time tdp and gain β of the circuit inverter in advance, it is possible to automatically set and measure an appropriate speed for each chip from these values.

<Example> A method for testing a wafer on which a large number of digital LSIs each having a built-in oscillation circuit are fabricated will be described as an example.

The wafer that has undergone the manufacturing steps required to function as a digital LSI is loaded into the LSI test system 1 in wafer form without being divided into individual semiconductor chips. The wafer 2 mounted on the LSI test system 1 is configured such that each chip has a small number of built-in inverters 8 for resonant circuits.

The LSI test system 1 includes a control circuit 4 that inputs and outputs control signals necessary for testing each chip 2. 5. Memory containing the factors of each chip, which will be described later. Memory 5
The oscillator 7 includes an arithmetic circuit 6 for calculating an optimum test speed and an oscillator 7 to which the result of the arithmetic circuit 6 is input and operates to oscillate at an appropriate speed.

In the above LSI test system, before determining whether each chip is good or bad, a factor program for determining the test speed of this determination mode is executed in advance.

That is, a pulse-like oscillation input signal A shown in FIG.
is applied to

The inverter 3 forms an output signal B corresponding to the input signal A and inputs it to the control circuit 4 of the test system.

In the control circuit 4, the length of the oscillation input signal A is set in advance to exceed the pulse width of the oscillation input signal A.

During the sweep operation of the strobe signal S, the control circuit 4 is given an output signal B from the output terminal of the inverter 3. appear with different delay times tdp. The delay time tdp is measured using the strobe signal S, and the measurement result is stored in the memory 5 in association with the chip position within the wafer.

In addition, for the same chip to be measured, when the input signal level of the inverter 3 for 1 oscillation circuit is changed from "high" to "1 low", the output current force 1 to gain β of the inverter 3 at each signal state is also calculated. are measured and stored in the memory 5 as well.

The time required to measure the propagation delay time j dp and gain β is extremely short, so the propagation delay time tdp and gain β are measured in advance for each chip provided on the wafer, and the memory 5 with sufficient capacity is to be memorized.

Next, in a non-defective determination test for each chip, for each set chip, the above contents (values of t, d, and β) stored in the memory 5 and the bus data sent from the control circuit 4 are used. The arithmetic circuit 6 calculates the difference between the two and sets the speed of the oscillator 7 appropriate for the delay time td and gain β of each chip. In the generation test mode, the digital LSI is automatically measured under optimal conditions.

In the above embodiment, the test conditions were determined by giving the propagation delay time Ldp and the gain β, but the test conditions are not limited to the above factors, and other factors may be used.

<Effects of the Invention> As described above, according to the present invention, by measuring and storing the variation in device parameter factors of digital LSI for each chip in advance, it is possible to efficiently perform the test mode when determining whether the device is good. Automatic measurement can be performed at a fast test speed, reducing test time. Furthermore, it is possible to perform tests that are compatible with each device, thereby increasing test accuracy and preventing erroneously identifying good products as defective products.

[Brief explanation of the drawing]

FIG. 1 is a block diagram for explaining an embodiment of the present invention, and FIG. 2 is a time chart for explaining the embodiment. 1: LSI test system, 2: chip. 3: Inverter for oscillation circuit, 4: Control circuit.

Claims (1)

[Claims] 1) In wafer testing of digital LSI, characteristics that regulate the test speed are measured in advance for each chip included in the wafer, and the results are stored in memory, and the above-mentioned stored contents are used during chip testing. A wafer testing method characterized by reading data, setting a test speed higher than the operating speed during actual use, and executing the test.