JP2000132996A - Method and apparatus for sorting defective of semiconductor memory - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a method and an apparatus for sorting defectives of a semiconductor memory whereby the semiconductor memory having a defective memory cell specifically inferior in performance which cannot be sorted according to a uniform sort condition among a plurality of memory cells of the semiconductor memory can be sorted. SOLUTION: There are provided a performance-testing part 6 for testing a performance of a semiconductor memory, a performance test control part 5 for executing the performance test to the semiconductor memory with a condition value designated to the performance-testing part 6, and judging good, defective memory cells, a correlation data-obtaining part 2 which outputs the condition value to the performance test control part 5, counts the number of defective memory cells of the semiconductor memory to the condition value from judgment results of the performance test control part 5, and obtains correlation data between the condition value and the number of defective memory cells, a reference condition value-determining part 3 for obtaining a reference condition value of a condition parameter reflecting an average performance of a plurality of memory cells, and a sort condition-determining part 4 for determining a sort condition value for the semiconductor memory on the basis of the reference condition value.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method and an apparatus for selecting defective or defective semiconductor memory devices.

[0002]

2. Description of the Related Art For example, SRAM (Static Random Ac
Semiconductor memory devices such as cess memory) have become faster, larger in capacity, and more sophisticated. In addition, in order to supply highly reliable semiconductor memory devices, semiconductor memory device test techniques have become important. I have. The performance test of the semiconductor memory device is performed using, for example, a test device called a memory tester. For example, the performance test is performed on the operating voltage, the temperature, and the like. Conventionally, non-defective products and defective products of a semiconductor memory device are selected by performing a predetermined performance test under a certain screening condition, for example, in the case of the same type of semiconductor memory device, for example, a certain voltage condition in the case of operating voltage. Good products and defective products were selected based on the test results.

[0003]

However, if non-defective and defective semiconductor storage devices are selected under uniform selection conditions, for example, electrical disconnection due to defects or dust may occur in the storage cells of the semiconductor storage device. When there is a leak or the like, there are many storage cells that can be reliably removed under a predetermined selection condition, and storage cells that operate under a certain selection condition but have a specifically inferior performance. Such a memory cell having a specifically inferior performance is hereinafter referred to as a weak bit. Although the weak bit passes the selection itself, the weak bit may cause a failure in an accelerated test after the selection or in actual use. For example, as shown in FIG. 8, when the same semiconductor memory device is tested under a plurality of different selection conditions, the number of storage cells determined to be defective increases as the selection conditions become more severe after the conditions 3 and 4. There is a tendency. In FIG. 8, as the hatching interval becomes narrower,
This indicates that the number of storage cells determined to be defective increases. Further, when the condition becomes looser than the condition 3, except for the weak bit, there is no memory cell determined to be defective.
In the case shown in FIG. 8, for example, condition 6 to condition 8
When a performance test is uniformly performed under any of the conditions, weak bits are not detected.

FIGS. 9 (a) to 9 (c) show examples of performance characteristics of three semiconductor memory devices of the same type having different performance characteristics, and the horizontal axis shows condition parameters. The condition becomes looser as the position advances in the axial direction, and the vertical axis indicates the logarithm of the number of defective memory cells. Further, each memory cell of the semiconductor memory device shown in FIG. 9A has excellent overall performance that passes more severe conditions, and each memory cell of the semiconductor memory device shown in FIG. However, the overall performance is inferior, and the semiconductor memory device shown in FIG. 9C has a weak bit.

When the performance of each memory cell of a semiconductor memory device is entirely uniform, as shown in FIGS. 9A and 9B, regardless of the overall performance, the condition parameter is not affected. The logarithmic value of the number of defective memory cells changes smoothly,
As the condition of the condition parameter becomes milder, the number of storage cells determined to be defective in the downward right direction decreases. On the other hand, in the semiconductor memory device shown in FIG. 9C, weak bits that are determined to be defective are specifically generated according to changes in the condition parameters. If the semiconductor memory devices of all performances are uniformly selected with the same condition value Vk, only the semiconductor memory device of poor overall performance shown in FIG. 9B is selected as a defective semiconductor memory device, and weak bits are determined. The semiconductor memory device having the weak bit was determined to be non-defective, and it was difficult to select the semiconductor memory device having the weak bit.

SUMMARY OF THE INVENTION The present invention has been made in view of the above problems, and has a semiconductor memory device having a memory cell having a specifically inferior performance which cannot be selected under a uniform selection condition among a plurality of storage cells of a semiconductor memory device. It is an object of the present invention to provide a method for selecting a defective semiconductor memory device that can select a memory device.

[0007]

According to the present invention, a performance test is performed on a plurality of storage cells included in a semiconductor memory device with respect to predetermined condition parameters, and good and defective semiconductor memory devices are selected based on the test results. Performing a performance test of the storage cell with respect to a plurality of condition values of the condition parameter to obtain correlation data between the condition parameter and the number of defective storage cells. Determining a selection condition value of the condition parameter for selecting non-defective products and defective products of the semiconductor storage device based on the data.

The step of obtaining the correlation data and the step of determining the selection condition value are performed for each semiconductor memory device to be selected.

In the step of obtaining the correlation data, the performance test is performed on all of the plurality of storage cells.

[0010] The step of obtaining the correlation data includes the step of performing a performance test on the condition parameters of some of the plurality of storage cells, and the step of determining the number of defective storage cells based on the result of the performance test and the condition. A step of obtaining correlation data with parameters; and a step of estimating correlation data between the number of defective storage cells and the condition parameters for all storage cells based on the correlation data for some of the storage cells.

The step of determining the selection condition value includes the step of obtaining a reference condition value of the condition parameter reflecting an average performance of the plurality of storage cells based on the correlation data; Determining a selection condition value for selecting good or defective semiconductor memory devices based on the condition value.

In the step of obtaining the reference condition value, a value of a condition parameter for setting a ratio of the total number of storage cells to the number of defective storage cells to a predetermined value is determined based on the correlation data, and the value of the condition parameter is determined. The reference condition value is used.

In the relationship between the condition parameter and the logarithm of the number of defective storage cells, the value of the condition parameter when the value of the logarithm of the number of defective storage cells is half of the logarithm of the total number of storage cells is set to the reference condition. Value.

In the step of determining the selection condition value, the logarithm of the number of defective memory cells is half the logarithm of the total number of memory cells in the relationship between the condition parameter and the logarithm of the number of defective memory cells. Setting the value of the condition parameter at the time as the reference condition value; determining a rate of change of the logarithmic value of the number of defective storage cells with respect to the condition parameter in the vicinity of the reference parameter value; Using the condition parameter as a variable and using a solution of a linear equation having a predetermined constant term as the screening condition value.

The condition parameter is an operating voltage of the semiconductor memory device.

After the selection condition value is determined, the method further includes a step of selecting defective products according to the selected selection condition values and performing a repair process on the selected defective semiconductor memory device.

Further, the present invention provides a semiconductor memory device which performs a performance test on a plurality of memory cells included in a semiconductor memory device with respect to predetermined condition parameters, and sorts a non-defective product or a defective product of the semiconductor memory device based on a test result. A performance test unit for performing the performance test on the semiconductor storage device, and causing the performance test unit to perform a performance test of the semiconductor storage device under specified condition values. And a performance test control unit for discriminating a non-defective product and a defective product of the storage cell from the result, and outputting the condition value to the performance test control unit. Count the number of defective storage cells of the device, a correlation data acquisition unit that acquires correlation data between the condition value and the number of defective storage cells, from the correlation data,
A reference condition value determination unit that obtains a reference condition value of the condition parameter that reflects an average performance of the plurality of storage cells;
A selection condition determination unit configured to determine a selection condition value for selecting a non-defective product or a defective product of the semiconductor storage device based on the reference condition value and the correlation data.

According to the present invention, correlation data between a condition parameter and the number of defective memory cells of a semiconductor memory device is obtained, and a condition parameter selection condition value for selecting a good or defective semiconductor memory device based on the correlation data. Is determined, the selection condition value reflects the performance characteristic of the storage cell of the semiconductor memory device. Therefore, it is possible to select a semiconductor memory device having a defective memory cell that cannot be selected with a uniform selection condition value.

[0019]

Embodiments of the present invention will be described below in detail with reference to the drawings. FIG. 1 is a configuration diagram illustrating a configuration of a defective product selection device according to an embodiment of the present invention. In FIG. 1, a defective product selection device 1 includes a correlation data acquisition unit 2.
And a reference condition value determination unit 3, a selection condition determination unit 4, a main control unit 5, and a performance test unit 6. The performance test unit 6
It has a function of performing various performance tests on the semiconductor memory device to be tested and outputting the test results to the main control unit 5 as a signal 6s. The main control unit 5 outputs a control command 5sa for controlling the operation of the performance test unit 6 to the performance test unit 6 and causes the performance test unit 6 to perform a performance test of the semiconductor memory device under the specified condition value. Based on the result, a good product or a bad product of each memory cell of the semiconductor memory device is determined, and the result of the determination test is signal 5s.
It has a function of outputting to the correlation data acquisition unit 5sb as b.

The correlation data acquisition unit 2 outputs a control command 2sa for designating a condition value relating to a condition parameter of a performance test of the semiconductor memory device to the main control unit 3.
The number of defective memory cells of the semiconductor memory device with respect to the condition value is counted from the determination result of the non-defective product and the defective product of each memory cell,
It has a function of acquiring correlation data between the condition value and the number of defective storage cells.

The reference condition value determining unit 3 designates a condition value relating to a condition parameter V of a performance test of the semiconductor memory device,
The designated condition value 3 is output to the correlation data acquisition unit 2 as the signal 3sa, and the correlation data acquired by the correlation data acquisition unit 2 is acquired from the correlation data acquisition unit 2 as the signal 2sb. Further, the reference condition value determination unit 3 has a function of obtaining a reference condition value Va of a condition parameter V that reflects the average performance of the storage cell of the semiconductor memory device from the obtained correlation data.

FIG. 3 shows the relationship between the condition parameter V and the number C of defective storage cells of the storage cells of the semiconductor memory device. The vertical axis represents the number C of defective memory cells in a logarithmic manner, and the condition parameter V on the horizontal axis is changed from a strict condition to a gentle condition as it progresses in the horizontal axis direction. In the case where the weak bit WB does not exist in each memory cell of the semiconductor memory device and the performance characteristics of each memory cell are average, as shown by a curve X in FIG. , The logarithm of the defective memory cell number C smoothly falls to the right. Further, when the weak bit WB exists in the semiconductor memory device, the curve X does not change smoothly in the lower right region, but changes as shown by a dotted line WB, for example. The reference condition value determination unit 3 determines a condition when the number C of defective storage cells with respect to the total number A of storage cells is a predetermined ratio, for example, when the value Ca is the square root value of the total number A of storage cells. The value of the parameter V is set as a reference condition value Va. The point Pa in FIG. 3 is hereinafter referred to as a reference point Pa.

The selection condition deciding section 4 includes a reference condition value deciding section 3
And the correlation data acquired by the correlation data acquisition unit 2 are input as a signal 3sb,
Based on the reference condition value and the correlation data, the semiconductor memory device has a function of determining a selection condition value Vc for selecting good or defective semiconductor storage devices. Specifically, the value of the condition parameter at the point Pc where the tangent L at the reference point Pa of the curve X shown in FIG. 3 intersects the horizontal axis is set as the selection condition value Vc. The tangent line L is defined by a point Pb and a reference point P on the curve X corresponding to the condition parameter value Vb separated by a small value from the reference condition value Va.
It can be obtained by finding a straight line connecting to a. If the selection is performed using the selection condition value Vc, as shown in FIG. 3, if the semiconductor memory device has the weak bits, the weak bits can be detected.

FIG. 2 is a configuration diagram showing an example of a memory tester to which the present invention is applied. The memory tester shown in FIG. 2 includes a microprocessor 21, a main memory 22,
A data level power supply 23, a programmable power supply 24,
It has a measurement unit 25, a pattern generator 26, a timing pattern generator 27, a pattern formatter 28, and a pin interface unit 29.

The microprocessor 21 controls the entire memory tester, processes measured data, and the like. The main memory 22 stores a program for operating a memory tester and various programs and data such as measurement data.
The data level power supply 23 includes a pin interface unit 29
Is a power supply for determining the operating voltage level. The programmable power supply 24 is a DC power supply for applying an operating voltage to the semiconductor memory device under test when a performance test of the semiconductor memory device under test is performed.

The measuring unit 25 is a DC power supply with a measuring function capable of selecting two functions of constant voltage supply-current measurement or constant current supply-voltage measurement. The pattern generator 26 is a pattern generator that generates a test pattern for the semiconductor memory device to be measured, and generates a test pattern of an address, data, and a clock for the semiconductor memory device to be measured by microprogramming. The timing pattern generator 27 designates rising and falling timings of a pulse waveform so that the pattern formatter 28 generates a pulse signal generated by the pattern generator 26 into a pattern signal having a predetermined pulse width.

The pattern formatter 28 forms a pattern signal to be supplied to each input pin of the semiconductor memory device under test when a performance test of the semiconductor memory device under test is performed. The pin interface unit 29 interfaces with a single semiconductor memory device to be measured, and includes a programmable power supply 24, a measurement unit 25, and a pattern formatter 2.
8 is provided to each designated pin of the semiconductor memory device to be measured, and a comparator for comparing a voltage appearing at an output pin of the semiconductor memory device to be measured with a determination condition.

The performance test section 6 includes a data level power supply 23, a programmable power supply 24,
5, a pattern generator 26, a timing pattern generator 27, a pattern formatter 28, and a pin interface unit 29. Further, the main control unit 5 can be configured by predetermined software prepared in the microprocessor 21 and the main memory 22.

Further, the correlation data acquisition unit 2, the reference condition value determination unit 3, and the selection condition determination unit 4 can be constituted by predetermined software prepared in the microprocessor 21 and the main memory 22. In particular,
When the correlation data acquisition unit 2 receives the condition value of the condition parameter as an input parameter, the function F that returns, as an output, the number C of defective storage cells in the condition value of the semiconductor memory device to be measured.
Is provided in the main memory 22. Note that, when this function F is called once,
The following processing is performed by the control unit 5 and the performance test unit 6.

First, a performance test is performed on all the memory cells of the semiconductor memory device to be measured in accordance with the condition value specified by the reference condition value determining unit 3, and the result of discriminating the pass / fail of each memory cell (pass / fail). Read (fail judgment). Next, the number of failures of the memory cell is counted, and the number of failures is output as a return value.

In general, ^assuming that the total number of memory cells of a semiconductor memory device is A, the time required to perform a performance test on all memory cells of the semiconductor memory device to be measured is A ⁿ
Is proportional to Here, n is a constant (n ≧ 1) determined by the contents of the performance test pattern. In addition, the time required to read the discrimination result (pass / fail judgment) of each storage cell from the main control unit 3 and count the number of failures of the storage cell is proportional to the total number A of storage cells. .

Therefore, it takes time to perform a performance test on all the memory cells. In this embodiment, when a condition value of a condition parameter is input, a performance test is performed on some of the memory cells, and the output of the semiconductor device under test is output. A function G for returning an estimated value (C ′) of the number C of defective storage cells under the condition value of the condition parameter V of the storage device is stored in the main memory 22.
To prepare.

Specifically, the function G first causes a performance test to be performed on the number B of storage cells in an arbitrary part of the chip under test. Next, the pass / fail judgment result of the memory cell number B is read, and the number of fail is counted. Next, the return value is set to (A / B) times the number of failures.

The processing time of the function G is at least B / A compared to the function F. However, in order for the return value of the function G to be a sufficiently significant numerical value, the number of defective storage cells in the number of storage cells to be measured needs to be large to some extent, for example, at least several hundreds are required. In the present embodiment, for example,
When the total number A of memory cells is 16 Mbit, the number B of some memory cells is 4 Mbit, and the function G is used instead of the function F, the time required to obtain the number of failures of the memory cells of the semiconductor memory device Can be reduced to about 1/4.

Next, an example of a processing procedure in the defective product sorting apparatus 1 having the above configuration will be described with reference to flowcharts shown in FIGS. The case where the operating voltage V of the semiconductor memory device to be measured is used as the condition parameter in the performance test of the memory cell of the chip to be measured will be described. First, the reference condition value determining section 3 determines a reference condition value Va of the operating voltage. An operating voltage variable Vi, an increasing / decreasing variable Vj of the operating voltage variable Vi, and a threshold voltage Vt of the increasing / decreasing variable Vj are defined (step S1). Operating voltage variable V
The initial values of i, increase / decrease variable Vj, and threshold voltage Vt are, for example, operating voltage variable Vi is an average value expected for reference condition value Va of operating voltage V, and reference condition value Va of increase / decrease variable Vj And the threshold voltage Vt is the same value as the accuracy required for the reference condition value Va. Specifically, the initial value of the operating voltage variable Vi is 2.3 [V], and the initial value of the increase / decrease variable Vj is
0.2 [V], and the threshold voltage Vt was 0.05 [V].

Next, the above-mentioned function G is called, the operating voltage variable Vi is input, and the return value of the function G is compared with the square root value Ca of the total number A of memory cells of the semiconductor memory device to be measured (step). S2). If the return value of the function G is larger than the square root value Ca of the total number A of memory cells, the operating voltage variable Vi is updated by adding the increase / decrease variable Vj to the operating voltage variable Vi (step S3). When the return value of the function G is smaller than the value Ca of the square root of the total memory cell number A, the increase / decrease variable Vj is subtracted from the operating voltage variable Vi to determine the operating voltage variable Vi.
Is updated (step S4). When the operating voltage variable Vi is updated, the increase / decrease variable Vj is divided by 2 to update the increase / decrease variable Vj (step S5). Next, the magnitude of the increase / decrease variable Vj is compared with the threshold voltage Vt (step S6). If the increase / decrease variable Vj is smaller than the threshold voltage Vt, the process returns to step S2 to repeat the above processing. Increase / decrease variable V
If j is higher than the threshold voltage Vt, the current operating voltage variable Vi is set as the reference condition value Va (Step S).
7). The reference condition value Va is determined by the processing in the reference voltage determination unit 3 described above.

The operating voltage variable V in each of the above steps
FIG. 7 shows an example of possible values of i and the increase / decrease variable Vj. As shown in FIG. 7, when the processing of steps S2 to S6 is repeated three times, the operating voltage variable Vi has eight possible values. Further, finally, the operating voltage variable Vi
Is about twice as large as the increase / decrease variable Vj, and it is desirable to take this point into account when determining the initial value of the increase / decrease variable Vj.

Next, in the selection condition determining section 4, FIG.
The procedure for obtaining the selection condition value Vc described in the above will be described. As shown in FIG. 4, first, an arbitrary minute voltage value ΔV is added to the above-described reference condition value Va, and a voltage value Vb which is a value of a condition parameter separated from the above-mentioned reference condition value Va by a minute value is obtained. It is calculated (step S10). The value of ΔV may be, for example, the same value as the accuracy required for the selection condition value Vc.

Next, the function G is called to find the number Ca of defective memory cells at the reference condition value Va and the number Cb of defective memory cells at the operating voltage Vb. That is, Ca = G
(Va), Cb = G (Vb) (Step S1)
1).

Next, the number of defective memory cells Ca and Cb are compared and determined (step S12). If the number of defective memory cells Ca and the number of defective memory cells Cb are equal, the process proceeds to an exception process, and an arbitrary selection condition is separately set. Determine the value (Step S1
5). When the number Ca of defective memory cells is different from the number Cb of defective memory cells, the solution of the linear equation shown in the following equation (1) is calculated using the reference condition value Va, the operating voltage Vb, and the numbers Ca, Cb of defective memory cells. Then, the selection condition value Vc is determined. In addition,
V0 is an arbitrary offset value. Also, if the obtained selection condition value Vc does not satisfy a certain criterion,
The process proceeds to the exception process, and an arbitrary selection condition is separately determined (step S14).

[0041]

(Equation 1)

FIG. 6 is a diagram showing the result of obtaining the selection condition value Vc of the same type of semiconductor memory device having the memory cell having various performance characteristics by the above-described processing procedure. FIG.
FIG. 6A shows the case of a semiconductor memory device having excellent overall performance in which each memory cell passes more severe conditions.
FIG. 6B shows a case where each memory cell has no defect but has poor overall performance, and FIG. 6C shows a case where each memory cell has a weak bit. As can be seen from FIG.
When the selection condition value Vc is obtained according to the above-described processing procedure, the selection condition value Vc is determined according to the overall performance characteristics of the storage cell of each semiconductor memory device, and as shown in FIG. If the device has a weak bit, the weak bit is reliably detected. That is, if there is no weak bit having a specific performance characteristic in the memory cell of the semiconductor memory device, as shown in FIG.
Since the relationship between the condition parameter V and the logarithm of the number of defective memory cells is a smooth downward-sloping curve, the slope of the downward-sloping curve reflects the average performance characteristics of the memory cells of the semiconductor memory device. I can say. Therefore, if the relationship between the condition parameter V and the logarithm of the number of defective memory cells does not form a smooth right-downward curve but deviates from the tangent of the right-downward curve, the semiconductor memory device is considered to have weak bits. You can judge.

In the present embodiment, as a step subsequent to the above-described step of selecting a semiconductor memory device, repair processing is performed on weak bits of the selected semiconductor memory device. The repair process is a process of replacing weak bits with spare memory cells (redundant cells) facilitated by a semiconductor memory device. The work of replacing weak bits with redundant cells is, for example,
This is performed by cutting a specific partial wiring of the semiconductor memory device with a laser cutter device (usually, blowing a fuse), and the weak bit is replaced with a substantially equivalent electrically redundant cell. Therefore, even if the semiconductor memory device has a weak bit, it can be reproduced as a non-defective product by this repair process.

In the repair process, which memory cell is to be repaired is usually determined by performing a function test on the semiconductor memory device under certain conditions in the above-described memory tester and based on the test result. . That is, the address of the storage cell that is defective in the above test is taken into the main memory 22 of the memory tester,
The location to be repaired is determined based on this information, and the wiring of the semiconductor memory device is cut by the laser cutter device.

As described above, according to the present embodiment, the selection condition value Vc is determined according to the average performance characteristics of the storage cells of the semiconductor memory device. It is possible to detect weak bits having specific performance characteristics deviating from the characteristics. As a result, a more reliable semiconductor memory device can be selected.

According to the present embodiment, the selection condition value Vc is determined using the logarithm of the number of defective memory cells. Therefore, even when a weak bit exists in the semiconductor memory device,
The reference point Pa on the graph hardly shifts. In addition, the inclination of the tangent line L at the reference point Pa hardly shifts, and the sorting condition value Vc can be obtained with high accuracy. According to the present embodiment, it is necessary to perform the performance test of the semiconductor memory device a plurality of times for each condition value.
By using the function G, it is not necessary to perform the performance test on all the memory cells, so that the time required for the performance test of the semiconductor memory device can be minimized.

According to the present embodiment, the repair process is performed in the post-process of the performance test of the semiconductor memory device.
Reproduction of a weak bit becomes possible, and a semiconductor memory device having a weak bit does not have to be discarded, and a decrease in yield in the manufacture of a semiconductor memory device can be suppressed to a minimum.

In this embodiment, the condition parameter V
As described above, the case of the operating voltage of the semiconductor memory device has been described. However, the present invention is not limited to this. For example, the operating temperature, various test patterns, and the retention voltage are used as the condition parameters V to select the sorting condition value Vc. It is possible to decide. Note that the above retention voltage is the minimum storage holding voltage in the standby mode (when not operating) in the semiconductor memory device. Even when the retention voltage is set to the condition parameter V, the relationship between the retention voltage and the number of defective memory cells is the same as the relationship shown in FIG.

[0049]

According to the present invention, the selection condition value for each semiconductor memory device is determined in accordance with the performance characteristics of the memory cells of the semiconductor memory device. Defective semiconductor storage devices capable of selecting weak semiconductor memory devices can be effectively selected.

[Brief description of the drawings]

FIG. 1 is a configuration diagram illustrating a configuration of a defective product selection device according to an embodiment of the present invention.

FIG. 2 is a configuration diagram showing an example of a memory tester to which the present invention is applied.

FIG. 3 is a diagram showing a relationship between a condition parameter V and the number C of defective storage cells of storage cells included in the semiconductor storage device.

FIG. 4 is a flowchart illustrating an example of a processing procedure of the defective product selection device of the present invention.

FIG. 5 is a flowchart for explaining a processing procedure following FIG. 4;

FIG. 6 is a diagram showing a result of obtaining a selection condition value V of the same type of semiconductor memory device having various performance characteristics by the method according to the present invention.

FIG. 7 is a diagram showing an example of possible values of an operating voltage variable Vi and an increase / decrease variable Vj.

FIG. 8 is an explanatory diagram for explaining a problem caused by weak bits.

FIG. 9 is a diagram showing an example of performance characteristics of three semiconductor memory devices of the same type having different performance characteristics.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... Defective product selection apparatus, 2 ... Correlation data acquisition part, 3 ... Reference condition value determination part, 4 ... Selection condition determination part, 5 ... Main control part, 6
... Performance testing department.

Continued on the front page F term (reference) 2G032 AA07 AB01 AB04 AB13 AD01 AD08 AE08 AE10 AE12 AE14 AG02 AL14 3F079 AD06 CA37 4M106 AB01 AB07 AB15 AC07 CA01 CA05 CA32 DJ18 5B015 JJ00 RR02 5L106 AA02 DD22 DD24 DD25 DD35 GG07

Claims (10)

[Claims] A performance test is performed on a plurality of storage cells of a semiconductor memory device with respect to predetermined condition parameters, and based on the test results, a non-defective product of the semiconductor memory device is selected. A method of performing a performance test of the storage cell for a plurality of condition values of the condition parameter to obtain correlation data between the condition parameter and the number of defective storage cells; Determining a selection condition value of the condition parameter for selecting non-defective and defective products of the device. 2. The method according to claim 1, wherein the step of obtaining the correlation data and the step of determining the selection condition value are performed for each semiconductor storage device to be selected. 3. The method according to claim 1, wherein the step of obtaining the correlation data includes performing the performance test on all of the plurality of storage cells. 4. The step of obtaining the correlation data includes the step of performing a performance test on the condition parameters of some of the plurality of storage cells, and the number of defective storage cells based on the result of the performance test. Obtaining correlation data with the condition parameter; based on the correlation data for the some storage cells,
2. The method according to claim 1, further comprising the step of: estimating correlation data between the number of defective storage cells and the condition parameters for all storage cells. 5. The step of determining the selection condition value includes the step of obtaining a reference condition value of the condition parameter reflecting an average performance of the plurality of storage cells based on the correlation data; 2. The method according to claim 1, further comprising the step of: determining, based on the reference condition value, a selection condition value for selecting non-defective products and defective products of the semiconductor storage device. 6. The step of obtaining the reference condition value includes the step of obtaining a condition value for setting a ratio of the total number of storage cells to the number of defective storage cells to a predetermined value based on the correlation data, and 5. The method according to claim 4, wherein the condition value is a condition value. 7. The step of determining the selection condition value includes the step of determining that the logarithm of the number of defective storage cells is half the logarithm of the total number of storage cells in the relationship between the condition parameter and the logarithm of the number of defective storage cells. Setting the value of the condition parameter when the reference condition value is satisfied; determining a rate of change of the logarithm of the number of defective storage cells with respect to the condition parameter in the vicinity of the reference parameter value; and the rate of change The method according to claim 6, further comprising the step of: setting a solution of a linear equation having a predetermined constant term as the selection condition value. 8. The method according to claim 1, wherein the condition parameter is an operating voltage of the semiconductor memory device. 9. The method according to claim 1, further comprising the step of, after determining the selection condition value, selecting a defective product according to the selection condition value and performing a repair process on the semiconductor storage device of the selected defective product. 13. A method for selecting a defective product of a semiconductor storage device according to the above. 10. A plurality of storage cells of a semiconductor memory device are subjected to a performance test with respect to predetermined condition parameters, and a non-defective / non-defective semiconductor memory device is selected based on a test result. A performance test unit for performing the performance test on the semiconductor storage device; and causing the performance test unit to perform a performance test on the semiconductor storage device under specified condition values, and performing the performance test on the basis of a result of the performance test. A performance test control unit for discriminating a non-defective product or a defective product of the storage cell; and outputting the condition value to the performance test control unit. A correlation data acquisition unit that counts the number of cells and acquires correlation data between the condition value and the number of defective storage cells, and from the correlation data, an average of the plurality of storage cells. A reference condition value determining unit for obtaining a reference condition value of the condition parameter reflecting performance; and a selection condition value for selecting a non-defective product or a defective product of the semiconductor storage device based on the reference condition value and the correlation data. And a sorting condition determining unit for determining a defective product.