JPS61273648A - Memory address generating circuit - Google Patents

Abstract

PURPOSE:To produce a memory address where a base and a partial address are connected to each other at high speed by providing an ALU which is used in an OR mode with a partial address together with a shift circuit and a register for the output of the ALU. CONSTITUTION:A control part 16 reads out the contents of a register Rn and supplied them to a register 12 for latching with a specific instruction. Then the part 16 supplies the contents of a register Rn+1 to a shift circuit 14 through an ALU 13 for shifting and supplies the output data of the circuit 14 to a register 15 for latching. The part 16 switches the ALU 13 to an OR mode designating state to read out the contents of a register Rn+2 to supply them to the ALU 13. Here the ALU 13 is set to an OR mode to perform the OR operation of the contents of the register 15 and the contents of the Rn+2. The output of said OR operation is supplied to the circuit 14 and the shift result is latched by the register 15. The contents of the register Rn+3 are processed in the same way and the connected memory addresses can be produced at the high speed.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a memory address generation circuit particularly suitable for accessing an image memory of an image processing apparatus.

[Technical Background of the Invention and Problem 1 Thereof An arbitrary point (arbitrary data position) in an image memory is logically indicated by X and Y coordinates, as shown in FIG.

On the other hand, the address of the image memory is generally physically allocated in the address space of the CPU, and the data is arranged as shown in Figure 4, for example, in the case of an image memory with a 512x512x8 bit configuration. Become. Therefore, the physical address for the image memory is in the form of a concatenation of X and Y addresses, as shown in FIG. In addition, in Fig. 5, the base address B that forms part of the address
is used to designate the leading position in the address space of the corresponding image memory, and for example, if there are multiple image memories, it can also be interpreted as identification information for specifying the image memory, that is, the image memory number.

Now, when handling image memory logically, X.

Of course, it is easier to handle if the Y address is separated. Therefore,
Normally (when image memory is handled logically), X and Y addresses are expressed in separate and independent forms as shown in FIG. Therefore, when actually accessing the image memory, it is necessary to convert the address into the format shown in FIG. 5 before use.

Conventionally, this conversion (that is, generation of a memory address for image memory access) has been performed using a software subroutine or the like. This caused a problem in that the image memory access speed decreased.

Therefore, there has been a demand for hardware that can generate memory addresses for image memory access at high speed.

[Purpose of the Invention] This invention has been made in view of the above circumstances, and its purpose is to specify a data location in memory where the base address and the plurality of partial addresses are specified by a base address and a plurality of partial addresses. An object of the present invention is to provide a memory address generation circuit that can generate connected memory addresses at high speed.

[Summary of the Invention] According to the present invention, a memory address that generates a memory address in which a base address and a plurality of partial addresses are concatenated, where an arbitrary data location in a memory is specified by a base address and a plurality of partial addresses. A generation circuit is provided.

The memory address generation circuit includes a storage means for storing a base address, a plurality of partial addresses, and bit length information indicating address bit lengths of the same partial addresses, and a storage means for storing the base address, partial addresses, and bit length information in a fixed order from the storage means. A reading means for reading data from the storage means; a first register for holding bit length information when the read data from the storage means is bit length information; and a first and second input terminal.
It has an LU, a shift circuit, and a second register that holds output data of the shift circuit.

The output data of the second register is provided to the first input of the ALU. A second input terminal of the ALU is supplied with read data from the storage means. The ALU is used in the second input terminal side input through mode when the data read from the storage means is a base address, and is used in the OR mode when it is a partial address.

The output data of the ALU is supplied to a shift circuit.

The output data of the first register is also supplied to the shift circuit. The shift circuit shifts the output data of the ALU in a fixed direction by the number of bits indicated by the bit length information held in the first register. The output data of the shift circuit is held in the second register. The output data of this second register is AL
is supplied to the first input of U. Then, the last address is read from the storage means and calculated by the ALU, and the result of the calculation is held in the second register via the shift circuit, so that the memory address in which the base address and a plurality of addresses are connected is stored in the second register. Desired.

[Embodiments of the invention] An embodiment of the present invention will be described below with reference to the drawings.

Note that this embodiment is applied to an image processing apparatus having a plurality of image memories, and is applied to a memory address generation circuit that generates memory addresses of the image memories.

Figure 1 shows the configuration of the memory address generation circuit.
Reference numeral 11 denotes a storage means, for example, a general-purpose register. The general-purpose register 11 includes a register Rn with a register number n, a register 6-Rn+1 with a register number n+1, and a register Rn+2 with a register number n+2.
and a register Rn+3 whose register number is n+3. 12 is the read data from the general-purpose register 11 as signal 3.
1 is the register to latch, 13 is the mode designation signal 3
This is an ALU (arithmetic logic unit) that performs arithmetic operations according to 2. 14 is a shift circuit that shifts the output data of the ALU 13 in a fixed direction, for example, to the left, by the number of bits indicated by the data held in the register 12 when the shift designation signal 33 is ON; 15 is a shift circuit that shifts the output data of the shift circuit 14 to the signal 3;
This register is latched by 4. The data held in the register 15 is supplied to the input terminal of the ALU 13. A L
Read data from the general-purpose register 11 is supplied to the B input terminal of U13. General-purpose register 11, register 1
2, the ALU 13, the shift circuit 14, and the register 15 are connected to the control section 16. The control unit 16 interprets instructions and controls each unit, and outputs the above-mentioned signals 31 to 34 as necessary, as well as a register designation signal 35 that designates the register number of the general-purpose register 11. There is.

Next, the operation of the configuration shown in FIG. 1 will be explained with reference to the operation diagram shown in FIG. 2.

In this embodiment, the general-purpose register 11 has a base address B and a Y address (Y coordinate value) in the format shown in FIG.
Additionally, four types of data are prepared in advance: an X address (x coordinate value) and bit length information W indicating the bit length W of the X and Y addresses. As for the bit length information W, 9 is used when the size of the image memory is 512x512 as shown in FIG. 3, and 10 is used when the size of the image memory is 1024x1024, for example. As shown in FIG. 1, bit length information W is prepared in register Rn in general-purpose register 11, and base address B is prepared in the next register Rn+1. Also, the Y address is in register Rn+2, and the X address is in register R.
Each is prepared for n+3. Note that the order in which the four types of data described above are arranged in the general-purpose register 11 does not necessarily have to be as described above.

In such a state, a specific instruction that uses a memory address in the format shown in FIG. 5 (this is called a two-dimensional address), that is, a two-dimensional address in which the Assume that it has been read from main memory. This specific instruction has information specifying the register number of the register in the general-purpose register 11 to be read first, for example n. The control unit 16 interprets the instruction when the instruction is read from the main memory. The control unit 16 is
If the instruction from main memory is the above specific instruction, the following ■～■
Perform the control operation according to the following steps.

Operation (2) When the instruction from the main memory is the above-described specific instruction, the control unit 16 first outputs a register designation signal 35 that designates register Rn of the general-purpose register 11.

As a result, the contents of register Rn (bit length information W) are read out. Contents of this register Rn (bit length information W)
is supplied to register 12. At this time, the control unit 16 supplies the signal 31 to the register 12. As a result, the contents of register Rn in general-purpose register 11 (bit length information W) are changed to register 1 by signal 31 as shown in FIG. 2(a).
It is latched to 2.

Operation■ Next, the control unit 16 selects the register Rn+ of the general-purpose register 11.
A signal 35 specifying 1 is output. As a result, the contents of register Rn+1 (base address B) are read out. The contents of this register Rn+1 (base address B) are the second
The signal is supplied to the B input terminal of the ALU 13 as shown in FIG. At this time, the control unit 16 controls the ALU 13 to
A mode designation signal 32 designating the OP (B input through) mode is output. As a result, the contents of register Rn+1 (base address B) in general-purpose register 11 pass through ALU 13 and are supplied to shift circuit 14 as is, as shown in FIG. 2(b). The shift circuit 14 is designated to perform a shift operation by a shift designation signal 33 from the control unit 16, and converts the output data of the A L Ll 13, that is, the base address B, to the number of bits indicated by the bit length information W latched in the register 12. Shift to the left by W.

Output data of shift circuit 14 is supplied to register 15.

At this time, the control unit 16 supplies the signal 34 to the register 15. As a result, the output data of the shift circuit 14, ie, the result of shifting the base address B to the left by W bits, is latched into the register 15 by the signal 34 as shown in FIG. 2(b).

Operation■ Next, the control unit 16 changes the mode designation signal 32 for the A L tJ 13 from the NOP mode designation state to the OR mode (
OR operation mode) Switch to the specified state. The control unit 16 then outputs a signal 35 specifying register Rn+2 of the general-purpose register 11. As a result, the contents (Y address) of register Rn+2 are read out. This register Rn+
The contents of 2 (Y address) are A as shown in Figure 2 (C).
It is supplied to the B input terminal of L U 13. On the other hand, ALU1
The output data of the register 15 is supplied to the input terminal of the register 3. At this time, the ALU 13 is set to the OR mode as described above. Therefore, the ALU 13 receives the output data of the register 15 (in this example, the W-bit left shift result of the base address B), which is the input content, and the read data from the general-purpose register 11, which is the B input content (in this example, the contents of register Rn+2). (Y address)). As a result, the data in which base address B and Y address are concatenated is lower-ordered and
13 and supplied to the shift circuit 14. The shift circuit 14 shifts the output data from the ALU 13 to the left by the number of bits W designated by the register 12, and supplies the shift result to the register 15.

At this time, the control unit 16 supplies the signal 34 to the register 15. As a result, the output data of the shift circuit 14, that is, the W-bit left shift result of the concatenated data of the base address B and the Y address, is latched into the register 15 by the signal 34 as shown in FIG. 2(C).

Operation (2) Next, the control unit 16 sets the shift designation signal 33 to the shift circuit 14 to 0FFL, thereby inhibiting the shift operation of the shift circuit 14. Then, the control unit 16 outputs a signal 35 specifying the register R 3 of the general-purpose register 11.

As a result, the contents of register R1) I-3 (X address)
is being published one after another. The contents of this register Rn+3 (X address) are supplied to the B input terminal of the ALU 13 as shown in FIG. 2(d). On the other hand, the output data of the register 15 is supplied to the input terminal of the ALU 13. At this time A L
Ll 13 is set to OR mode as described above. Therefore, ALU 13 outputs the output data of register 15, which is the input content (in this example, the W-bit left shift result of the concatenated data of base address B and Y address), and the input content from general-purpose register 11, which is the input content of B. An OR operation with read data (in this example, the X address which is the contents of register Rn+3) is performed. As a result, data in which the base address B, Y address, and X address are concatenated is outputted from the ALU 13 in a lower-ordered state and supplied to the shift circuit 14. Since the shift operation is prohibited, the shift circuit 14 supplies the output data from the ALU 13 to the register 15 as is. At this time, the control unit 16 supplies the signal 34 to the register 15. As a result, the output data of the shift circuit 14, that is, the concatenated data of the base address B, Y address, and X address, is latched into the register 15 by the signal 34 as shown in FIG. 2(d).

Through the above operations, a two-dimensional address in the format shown in FIG. 5 is obtained in the register 15.

In the above embodiment, a case has been described in which the X and Y addresses have the same address bit length, but the present invention is not limited to this. However, the bit length of the X and Y addresses is wl
, w2, and their bit length information is Wl, W2. Prior to the shift operation for base address B, bit length information W2 is loaded into the register 12, and the concatenated data of base address B and Y address is It is necessary to load the bit length information W1 into the register 12 prior to the shift operation for. Further, in the above embodiment, a case has been described in which a memory address (two-dimensional address) of an image memory is generated, but the present invention is also applicable to generation of a frame memory address necessary for accessing a frame memory of a graphic display device, for example. Simply store data in main memory, such as tree-structured data, in an N-dimensional array (N
is an integer of 2 or more).It can also be applied when the main memory address is expressed in the form of concatenated information of a base address and N types of partial addresses.

[Effects of the Invention] As detailed above, according to the present invention, in a case where an arbitrary data position in a memory is specified by a base address and a plurality of partial addresses, a memory in which the base address and a plurality of partial addresses are concatenated is provided. Address generation,
It can be performed faster than software processing.

[Brief explanation of drawings]

FIG. 1 is a block configuration diagram of a memory address generation circuit according to an embodiment of the present invention, FIG. 2 is a state transition diagram for explaining the operation, and FIG. 3 is a diagram of X and Y data positions in the image memory.
A diagram explaining the form of expression using two-dimensional coordinates, Figure 4 is CP
FIG. 5 is a diagram showing an example of assignment of image memory addresses to the address space of U. FIG. 5 is a diagram showing a physical address representation format for the image memory. FIG. 6 is a diagram showing a logical address representation format for the image memory. It is. 11...General-purpose register, 12.15...Register,
13...ALU, 14...Shift circuit, 16...
control section. Applicant's Representative Patent Attorney Takehiko Suzue Figure 3 Figure 5 Figure 6 Figure 4

Claims (2)

[Claims] (1) Where an arbitrary data location in the memory is specified by a base address and multiple partial addresses, a memory that stores bit length information indicating the address bit length of the base address, the multiple partial addresses, and the same partial addresses. means for reading out the base address, the partial address, and the bit length information from the storage means in a fixed order; 1 register, and a first input terminal and a second input terminal to which read data from the storage means is supplied, and when the read data from the storage means is at the base address, the second input terminal side input through mode is set. is used in the OR mode when the data read from the storage means is the partial address, and the output data of this ALU is
A shift circuit that shifts in a fixed direction by the number of bits indicated by the contents held in the register, and a second register that holds output data of the shift circuit and supplies the held contents to a first input terminal of the ALU, A memory address generation circuit characterized in that a memory address in which the base address and the plurality of partial addresses are concatenated is obtained in the second register. (2) The memory address generation circuit according to claim 1, wherein the partial address is an X address and a Y address of an X, Y two-dimensional coordinate address.