JPH0573303A - Processor - Google Patents

Abstract

PURPOSE:To enable a high speed reference of different bank information by providing a designation means designating the address space of the first storage means based on information indicating a unit bank and information indicating the position of the register in the unit bank. CONSTITUTION:The contents of registers of banks 2 to 5 of a bank RAM 1 are stored in a general register group 3. When referring to the content of the register R2 of a bank 6 for interrupt routine different from this bank, the bank number 6 is transferred from a general register Rn where the bank number 6 is set to a shift register SR 1. Simultaneously, the register number 2 of the register SR2 is supplied to one input of a computing element 4. The address of the operation result is sent to an address latch 81 of a BIU 8, and the bank RAM 1 is accessed. The register R2 of the bank 6 is selectively designated, and the reference of the contents is enabled by outputting the held content to the data latch 82.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a processor having a bank structure register, and more particularly to a processor which refers to a register of another bank without switching banks.

[0002]

2. Description of the Related Art In a conventional processor, its CP
The number of general-purpose registers used in U is limited from the viewpoint of reducing the chip area. For this reason, there is one in which a RAM or the like is formed into a bank structure so as to include a plurality of sets of general-purpose register groups.

In a processor employing such a bank structure, for example, as shown in FIG. 4, a bank "0" of a bank register 102 is assigned as a general-purpose register group 101 for a main routine, and interrupt processing is performed. Bank register 1 as general-purpose register group 103 for routine
No. 02 bank “3” is assigned. Each bank of the bank register 102 is selectively designated by the contents of the bank designation register 104.

In the allocation of the general-purpose register group 103, the routine executed when "0" is set in the bank specifying register 104, the bank "0" is selected and specified, and the main routine is executed. When it is desired to refer to a register in a bank different from the bank used in, for example, to refer to the information held in the register R6 of the general-purpose register group 103 in the bank "3" for the interrupt processing routine, The procedure is shown in.

First, "3" indicating the bank "3" for the interrupt processing routine is written in the bank designation register 104,
The bank of the bank register 102 is switched from the bank “0” to the bank “3”. After that, the information held in the register R6 of the bank "3" is written in the information storage area other than the bank. Next, "0" is written in the bank designation register 104, the bank of the bank register 102 is switched from the bank "3" to the bank "0" again, and the bank is changed to the bank "0".
Return to. In such a state, the information held in the register R6 of the bank "3" written in the information storage area other than the bank is referred to.

As described above, when referring to the information of different banks, it is necessary to perform the switching operation of the banks twice, which complicates the operation processing for that purpose, and
It took me a long time to refer.

On the other hand, as another procedure, there is a method using a technique of copying information. This method is for bank "3"
The information of the register R6 of the above is copied to the register R6 of the bank "0". However, in this method, in order to prevent the contents of the copy destination from changing, it is necessary to copy the contents of the register R6 of the bank "0" in advance. Therefore, it takes time to save the information, and it takes time to refer to the information of different banks, as in the above procedure.

[0008]

As described above,
In a conventional processor having a bank structure, when trying to refer to information of a bank different from the bank currently in use, the processing for that becomes complicated, the processing time is reduced, and the speed of instruction execution is increased. Had been an obstacle.

Therefore, the present invention has been made in view of the above, and an object thereof is to refer to information of different banks at high speed by a simple method without increasing the size of the configuration. It is to provide a possible processor.

[0010]

In order to achieve the above object, the present invention provides a first unit bank comprising a plurality of registers to which consecutive addresses are allocated, which are arranged continuously in an address space. Based on information indicating a unit bank to which the register belongs and information indicating a position of the register in the unit bank. A plurality of designation means for designating on the address space of the first storage means, reference means for referring to the information held in the register designated by the designation means, and a plurality of processes corresponding to the processing being executed. Second storage means to which register information in the unit bank is transferred.

[0011]

In the above structure, the present invention allocates consecutive addresses to the registers in each bank, and based on the information for distinguishing the unit bank and the information indicating the position of the register within the unit bank, I'm trying to address the register.

[0012]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a diagram showing a configuration of a bank RAM of a processor according to an embodiment of the present invention.

In FIG. 1, the bank RAM1 has 256 banks (bank "0" to bank "25" in the memory space.
5 ") are arranged in succession. Each bank is composed of four 16-bit length registers and eight 8-bit length byte registers (R0 to R7). Each register in the bank
Start address "00" in the address space of bank RAM1
00 "are sequentially assigned, and the final address indicating the register R7 of the bank" 255 "is" 07FF ". For example, the address" 0000 "is assigned to each of the registers R0 to R8 of the bank" 0 ". To “0007” are assigned, and the number of addresses (scaling) assigned to one bank is “8”.

In the bank RAM 1 having such a configuration, as shown in FIG. 2, a group of general-purpose registers for the main program are assigned to banks "2" to "5".
General-purpose register group for interrupt routine 1 is bank "6"
The general-purpose register group for the interrupt routine 2 is allocated to the bank “9”, and the general-purpose register group for the interrupt routine 3 is allocated to the banks “10” to “13”. Assigned to.

In such a bank structure, the processor has an addressing mode for selecting and specifying the register of each bank, and the register is selected and specified by the following formula and the contents are referred to.

SpcR + Base × SS + disp Here, “SpcR” is a value indicating the address of the first bank in the address space of the bank RAM and is the first address. Therefore, the value of "SpcR" is a variable according to the arrangement of banks in the address space, and is "0" in the arrangement example shown in FIG. “Base” is the number of the bank to which the register to be referred belongs.
“SS” is the number of addresses (scaling) assigned to one bank, and has a value according to the number of registers included in one bank, and is “8” in the arrangement example shown in FIG. “Disp” is a value indicating the number of the register in the bank.

The addressing mode for addressing a register by such a calculation formula is executed in the processor configuration as shown in FIG. 3, for example.

In FIG. 3, the processor includes a bank RAM1 having the configuration shown in FIG. 1 and a general-purpose register group 3 connected to the bank RAM1 via a dedicated transfer path 2.
And an arithmetic unit 4 for executing the arithmetic operation of the above-described calculation formula, and a shift register SR1, for operating and holding the input of the arithmetic unit 4.
It is configured with SR2 as a main component.

In such a configuration, the main program is currently being executed, and the general-purpose register group 3 stores the contents of the registers of the banks "2" to "5" of the bank RAM1. When trying to refer to the contents of a register in a bank different from the currently used main program bank "2" to bank "5" while the main program is being executed, for example, When referring to the contents of the register R2 in the bank "6" for the interrupt routine 1, the addressing mode described above is executed.

When this addressing mode is executed, first, the general register Rn in the general register group 3 in which the bank number "6" of the bank "6" to which the register R2 to be referred belongs is set is held. The bank number “6” that is being transferred is transferred to the shift register SR1 via the X bus 5 as “Base”. At the same time, the register R2 set in the queue register (not shown)
Of the register number "2" is given to one input of the arithmetic unit 4 via the Y bus 6 and the shift register SR2 as "disp".

The bank number "6" transferred to the shift register SR1 is shifted to the left by 3 bits. As a result, the bank number “6” is multiplied by 8 to calculate Base × SS (6 × 8) in the above calculation formula. The calculated value is given to the other input of the arithmetic unit 4.

When both inputs are given to the arithmetic unit 4, the arithmetic unit 4 adds the register number “2” which is “disp” of one input and “48” which is “Base × SS” of the other input. It As a result, the above calculation formula, SpcR
The value of + Base × SS + disp is obtained as “50”. As a result, the address value in the addressing mode is calculated.

The address of this operation result is transferred from the operation unit 4 to the address latch 8 ₁ of the bus interface (BIU) 8 via the Z bus 7, and the bank RAM 1 is accessed by the transferred address. As a result, the register R2 of the bank "6" is selected and designated, and the content held in the register R2 is output to and stored in the data latch 8 ₂ of the bus interface 8. By reading the contents the stored in the data latch ₈₂ to the Y bus 6, it is possible to see the contents of register R2 of the bank "6" in the bank RAM 1.

As described above, according to the addressing mode, which is a feature of the present invention, the information to be referred to by performing the transfer of two or three pieces of information, the 3-bit shift operation, and the addition processing once. Therefore, it is possible to refer to the information in another different bank at high speed without switching the bank as in the conventional case, in the configuration normally provided in the processor.

In the above calculation formula, "Spc
When the value of “R” is not “0”, the addressing can be performed by one addition by using the 3-input arithmetic unit.

[0027]

As described above, according to the present invention, the register in each bank is addressed and selected by the addressing mode, so that the bank can be switched according to the configuration of the normal processor. However, it becomes possible to access and refer to the contents of the register in another different bank. Therefore, this reference processing can be performed quickly and easily.

[Brief description of drawings]

FIG. 1 is a diagram showing a configuration of a bank RAM of a processor according to an embodiment of the present invention.

FIG. 2 is a diagram showing a correspondence relationship between processing routines executed by a processor according to an embodiment of the present invention and banks.

FIG. 3 is a diagram showing a configuration of a processor according to an embodiment of the present invention.

FIG. 4 is a diagram showing a conventional bank switching method.

[Explanation of symbols]

1 bank RAM 2 transfer path 3 general purpose register 4 arithmetic unit 5 X bus 6 Y bus 7 Z bus 8 bus interface 8 ₁ address latch 8 ₂ data latch

Claims (1)

[Claims] 1. A first storage means in which a plurality of unit banks, each of which is composed of a plurality of registers to which consecutive addresses are allocated, are consecutively arranged in an address space, and the information holding information to be referred to. A designation for designating a register of the first storage means on the address space of the first storage means based on information indicating a unit bank to which the register belongs and information indicating a position of the register in the unit bank. Means, reference means for referring to the information held in the register designated by the designating means, and second storage for transferring the information of the registers in the plurality of unit banks corresponding to the processing being executed. A processor having means.