GB2282470A - Expanded memory management for multi-tasking environment. - Google Patents

Abstract

A processor (10) with a memory management arrangement (12) for mapping a logical address from the processor to an expanded physical address of memory (15, 16), thereby allowing the processor to address a larger memory space than is otherwise possible using its finite logical address capability. In one aspect of the invention, program code which defines a task and memory required by that task are mapped by the memory management means to a common set of logical addresses (shared memory space 55). In another aspect, stack memory is located at logical addresses (52) which are mapped to different subsets of physical addresses (private memory 102, 104) and the stack memory is divided into separate portions, a portion of stack memory being provided for different tasks. <IMAGE>

Description

A PROCESSOR ARRANGEMENT WITH MEMORY MANAGEMENT Field of the Invention This invention relates to a processor arrangement having memory management means for mapping a logical address from a processor to an extended physical address of the memory, sometimes referred to as "bank switched memory", thereby allowing the processor to address a larger memory space than is otherwise possible using its finite logical address capability.

In at least one embodiment, the arrangement described is particularly applicable, for example, to use in data modems.

Background to the Invention

Microprocessors, such as Motorola'skMC68HC11 are available with 16 bits of memory addressing bus. Such a microprocessor can address 64K of address space. All microprocessors have a finite limit to the logical address space they can address.

Techniques are available for extending the physical memory that can be used with a microprocessor by utilizing various forms of memory management means.

An example of means for memory management is the Motorola memory management circuit MDI5000. This device converts a 16-bit address to a 20-bit address. The principle of the conversion is by converting the four most significant bits of the logical address to 8 most significant bits of the physical address. The MDI 5000 has 16 internal registers: MM0 MMF. Each register is referred to by 4K of logical address space.

This procedure of switching between memory maps is called bank switching.

When using banked switched memory, the logical memory map is conceptually divided between shared memory and private memory. Shared memory is not bank switched, but is always mapped directly between given logical addresses and corresponding physical addresses. Private memory, on the other hand, is bank switched and can only be used when the memory management unit maps the logical address base to that particular private memory address space.

It is normal to use shared memory for such uses as stack random access memory (RAM).

The Motorola radio operating system ROS is a kernel of operating system software by Motorola for the MC68HCl1 microcontroller. This operating system, as is common with operating systems, provides that stack memory is located in common address space.

Considering an example where 2 K of stack memory needs to be provided for each individual task of a multi-tasking system, where the system has, for example, 20 tasks, 40 K of the available 64 K of valuable shared memory would be used for stack memory alone. Although not every task will require 2 K of stack memory, it is necessary to provide uniform size of stack memory adequate for every task.

It is common to provide the code for a task in bank switched (private) memory. That task may require reading to and writing from RAM memory and it is normal to provide RAM memory in shared memory space. There is quite simply not enough total logical memory space to achieve all these arrangements together. Shared memory is particularly valuable and detailed consideration needs to be given to the locating of the various tasks and RAM memory so as to work within the limited shared memory space available.

Additionally, it is useful to retain large blocks of memory for different functions, and to avoid excessive switching between small blocks of memory.

The present invention addresses these problems.

Summarv of the Invention According to a first aspect of the invention, a microprocessor arrangement is provided comprising: a processor arranged to address 2M logical addresses and arranged to perform multiple tasks; a memory comprising 2N physical addresses, where N is greater than M; and memory management means for converting an address of M bits to an address of N bits . The memory comprises first and second sets of physical addresses and the processor is arranged to address always the first set of physical addresses by means of a first set of logical addresses whereby the first set of physical addresses provides shared memory space which is shared by different tasks performed by the processor and to address selected subsets of a second set of physical addresses, under control of the memory management means, by means of a second set of logical addresses. The arrangement is characterized in that program code which defines a task and RAM memory required by that task are located at physical addresses within the second set of physical addresses and are mapped by the memory management means to a common set of logical addresses.

In this manner, a task and its RAM memory share the same logically address space. The memory management means are arranged to switch, in response to a task which requires use of RAM memory associated with the task, from mapping the common set of logical addresses to the physical addresses of the task to mapping the common set of logical addresses to physical addresses of the associated RAM memory.

Program code for reading from and writing to the RAM memory may be located in shared address space. The instructions for achieving this are very much shorter than the entire task and the same instructions can be used regardless of the task being performed. The code for switching between the task and its associated RAM memory may also be stored in the shared memory, thereby enabling the Task to be recalled when the use of the RAM memory has been completed.

The arrangement is particularly useful where the RAM memory is used by the processor as first-in, first-out (FIFO) memory. The arrangement is particularly applicable to use in, for example, a data modem, or other arrangement which has an input port and an output port, where the RAM memory is used as buffer memory for buffering data, information or messages transferred between the ports and where the task controls the buffering. In such arrangements, the RAM memory is used intensively, but at somewhat infrequent intervals, so that the switching between the task and its memory is not excessive.

In a second aspect of the invention, the processor arrangement comprises: means in the memory management unit for simultaneously switching from, in a first context, mapping of logical addresses to the program code for the first task and the corresponding portion of stack memory and, in a second context, mapping of the same logical addresses to the program code for the second task and the corresponding portion of stack memory.

In this manner, only as much logical stack memory space needs to be set aside as will be required by the largest portion of stack memory required by any of the tasks.

Switching between tasks is also referred to as context switching. The present invention places emphasis on a memory management structure which is organised by context. In the preferred embodiment, the switching from a first context to a second context involves changing of the mapping of the stack memory as well as changing of the mapping of the program code memory in which the task is located. The arrangement also introduces the concept of a context queue, that is to say FIFO memory which is associated with a particular task and is therefore only used within a particular context.

Brief Description of the Drawings 'Fig. 1 shows a hardware block diagram of a processor arrangement with memory management in accordance with the preferred embodiment of the invention.

Fig. 2 shows a memory map for the logical address space of a processor of Fig. 1 and Fig. 3 is a memory map showing logic addresses on the left hand side and alternative physical addresses on the right hand side.

Fig. 4 is a composite diagram showing, on the left-hand side portions of the memory map of Fig. 2, in the centre different mapping arrangements of mapping of the task private code of the memory map and, on the right-hand side different arrangements of mapping of the stack and Far RAM memory of the memory map.

Detailed Description of the Preferred Embodiment Referring to Fig. 1, a microprocessor 10 is provided, such as a Motorola MC68HCii connected by a 16-bit address bus 11 to a memory management unit 12, such as a Motorola MDI5000. The memory management unit 12 is connected by 20-bit buses 13 and 14 to 128 K of RAM memory 15 and 256 K of ROM memory 16 respectively. The memory management unit 12 also has chip select outputs 17 for selecting different circuits 18 which include a first in/out port 19 and a second in/out port 20. As an example, the port 19 may be connected to a computer terminal and the port 20 may be connected to a radio. Connected between the microprocessor, the RAM memory, the ROM memory and the various chips 18 is a data bus 22.

In operation, the microprocessor 10 always addresses the memory management unit 12 via its address bus 11. The particular physical memory being addressed by address bus 11 is determined by the memory management unit 12.

The memory management unit 12 has 16 internal registers: MMO MMf. Each register is referred to by 4 K of logical address space. The value of each register can be from 00 to FF.

The first nibble of the logical address identifies the register number (0-F). The second, third and fourth nibbles remain the same.

Example: MMO refer to addresses 0000 to OFFF.

MM5 refer to addresses 5000 to 5FFF.

The conversion of the 4 bits to 8 bits is done by internal MDI5000 registers that can be assigned by the program at any time.

Examples: Logical Address = 1234.

MM1 value is AB.

The physical address will be AB234.

Logical Address = EB34.

MME value is C3.

The physical address will be C3B34.

When addressed, the particular byte of memory receives data or outputs data from or to the data bus 22.

Referring to Fig. 2, a memory map of the logical memory space that can be addressed on address bus 11 is shown. There is 64 K of logical address space. The logical addresses are shown on the left-hand side. In the figure, the address space is shown in portions of 4 K. The shaded area (51, 54, 56) is shared memory, which is always mapped by the memory management unit 12 to the same physical address space in RAM 15 or ROM 16, or on chip selector lines 17. The remainder of the memory space (52, 53, 55) is bank switched memory, which can be mapped by the memory management unit 12 to various different areas of RAM and ROM memory.

The memory map is arranged as follows. The first 4 K of memory address the chip select lines 17.

The next block of 4 K is used for stack memory and private global parameter storage. These are all stored in RAM memory 15. The third block is used for task FAR RAM for task mapping. The next three sections from 3XXX to 5XXX are shared RAM memory for shared global parameter storage.

The address space from 6XXX to 9XXX (16 K in total) is used for task private code stored in ROM memory 16. The remaining memory from AXXX to FXE is used for shared code, such as start-up code and other features described below.

Constant ROM mapping Logical addresses A000-FFFF are mapped to physical addresses FA000-FFFFF. Thus MMA to MMF are assigned to constant values: MMA is assigned to FA, MMB is assigned to FB, MMC is assigned to FC, MMD is assigned to FD, MME is assigned to FE, MMF is assigned to FF.

This area contains all Interrupt Service Routines, and all shared function calls, i.e. functions that are called by an Interrupt Service Routine or by a task or functions that are called by two or more tasks.

For example: memcpy0, memcmpO.

Constant RAM mapping Logical addresses 3000-5FFF are mapped to physical addresses BD000-BFFFF. Thus MM3 to MM5 are assigned to constant values: MM3 is assigned to BD, MM4 is assigned to BE, MM5 is assigned to BF.

This area contains all global variables which are referred by Interrupt Service Routines or shared by two or more tasks.

Dvnamic RAM mapping Logical addresses 1000-2FFF are mapped to any physical addresses between A0000-BFFFF.

This area is divided into 2 sections: 1100-1FFF logical address is the Task Stack Area and the task's private global variables.

2000-2FFF Task FAR memory (RAM/ROM) is used for task mapping to any 4 K RAM/ROM physical mapping.

For example: If task &num;1 wants to look at address Oxe4111 and that address is not not mapped by any 4k window it can use that window to access that address.

Dvnamic ROM mapping Logical addresses 6000-9FFF are mapped to physical addresses C0000-F9FFF.

This area is used by Tasks private Code or read/write to 16 K RAM queue.

Notes: Task's private code size is always less than 16 K.

Referring now to Fig. 3, this figure shows, on the left-hand side, the bank switched portions of the memory map of Fig. 2 and, on the right-hand side, Fig. 3 shows the mapping of those portions of the logical memory map to the different areas of physical memory.

At the top left of the figure, there is shown logical memory address space 100 which the microprocessor 10 uses for addressing stack memory.

Stack memory is a push-down pop-up type of random access memory (RAM) and is used for purposes such as storing of values of variable parameters etc.

Immediately following memory space 100 is logical memory space 101, which is used for task Far RAM memory.

As is shown on the right-hand side of Fig. 3, logical memory space 100 and 101 is mapped, for example, to physical memory space 102 and 103 in a first context and physical memory space 104 and 105 in a second context. In other words, when Task 1 is running, the processor is operating in the first context and memory space 100 and 101 is mapped to memory space 102 and 103 and when Task 5 (for example) is running, memory space 100 and 101 is mapped to physical memory 104 and 105. Examples of the addresses of memory space 102, 103, 104 and 105 are given in the figure.

A thick vertical line 110 is illustrated, representing context switching between the first and second contexts (between Task 1 and Task 5). A context switch involves commencement of a new task and simultaneous rearrangement of the mapping conducted by memory control unit 12. A context switch can, for example, be caused by an interrupt received at processor 10, where the interrupt causes the initiating of Task 5 at some point in time during the running of Task 1. Similarly, Task 1 may, from time to time, itself initiate a context switch. There may be a context switch back to Task 1 upon the completion of Task 5. Many other examples can be considered.

As shown in the lower half of Fig. 3, task private code memory space 120 can be mapped by memory control unit 12 to Task 1 private code memory space 121 or Task 5 private code memory space 122, which is physical memory in ROM 16.

As is illustrated by the line 110, context switching involves remapping of memory space 120 from physical memory space 121 to physical memory space 122, thereby enabling processor 10 to switch from running of Task 1 to running of Task 5. Examples of physical addresses of memory space 121 and memory space 122 are given in the figure.

Fig. 3 illustrates a feature of the invention, which is that the stack memory considered in total is divided into separate portions, a portion of stack memory being located in physical memory space 102 at addresses A1000 to A1FFF and another portion being located in physical memory space 104 at addresses A5000 to A5FFF. These respective portions of the total stack memory correspond to their respective Tasks 1 and 5. Thus, when a task is running, the stack logical memory 100 addresses the specific portion of stack memory allocated to that task. This is made possible by the fact that modularised code, as is used in a multi-tasking system, generally comprises self-contained modules or tasks, each of which defines and requires its own set of variable parameters.

If there are variable parameters required by more than one task, these must be stored in shared RAM memory elsewhere. The overall burden on the shared RAM memory is enormously reduced.

Referring to Fig. 4, this figure, in addition to the features of Fig. 3, represents the sharing of the task private code logical address space 120 between task code on one hand and FIFO/RAM memory on the other hand.

The task and its corresponding FIFO memory are alternately mapped within the same context.

Logical address space 100, 101 and 120 is illustrated as shown in Fig.

3. Physical address space for task stacks, task globals and task Far RAM (e.g. 102 and 103) is also shown. The mapping of physical address space 102 and 103 is as described with reference to Fig. 3. Also shown in the logical address memory are Read and Write instructions 150 and Return instructions 151.

In the centre of Fig. 4, there is shown, from top to bottom, a sequence of events in time. Thus, box 200 represents a first context, box 201 represents a second context and box 202 represents returning to the first context. A context switch event occurs between these contexts. Within the first context 200, that is to say the context of Task 1, task private code 120 can be mapped to one physical address space 121 or, alternatively, to 16 K of FIFO queue memory located in RAM 15. This queue memory 210 is located at physical addresses B0000 - B3FFF; it is standard RAM memory, but is used as a FIFO queue in a manner that is described below.

Memory space 211 is shown at which is stored the code for Task 2, in the same manner as is described with reference to Task 5 in Fig. 3. Task 2 does not require the use of FIFO memory and no such memory is shown in the context 201 of Task 2.

Within box 202, box 210 is repeated, thereby representing the switching back again to mapping of Task private code 120 to the 16 K FIFO queue memory 210. Also within box 202 is again shown Task 1 private code physical memory space 121.

The case will be considered where Task 1 controls the inputting of data from input port 19 and the outputting of that data to output port 20. For example, a block of data may be transferred from port to port in a larger packet of data.

As illustrated by box 121, the memory management unit 12 is mapping the Task private code logical memory space 120 to Task 1 private code physical address space 121. At some point during the running of the task, a block of data needs to be input from port 19 and stored in FIFO queue memory 210. When this requirement occurs, memory management unit 12 changes from addressing logical address space 120 from physical address space 121 to physical RAM address space 210. Once the mapping change has occurred, data is written into the FIFO queue using instructions 150 which are located in shared memory space.

During the course of this operation, an interrupt occurs causing the initiation of Task 2. A context switch takes place from the context 200 of Task 1 to the context 201 of Task 2. The context switch involves a remapping of the Task private code 120 to the Task 2 physical address space 211. Simultaneously, a re-mapping takes place of the stack and Far RAM logical memory space 100 and 101 to the physical memory space 220 and 221 of the stack and globals and the Far RAM for Task 2.

When Task 2 has completed its operation, a context switch again occurs back to the context of Task 1, as illustrated by box 202. Since Task 1 was, at the time of the interrupt, performing the writing operation into the FIFO queue memory 210, this operation is continued and task private code memory space 120 is mapped to RAM memory 210. When the writing operation is completed, command 151 in the shared memory space causes a return to Task 1 code, which is put into effect by memory management unit 12 by re-mapping task private code memory space 120 to Task 1 private code physical address space 121, as shown at the bottom of Fig. 4.

Simultaneously, a remapping occurs of the stack and Far RAM logical memory space 100 and 101 to the corresponding physical memory space 102 and 103.

Thus there has been described a complete operation involving the running of Task 1, the switching from Task 1 to the use of RAM memory as a FIFO queue, the interruption of the use of the queue to the running of a second task, the completion of that task and the return to the use of the queue and the completion of the use of the queue and the return to the task code that initiated the use of the queue.

The operation is similar in the case of reading from the FIFO queue to the output port 20.

In the case illustrated, Task 2 has a higher priority than Task 1.

Further examples can be considered where further tasks have even higher priority, so that many context switches can occur before the operation returns to the original task. Similarly, one or more of the higher priority tasks may require the use of FIFO queue memory.

The operation is not limited to the use of the processor in a modem.

Many other applications can be considered, particularly those that require handling of messages or packets of data, for example, a paging system controller or a node of a packet switched data network. Other applications outside the field of message handling can also be considered, but the invention, in at least some of its aspects, finds particular application in cases where the RAM memory 210 is used intensively in a series of operations, where those operations can be stored compactly in shared memory space 150.

Thus there has been described an arrangement where an area of logical memory space that has already been allocated to a task is reused for queue space for such operations as in-bound messages, out-bound messages and acknowledgements. When a task uses the queue, it does so through a queue interface library which resides in the shared memory. At that moment, the calling task does not have to be in the active segment of the logical address space, so the active segment can be used for the data of the queue.

In addition, an arrangement has been described in which stack memory can be located wherever a programmer wishes it to be. A different stack can be used privately by each task and the same method is used for switching the stacks as is used for switching the task code in the course of context switching. This allows an operating system to handle a large memory system with many tasks. It allows a software programmer to expand the usage of the stack beyond previous physical limitations. It also makes the division between tasks very clean and protected, because each task has its own private stack which no other task can interfere with.

Claims (7)

Claims

1. A processor arrangement comprising: a processor (10) arranged to address 2M logical addresses and arranged to perform multiple tasks, a memory (15, 16) comprising 2N physical addresses, where N is greater than M, memory management means (12) for converting an address of M bits to an address of N bits where the memory comprises first (51, 54, 56) and second (52, 53, 55) sets of physical addresses and the processor is arranged to address always the first set of physical addresses by means of a first set of logical addresses whereby the first set of physical addresses provides shared memory space which is shared by different tasks performed by the processor and to address selected subsets of a second set of physical addresses, under control of the memory management means, by means of a second set of logical addresses, characterized in that program code (121) which defines a task and RAM memory (210) required by that task are located at physical addresses within the second set of physical addresses and are mapped by the memory management means to a common set of logical addresses (120).

2. A processor arrangement according to claim 1, wherein the memory management means are arranged to switch, in response to a task (121) which requires use of RAM memory (210) associated with the task, from mapping the common set of logical addresses to the physical addresses of the task to mapping the common set of logical addresses to physical addresses of the associated RAM memory

3. A processor arrangement according to claim 2 wherein program code for switching between a task and its associated RAM memory is located at physical addresses within the first set of physical addresses, and the processor is arranged to address this program code to perform said switching.

4. A processor arrangement according to any one of the preceding claims, wherein program code (150) for reading from and writing to the RAM memory is located at physical addresses within the first set of physical addresses, and the processor is arranged to address this program code for operating the RAM memory while the common set of logical addresses are mapped to the RAM memory.

5. A processor according to any one of claims 1 to 4 wherein the processor is arranged to use the RAM memory as first-in, first-out memory.

6. A data modem including a processor according to any one of the preceding claims, and having an input port and an output port, wherein the RAM memory is used as buffer memory for buffering messages transferred between the ports and the task controls said buffering.

7. A processor according to claim 6, further comprising means in the memory management unit for simultaneously switching from, in a first context, mapping of logical addresses to the program code for the first task and the corresponding portion of stack memory and, in a second context, mapping of the same logical addresses to the program code for the second task and the corresponding portion of stack memory.

7. A processor arrangement comprising: a processor (10) arranged to address 2M logical addresses and arranged to perform multiple tasks, a memory (15, 16) comprising 2N physical addresses, where N is greater than M, said memory including stack memory for storing stack parameters/code/data for the tasks, memory management means (12) for converting an address of M bits to an address of N bits where the memory comprises first (51, 54, 56) and second (52, 53, 55) sets of physical addresses and the processor is arranged directly to address the first set of physical addresses by means of a first set of logical addresses whereby the first set of physical addresses provides shared memory space which is shared by different tasks performed by the processor, and to address the memory management means by means of a second set of logical addresses whereby the second set of logical addresses is mapped to subsets of the second set of physical addresses, program code for first and second tasks being stored at first (121) and second subsets (122) of the second set of physical addresses, characterized in that the stack memory is located at logical addresses (100) within the second set of logical addresses (52) and is divided into separate portions (102, 104), a portion of stack memory being provided for each of the first and second tasks.