JPH06348590A - Main storage device and memory card - Google Patents

Abstract

PURPOSE:To provide a main storage device of a small-sized computer such as a work station with nearly the same performance as the main storage device of a large-sized computer with a small physical quantity. CONSTITUTION:Plural storage parts (1-A0-1-A3, and 1-B0-1-B3) are constituted by providing with four groups of storage parts made of a couple of two storage parts (1-A0, 1-B0...), and the data lines of the couples of respective storage parts are made common and connected to a data part 4. A host computer 4 sends a request to access the main storage device to a control part 2. The control part 2 receives the access request and activates a storage part 1 through a control signal 2000-A or 2000-B. The control signal 2000-A activates the storage parts 1-A0-1-A3 and the control signal 2000-B activates the storage parts 1-B0-1-B3. Data read out of the storage parts 1-A0 and 1-B0 are inputted to the data part 3 through a common data line 3000-0 and the data part 3 switches the read data coming from the respective data lines 3000-0, 3000-1...3000-3 in order and transfers them to the host computer 4 through a data line 4000.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a computer system and its main memory, and more particularly to a main memory suitable for realizing high speed memory access.

[0002]

BACKGROUND OF THE INVENTION In the field of computer systems, especially workstations, the advent of high performance RISC processors has significantly improved their performance. However, R
While the performance of the ISC processor has been rapidly improved, the performance of the main memory is almost the same, so that the main memory becomes a performance bottleneck, and the improvement of the overall performance is reaching the ceiling. In other words, considering the case where the RISC processor requests the necessary data from the main memory, the processor must wait for the execution of the program until the data arrives from the main memory, and this wait time is necessary. Moreover, the computing performance is significantly reduced. This waiting time is now occupying 50% of the total processing time, and there is a problem in that the overall processing performance does not improve even if the performance of the processor is improved.

To solve this problem, it is necessary to improve the access performance of the main storage device. As a means for improving performance, there are a multi-way parallel access method and a high-speed page mode high-speed continuous access method. The parallel access method can improve the performance by increasing the number of memory devices operating in parallel. The performance is proportional to the physical quantity and is effective in a large and high performance computer system. On the other hand, the high-speed continuous access method has an advantage that a high-performance main storage device can be constructed with a smaller amount of material than the parallel access method, and is suitable for a small computer. However, in the high-speed continuous access method, since it is premised that the memory access is divided into a plurality of times, there is a limit to the performance improvement, and it is not sufficient in a performance-oriented computer system.

As a conventional example in which a compact and high-performance main memory device is realized by an intermediate method between the parallel access method and the high-speed continuous access method, Rob Honing, Wraith Johnson, et al.・ Low Cost PESC RISC Desktop Workstation "IEEE 1991 208-2
Page 13 (Rob Horning, Leith Jo
System Design for hson et al.
a Low Cost PA-RISC Deskto
p Workstation (IEEE, 1991, p
208-p213)). In this conventional technique, two banks are operated in a high speed page mode, and read data of the two banks are alternately switched and read. If the row addresses of the read data are the same, high speed data reading is possible.

[0005]

However, the above-mentioned conventional technique has a problem that the performance deteriorates when the read data has different row addresses. Further, since the operation is performed in the high speed page mode, it is premised that the memory access is divided into a plurality of times, and there is a problem that there is a limit to the performance improvement.

An object of the present invention is to provide a compact and high-performance main storage device which has a performance equivalent to that of the parallel access system with a small amount of material and can be used for a small computer.

[0007]

SUMMARY OF THE INVENTION It is an object of the present invention to standardize the data lines of a plurality of sets of memory elements that can operate in parallel and to output read data from the plurality of sets of memory elements to the common data line in order. This is achieved by adopting a control configuration.

[0008]

It is assumed that the main memory device is composed of two memory elements a and b, for example. In this case, the control signal A accesses the memory element a, and the control signal B accesses the memory element b. Then, by accessing the memory element b at a time half the access interval of the memory element a, data is output to the common data line without interruption. Therefore, the data line is halved, and a high-performance main memory device can be realized with a small amount of material.

[0009]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram of a computer system according to an embodiment of the present invention, which comprises a host computer 4 and a main storage device. The main storage device includes a control unit 2, a data unit 3, and a plurality of storage units (1-A0 to 1-A3, 1-B0 to 1-B3). The plurality of storage units are a pair of two storage units (1-
4 sets of A0 and 1-B0, and so on) are provided, and the data lines of each storage unit pair are connected in common to the data unit 4.

The host computer 4 issues an access request to the main storage unit to the control unit 2. The control unit 2 receives the access request and receives the control signal 2000-A or the control signal 20.
The storage unit 1 is activated via 00-B. Control signal 2
000-A activates the memory units 1-A0, A1, A2, A3, and the control signal 2000-B controls the memory units 1-B0, B1 ,.
Activate B2 and B3.

The data read from the storage units 1-A0 and B0 is taken into the data unit 3 through the common data line 3000-0. Similarly, the read data of the storage units 1-A1 and B1 is transmitted via the data line 3000-1, and the read data of the storage units 1-A2 and B2 is transmitted to the data line 3000-.
The read data of the storage units 1-A3 and B3 is loaded into the data unit 3 via the data line 3000-3 via the data line 3000-3. The data section 3 includes data lines 3000-0, 1, 2, 3
The read data coming from the
00 to the host computer 4.

When writing data to the main storage device 1, the host computer 4 writes the write data to the data line 40.
00 to the data section 3 in a time division manner, and the data section 3
The received write data to the data line 3000-0,
The output is distributed to 1, 2, and 3.

FIG. 2 is a detailed configuration diagram of one storage unit. The control signal 2000 is captured by the timing generation circuit 10. The timing generation circuit 10 is the RAS 100.
0, CAS 1001, WE 1002, ADR 1003 are generated, and the storage element unit 11 is driven. When reading, the storage element unit 11 outputs read data to the data line 3000. When writing, the storage element unit 11 takes in write data from the data line 3000.

In the present embodiment, the storage unit 11 is composed of at least one memory card. This storage element section 11
The external appearance of is shown in FIG. The storage element unit 11 includes a memory card 111 having a plurality of random access memories 110 mounted therein.

In general, random access memory 11
0 is divided into several types according to access performance. The memory card 111 outputs an access performance identification signal 1111 for identifying the access performance of the mounted random access memory 110.

FIG. 4, storage element section 11 and memory card 1
11 is a diagram showing a relationship between an access performance identification signal 1111 and FIG. The memory element unit 11 is at least one memory
The access performance identification signal 1111 of one memory card 111 in the card 111 is pulled out to the outside.

FIG. 5 is a diagram showing how the access performance identification signal 1111 output from the storage element section 11 is wired. The access performance identification signal 1111 output from the storage element unit 11 is the timing generation circuit 10
And is output from the storage unit 1. Access performance identification signal 1111 output from the plurality of storage units 1
Is supplied to the control unit 2, the data unit 3, and the host computer 4.

FIG. 6 shows that the base of the memory card 111 is
Indicates that the colors are classified according to access performance. In the figure, memory card 111-U and memory card 111-
V has a different access performance, and the base has a different color.

FIG. 7 shows that a part of the base of the memory card 111 is color-coded according to access performance. Memory card 111-U and memory card 1 in the figure
The 11-V has different access performance, and a part of the base is colored with another color.

By performing such color-coding, the main memory device is constituted by a plurality of memory cards having the same performance. Alternatively, one terminal of the memory card is used as an access performance identification signal output terminal, and when a plurality of memory cards are mounted, this terminal of each memory card is connected by wired OR. Then, for example, the output of the relevant terminal of the memory card having a read performance of 60 ns is set to “H”,
The output of the relevant terminal of the memory card having a read performance of 80 ns is set to "L", and the output is set to "L" if even one card of 80 ns is mounted. If a means for identifying the result of the wired OR is provided and the main memory device is operated for 80 ns, the main memory device can be operated without any trouble.

FIG. 8 is a detailed block diagram of the data section 3.
Data lines 3000-0, 3000-1, from the storage unit 1
3000-2 and 3000-3 are connected to the inputs of the multiplexer 30 and write data
It is connected to the outputs of the registers 32-0, 32-1, 32-2, 32-3. The output of the multiplexer 30 is read
The output of the read data register 31 and the inputs of the write data registers 32-0, 32-1, 32-2, 32-3 are connected to the input of the data register 31, and the data line 4000 with the host is connected to the data line 4000. Connected.

In the case of reading, reading from the storage unit 1
The data are data lines 3000-0, 3000-1, 30.
It is taken into the multiplexer 30 via 00-2, 3000-3. The multiplexer 30 switches the read data of four systems for each clock and selects the read data.
Transfer to the data register 31. The read data register 31 transfers the read data to the host computer 4 via the data line 4000.

In the case of writing, the host computer 4 writes the write data to the data section 3 via the data line 4000.
Transfer in batches. The four write data registers 32-0, 32-1, 32-2, 32-3 latch the four write data respectively, and the data lines 3000-
It is supplied to the storage unit 1 via 0, 3000-1, 3000-2, 3000-3.

FIG. 9 is an operation timing chart of the main memory device according to this embodiment. FIG. 9 shows a case where memory read requests are successively issued. At time B, the control unit 2 causes the storage units 1-A0, 1-A1, 1-A2, 1-A3 to
It is activated via the control signal 2000-A. Storage unit 1
-A0,1-A1,1-A2,1-A3 is 1
Start memory access with a delay of each machine cycle.
In FIG. 9, the storage units 1-A0, 1-A1, 1-A2, 1-
A3 is CAS 1001-A0, 1001-A, respectively
1, 1001-A2 and 1001-A3 are activated with a delay of one machine cycle. That is, the storage unit 1-A0 starts CAS 1001-A0 at time G, and the storage unit 1-A1 starts CAS 1001-A1 at time H.
The storage unit 1-A2 starts CAS 1001-at time I.
A2 is started, and the storage unit 1-A3 sets CAS100 at time J.
1-Start A3.

Next, the control unit 2 causes the storage units 1-B0 and 1-B.
Control signals 2000- for 1,1-B2 and 1-B3
Start at time F via B. Storage unit 1-B0,1
-B1, 1-B2, 1-B3 start memory access after each storage unit 1-A3 with a delay of one machine cycle. In FIG. 9, the storage units 1-B0, 1-B1, 1
-B2,1-B3 are respectively CAS1001-B0,
1001-B1, 1001-B2, 1001-B3
The figure shows a state in which the CAS 1001-A3 is activated with a delay of one machine cycle after the activation. That is, the storage unit 1-B0 starts CAS 1001-B0 at time K, the storage unit 1-B1 starts CAS 1001-B1 at time L, and the storage unit 1-B2 starts CAS 1001-B at time M.
2 is started, and the storage unit 1-B3 starts CAS 1001 at time N.
-Start B3.

Further, at the time J, the controller 2 stores the memory 1-A.
0, 1-A1, 1-A2, 1-A3 are activated via the control signal 2000-A. Storage unit 1-A0,
1-A1, 1-A2, and 1-A3 start memory access with a delay of one machine cycle each following the storage unit 1-B3. In FIG. 9, the storage units 1-A0, 1-A1,
1-A2 and 1-A3 are respectively CAS1001-A
0,1001-A1,1001-A2,1001-A3
Shows that the CAS 1001-B3 is activated with a delay of one machine cycle after the activation of the CAS 1001-B3. That is, the storage unit 1-A0 starts CAS 1001-A0 at time O, and the storage unit 1-A1 starts CAS 1001-A1 at time P.
Storage unit 1-A2 starts CAS 1001-at time Q.
A2 is started, and the storage unit 1-A3 sets CAS100 at time R.
1-Start A3.

FIG. 10 shows the data line 30 in the above operation.
The data appearing at 00,4000 are shown. Data line 30
00-0 includes CAS1001-A0 and CAS10.
The data A0 and B0 read from the storage units 1-A0 and 1-B0, respectively, are alternately displayed by the activation of 01-B0. Similarly, the data line 3000-1 is connected to the CAS100.
1-A1 and CAS 1001-B1 are activated, the data A1 and B1 respectively read from the storage units 1-A1 and 1-B1 are transferred to the data line 3000-2 on the CAS10.
01-A2 and CAS 1001-B2 are activated, the data A2 and B2 respectively read from the storage units 1-A2 and 1-B2 are transferred to the data line 3000-3 on the CAS line.
The data A3 and B3 read respectively from the storage units 1-A3 and 1-B3 appear alternately by the activation of 1001-A3 and CAS 1001-B3.

The data section 3 includes data lines 3000-0, 30.
00-1, 3000-2, 3000-3 are cyclically switched and supplied to the data line 4000. That is, the data A0 on the data line 3000-0 is supplied to the data line 4000 at the time J, and similarly, at the time K, the data line 30 is transmitted.
The data A1 on 0-1 is transferred to the data line 3000 at time L
-2 data A2, at time M data line 3000-3
The data A3 above, the data B0 on the data line 3000-0 at time N, the data B1 on the data line 3000-1 at time O, and the data B on the data line 3000-2 at time P.
2 at time Q, data B3 on the data line 3000-3
At time R, the data A0 on the data line 3000-0 is
The data A1 on the data line 3000-1 is supplied to the data line 4000 at the time S, the data A2 on the data line 3000-2 at the time T, and the data A3 on the data line 3000-3 at the time U.

FIG. 11 is another operation timing chart of the main memory device according to this embodiment. FIG. 11 shows a case where memory write requests are successively issued. Also in the case of memory write, the control signal 2000 and the CAS100 shown in FIG.
The timing with 1 is the same. That is, at the time B and the time J, the control unit 2 causes the storage unit 1-A0, 1-A1, 1-A.
2,1-A3 is activated, time F and time N
When the storage units 1-B0, 1-B1, 1-B2, and 1-B3 are activated, the CAS 1001-A0, 100
1-A1, 1001-A2, 1001-A3, 1001
-B0,1001-B1,1001-B2,1001-
B3 is activated at the timing shown in the figure.

On the other hand, the data section 3 writes write data from the host computer 4 every machine cycle A0, A1, A.
2, A3, B0, B1, B2, B3 are sequentially taken in through the data line 4, and the data lines 3000-0, 3000-
1, 3000-2, 3000-3. In the figure, the write timing by the early write is shown, which is 2 before and after the falling edge of CAS1001.
It is controlled so that the write data is retained during the machine cycle.

That is, the data A0 output to the data line 4000 at the time D is supplied to the data line 3000-0 during the time E to the time I, and the data A0 is output to the CAS 1001-A at the time G.
It is written to the storage unit 1-A0 by the falling edge of 0. Similarly, the data A1 output to the data line 4000 at time E is supplied to the data line 3000-1 between time F and time J, and CAS1001-A at time H.
Data A written to the storage unit 1-A1 by the falling edge of 1 and output to the data line 4000 at time F
2 is supplied to the data line 3000-2 between the time G and the time K, written in the memory unit 1-A2 at the falling edge of the CAS 1001-A2 at the time I, and output to the data line 4000 at the time G. The data A3 is supplied to the data line 3000-3 between the time H and the time L, and is written in the storage unit 1-A3 at the time J by the falling edge of the CAS 1001-A3.

Further, the data B0 output to the data line 4000 at the time H is supplied to the data line 3000-0 during the time I to the time M, and the data B0 is output to the CAS 1001-B at the time K.
It is written to the storage unit 1-B0 at the falling edge of 0. Similarly, the data B1 output to the data line 4000 at the time I is supplied to the data line 3000-1 between the time J and the time N, and the data is transmitted to the CAS 1001-B at the time L.
The data B written in the storage unit 1-B1 by the falling edge of 1 and output to the data line 4000 at time J
2 is supplied to the data line 3000-2 between the time K and the time O, written in the storage unit 1-B2 by the falling edge of the CAS 1001-B2 at the time M, and output to the data line 4000 at the time K. The data B3 is supplied to the data line 3000-3 between the time L and the time P, and is written in the storage unit 1-B3 at the time N by the falling edge of the CAS 1001-B3.

According to this embodiment, eight independent storage units 1 are provided.
The number of data lines 3000 of 4 is half of the number of storage units 1, and since the data lines 3000 can be used without interruption to access the memory, a high-throughput main storage device with a small amount of material can be realized. There is an effect that can be realized. Further, in the present embodiment, the read data read onto the data line 3000 is transferred to the data line 4000 without delay in the data section 3, so there is an effect that a main memory device having the shortest latency can be realized.

Further, since the access performance identification signal of one memory card 111 is distributed to all the other circuits, all the circuits of the main memory can recognize the access performance by a single system signal, and access with a small amount of material is possible. There is an effect that the performance can be recognized. In addition, memory card 1
By coloring the whole or a part of the base 11 of 11, there is an effect that it becomes easy to prevent the memory card 111 from being erroneously attached by visual inspection.

[0035]

According to the present invention, the number of data lines is reduced, and a main memory device having a performance equivalent to that of the parallel access system can be realized with a small amount of material. Also, the memory
Random access memory 1 according to the access performance identification signal of the card 111 and the color of the base of the memory card 111
Since the access performances of 10 can be identified, it is possible to use electrical identification and visual identification together. Therefore, there is an effect that the memory access performance can be surely identified with a small amount of material and the erroneous mounting of the memory card 111 can be easily prevented.

[Brief description of drawings]

FIG. 1 is an overall configuration diagram of a computer system and a main storage device according to an embodiment of the present invention.

FIG. 2 is a configuration diagram of a storage unit shown in FIG.

FIG. 3 is an external view of a memory card.

FIG. 4 is a configuration diagram of a storage element unit.

FIG. 5 is an access performance identification signal wiring diagram.

FIG. 6 is an explanatory diagram of a visual identification method of a memory card base.

FIG. 7 is an explanatory diagram of a visual identification method of a memory card base.

8 is a configuration diagram of a data section shown in FIG. 1. FIG.

9 is an operation timing chart of the main storage device shown in FIG.

10 is an operation timing chart of the main storage device shown in FIG.

FIG. 11 is another operation timing chart of the main memory device shown in FIG.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... Storage unit, 2 ... Control unit, 3 ... Data unit, 4 ... Host computer, 10 ... Timing generation circuit, 11 ... Storage element unit,
30 ... Multiplexer, 31 ... Read data register, 32 ... Write data register, 110 ... Random access memory, 111 ... Memory card.

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Kenichi Kurosawa 7-1, 1-1 Omika-cho, Hitachi-shi, Ibaraki Hitachi Ltd. Hitachi Research Laboratory (72) Inventor Sataka Ishikawa 1-chome, Horiyamashita, Hadano, Kanagawa Company General Manager Computer Division (72) Inventor Hidetada Fukunaka 1 Horiyamashita, Hadano City, Kanagawa Prefecture General Computer Division General Manager, Hitachi, Ltd. (72) Eiichiro Nagai 1 Horiyamashita, Hadano City, Kanagawa Hitachi Computer Engineering Co., Ltd.

Claims (12)

[Claims] 1. A main storage device in a computer system, comprising m × n (m: a plurality, n: a positive integer) storage units.
A control unit for generating control signals of m systems for controlling the storage units n units, and m controlled by the control signals of m systems.
A main storage device comprising n data lines, each of which has one storage unit as a set, and which connects the storage units in common, and a data unit which takes in the n data lines. 2. The method according to claim 1, wherein m = 2, and the control signals A and B of the two systems can be activated with each other with a time half of the access time of the storage unit. Storage device. 3. The control signals A and B according to claim 2.
Are capable of starting each other at intervals of a time obtained by adding a constant to the CAS width of the storage unit. 4. The data unit according to claim 2, wherein the data section includes a multiplexer that makes the n data lines one.
A main storage device characterized in that data of each data line is divided into n times and transferred to a host computer. 5. In claim 4, where t is the time for the data section to transfer data to the host computer once, i
From 0 to (n-1), the i-th storage unit is activated with a delay of txi after activation by the control signal. 6. At least one memory card equipped with a plurality of random access memories, and the memory card.
In a main storage device of a computer system including at least one storage unit to which at least one card is connected, a control unit that controls the storage unit, and a data unit that manages input / output of data to / from the storage unit. Memory card is memory
The memory access performance identification terminal is provided, and the memory access performance identification terminal of each memory card mounted on the main storage device is wired or connected to identify the common performance of each memory card and each memory is identified by the common performance. A main storage device having means for operating a card. 7. A memory used for the main storage device according to claim 6.
A memory card, wherein one of the terminals is an access performance identification terminal of the memory card. 8. At least one memory card equipped with a plurality of random access memories, and the memory card.
It is used for a main storage device of a computer system including at least one storage unit to which at least one card is connected, a control unit for controlling the storage unit, and a data unit for managing input / output of data with the storage unit. In the memory card, the memory card includes means for outputting a memory access performance identification signal to the control unit and the data unit. 9. At least one memory card equipped with a plurality of random access memories, and the memory card.
A memory used for a main storage device of a computer system including at least one storage unit to which at least one card is connected, a control unit that controls the storage unit, and a data unit that manages input and output of data to and from the storage unit The memory card is characterized in that the color of the base of the memory card is a color defined according to the access performance. 10. The m storage units whose outputs are connected to a common data line, and the host which stores the data cyclically accessed from each storage unit and cyclically read from each storage unit to the common data line. And a means for transferring to a computer. 11. The number of m storage units according to claim 10 is n.
A main memory device comprising groups, and means for collecting data output to n common data lines for each group into one data by a multiplexer and transferring the data to a host computer. 12. A computer system comprising the main storage device according to claim 1, 10, or 11.