JPS61273182A - External power source synchronous inverter - Google Patents

Abstract

PURPOSE:To suppress the frequency change rate by limiting a signal in response to the phase difference between an external power source voltage and an inverter output voltage to the prescribed time width within each zone divided in a plurality to input to a phase synchronizer system. CONSTITUTION:An inverter 1 of an external power source synchronous inverter supplies power through an AC switch 2 to a load 3, and a backup external power source 4 supplies power through an AC switch 5 to the load 3. The controller of the inverter 1 is composed of a gate controller 8 through a frequency divider 7 from a voltage control oscillator 6. In this case, to synchronize the voltage of the power source 4 with the output voltage of the inverter 1, a synchronization instructing circuit 9 and a phase comparator 10 are provided. Thus, the phase difference of the both is detected in response to a deviation of the both output voltages, and input only in the prescribed time width at the center of the zone of each half cycle. The prescribed time width is gradually expanded by the manner used for longitudinally increasing from the center.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Application of the Invention] The present invention relates to an external power supply synchronized inverter device, and particularly to an external signal synchronized inverter device with little frequency transient fluctuation.

[Background of the invention]

There are cases where an inverter device is operated in synchronization with an external power source such as a commercial power source to supply power to a load, and when the inverter fails or is maintained, the external power source is switched to supply power to the load. In such an inverter device, as disclosed in Japanese Patent Publication No. 58-21506, for example, in order to obtain an inverter output synchronized with an external power source, the phase difference between the external power source voltage and the inverter output voltage is detected by a phase comparator circuit. To detect. The frequency of a voltage controlled oscillator (VCO) is controlled by a voltage corresponding to the difference, and the frequency is further divided by the number of inverter phases using a frequency divider. This is the so-called phase-locked loop (PL
L) and is the most popular circuit. Incidentally, recently, as electronic equipment becomes more precise, there is a demand on the load side that the rate of change in the frequency of an inverter must be limited to a certain value or less. - For example, in an electronic computer used at commercial frequencies, the frequency change rate is 1 (
Hz/sec] or less.

In conventional circuits, the frequency of the inverter is manufactured to have a variation range of approximately ±2%.

Further, the response speed is about 0.1 seconds. Here, consider the case where external power is applied for the first time while the inverter is operating. If the phases of the external power source and the inverter are different, the inverter is synchronized with the external power source by the operation of the PLL described above. At this time, the frequency change rate is approximately as shown in the following equation, and the change rate is too excessive.

0.1 second In order to suppress this to below 1 (Hz/second), the frequency fluctuation range must be narrowed or the response time must be lengthened.However, in the former case, the frequency of the external power supply is usually around 1%. In the latter case, the response can be slowed down with a time delay element such as a capacitor, but when the phase is completely defeated, a hunting phenomenon occurs before it converges to the target value. , control becomes unstable.

Conventional control circuits have a problem in that they cannot suppress the rate of frequency change and stably control the phase.

[Purpose of the invention]

An object of the present invention is to provide an external power supply synchronized inverter device that suppresses the frequency change rate and has excellent settling accuracy and stability during steady state.

[Summary of the invention]

A feature of the present invention is that a signal corresponding to the phase difference between the external power supply voltage and the inverter output voltage is limited to a predetermined time width within each section divided into a plurality of sections, and is input to the phase synchronization system. It is to be.

In one preferred embodiment of the present invention described below,
The phase difference between the external power source and the inverter is detected according to the deviation between the two output voltages, and is input to the phase synchronization control system only during a predetermined time width in the center of each half cycle section.

Further, this predetermined time width is gradually widened from the central portion to the front and back, and is eventually input to the phase synchronization control system over the entire period.

With this configuration, it is possible to obtain an external power supply synchronized inverter device that suppresses the frequency change rate to a low level and does not impair frequency accuracy and stability during steady state.

[Embodiments of the invention]

Hereinafter, the present invention will be explained in detail with reference to illustrated embodiments.

FIG. 1 is an overall block diagram of an external power supply synchronized inverter device according to an embodiment of the present invention. Inverter 1 is
Power is supplied to the load 3 via the AC switch 2, and an external power source 4 for backup can supply power to the load 3 via the AC switch 5. Further, the control device for the inverter 1 is constituted by a gate control circuit 8 that runs from a voltage controlled oscillator 6 through a frequency divider 7 that performs frequency division proportional to the number of polyphase or single-phase phases.

Now, in order to synchronize the voltage of the external power supply 4 and the output voltage of the inverter 1, a synchronization command circuit 9 and a phase comparison circuit 10 are provided. The phase comparison circuit 10 is connected to the synchronization command circuit 9
When the output signal VIS of becomes “1”, the power supply voltage V,
A synchronous control system is constructed in which the phase difference between the inverter output voltage V+t and the inverter output voltage V+t is detected, and a signal vl corresponding to this phase difference is input to the voltage controlled oscillator 6 to increase or decrease the frequency to reduce the phase difference.

Note that the signal V14 is a signal that distinguishes between positive and negative half cycles for synchronous detection.

FIG. 2 shows a specific configuration of the phase comparator circuit 10 in FIG. 1, including an operational amplifier 114 and a resistor ill.

112.113 inverts the inverter output voltage waveform, operational amplifier 119, resistor 115, 116.117°118
takes the difference between the external power supply voltage waveform and the inverter output voltage waveform to obtain the differential voltage V+S. The multiplexer 124 is for synchronously detecting the differential voltage vI. resistance 120
, 121, 122, 123 are input resistances of the operational amplifier 127, including a resistor 125°128 and a capacitor 126.
．． 129 are an output resistor and an output capacitor, respectively;
The ripple component is removed from the synchronous detection waveform to obtain a DC voltage V.

In order to obtain , the −th lag element is used. 130 is a logic inversion circuit, 131 and 132 are AND circuits, and logical signals V, , V are given to the control terminals A and H of the multiplexer 124 by ANDing the synchronous detection signal V14 and the synchronous command circuit output vlS. , , occurs.

Here, the output terminals X and Y of the multiplexer are connected according to the signals of the control terminals A and H as shown in the table below. , input terminal Y, are connected to the output terminal Y, the inputs of the operational amplifier are both at zero voltage, and the output voltage v1. also becomes zero voltage.

If the A terminal is "1" and the B terminal is 0, the input terminal X1 is connected to the output terminal X, the input terminal Y1 is connected to the output terminal Y, and the operational amplifier 127 operates as an inverting amplifier, so the voltage v1 An output voltage v1. with the polarity reversed is obtained.

If the A terminal is "0" and the B terminal is "1", input terminal X is connected to output terminal X, input terminal Y is connected to output terminal Y, and the operational amplifier 127 operates as a non-inverting amplifier. - Obtain a Q voltage v1. of the same polarity as the voltage v13.

If both A and B terminals are “1”, input terminal X1
is connected to the output terminal X, the input terminal Y1 is connected to the output terminal Y, and the inputs of the operational amplifier are both at zero voltage.
7 output voltage v1. also becomes zero voltage.

In this embodiment, the phase comparison circuit 10 transmits the phase difference equivalent signal to the voltage controlled oscillator 6 only during the period when the command signal vIS given from the synchronization command circuit 9 is "1".

Therefore, in order to make it easier to understand, first, the operation when the command signal V+S is assumed to be "1" over the entire range is described in the third section.
For the power supply voltage waveform Vll, which will be explained with a diagram,
Let us take as an example a case where the inverter output voltage waveform V1g is delayed by 90°. The difference voltage V (2 is a waveform advanced by 45 degrees with respect to the external power supply voltage vII. Here, from 1-1. to txi
.

Up to this point, the synchronous detection signal V14 is 10゜, and the synchronous command circuit output vIS is "1", so the output signal V14 of the AND circuit 131 is "O" and the output signal V+1 of the AND circuit 132 is "1". ” multiplexer 124
0' is applied to the control terminal A, and 1' is applied to the control terminal B. Therefore, as described above, operational amplifier 127 operates as a non-inverting amplifier.

If the output voltage of the operational amplifier 127 in a circuit without the capacitors 126 and 129 is vl', it will be in phase with the differential voltage V+S, as shown by the broken line in the figure. capacitor 1
26.129, the ripple component of the output voltage is removed and a DC voltage component is obtained, so the output voltage v1. is obtained as a positive polarity voltage.

Next, °, 1-1. From 1-1□ is the synchronous detection signal V1
4 is "l", and the synchronization command circuit output V+S is 1
', so the output signal v0 of the AND circuit 131 is "l".
, the output signal vI? of the AND circuit 132 becomes 60'. "1" is applied to the control terminal A of the multiplexer 124, and O' is applied to the control terminal B. Therefore, the operational amplifier 127 operates as an inverting amplifier. If the capacitor 126,
The output voltage v,,,' of the operational amplifier 127 in the circuit without 129 has its polarity inverted with respect to the differential voltage vI3, as shown by the broken line in the figure. Since the capacitors 126 and 129 remove the ripple component of the output voltage and obtain a DC voltage component, the output voltage V+S of the operational amplifier 127 is obtained as a positive polarity voltage. By performing synchronous detection with the multiplexer 124, a DC voltage proportional to the phase difference is extracted,
By increasing the frequency of the voltage controlled oscillator 6, the aforementioned 90° delay with respect to the power supply voltage can be recovered and synchronized with the external power supply.

Now, with reference to FIG. 4, the ability to suppress the frequency change rate, which is the main part of the present invention, will be explained. Similarly to the above, for the external power supply voltage waveform V, the inverter output voltage waveform ■
18 is delayed by 90 degrees. The differential voltage vIff has a waveform that is advanced by 45 degrees with respect to the external power supply voltage Vll. Here, 1-1. The synchronization control function shall be operated from the beginning to synchronize with the external power supply. First, 1-1. From tss
During l+, the synchronization command circuit output VtS is output at equal intervals before and after the center point of the "0" section of the synchronized detection signal VI4, and becomes "1" for 1 = 1 interval from txt, .
Therefore, the output signal Vl of the AND circuit 132? gat"
The operational amplifier 127 becomes "1" from tt+ to t ''' t, , and the operational amplifier 127 operates as a non-inverting amplifier.
The output voltage V+S' of 27 is as shown by the broken line in the figure.

Output voltage ■1. is smoothed, so 1=1. It gradually increases from 1 = 1, , and after t”t,!, approximately -t, to 1mj,
! It gradually becomes lower at the same time as , and reaches zero voltage at txt, . ixj, the output voltage of the operational amplifier 127, that is, the output voltage of the phase comparator 10 is t-tlI
A slightly positive voltage is generated between i-t 13 and the frequency of the voltage controlled oscillator 6 is also slightly higher.
From t-t3, the synchronization command circuit output V+S is:
They are output at equal intervals before and after the center point of the "1" section of the synchronous detection signal V14, and 1-1. , to l-1,S “1
”, therefore, the output signal vi of AND circuit !31
If a becomes 1 degree from 1=1.4 to t '' t , and the operational amplifier 127 operates as an inverting amplifier,
Output voltage of operational amplifier 127 in a circuit without capacitors 126 and 129■3. ' is as shown by the broken line in the figure. Since the output voltage vl is smoothed by the capacitors 127 and 129, it gradually increases from 1-tl4 to t-tIS, L"t, and thereafter approximately 1xl, from 4 to tt
The voltage gradually decreases over the same time period as , , and reaches zero voltage at t-tl. 1-1. From 1-1. The output voltage of the operational amplifier 127, that is, the output voltage of the phase comparator 10 between t m t
, , a slightly positive voltage is generated between entangle=tlA, and the frequency of the voltage controlled oscillator 6 also becomes slightly higher. Below 1=
1° to 1-1. Between t and !, the output V+S of the synchronization command circuit 9 is t, ! It is assumed that between l, , and 1-1, Il is @1'. 1-1° to 1-1. In between, the output Vis of the synchronization command circuit 9 is "1" from tmlt to 1-1□.
The output VI8 of the synchronization command circuit 9 gradually lengthens the 1° interval, and finally becomes "1" in the entire interval (signal v1. is in the state shown in Fig. 3), reaching a steady state.Synchronization command circuit 9
If the duty of the output VI5 is d, then the operational amplifier 1
The time during which the output voltage Vl11 of No. 27 is outputted is 2d. Therefore, according to this embodiment, the frequency change rate is approximately 2d times that of the conventional example.Here, if the duty is gradually increased, for example, in steps of 0.05, the frequency change rate will be approximately 2d times that of the conventional example. , becomes 0.1 times and becomes 1 (Hz/S). Also, by changing the duty appropriately,
There is no need to change the responsiveness of the zero-phase comparison circuit 10 whose frequency change rate can be arbitrarily adjusted and the frequency change range of the voltage controlled oscillator 6, and there is no hunting phenomenon or narrowing of the synchronizable frequency range. Sometimes the third
As shown in the figure, since the output V+S of the synchronization command circuit 9 is 11° over the entire range, it is clear that sufficient settling accuracy can be obtained.

Although the details of the synchronization command circuit 9 have been omitted, it is clear that it can be easily constructed using recent pulse width control technology. In this case, the synchronization command signal V+S is changed once every half cycle.
It is also easy to make modifications such as one pulse per cycle instead of two pulses.

Although one embodiment of the present invention has been described above, the present invention is not limited to the above-mentioned embodiment, but can be further modified. Needless to say, other types of phase comparison means for detecting phase differences can also be applied.

〔Effect of the invention〕

According to the present invention, it is possible to provide an external power supply synchronized inverter device that can suppress the frequency change rate without impairing frequency accuracy and stability during steady state.

[Brief explanation of drawings]

FIG. 1 is a block diagram of the overall configuration of an external power supply synchronized inverter device according to an embodiment of the present invention, FIG. 2 is a detailed circuit diagram of the phase comparator circuit lO of FIG. 1, and FIGS. 3 and 4 are FIG. 4 is an explanatory diagram of the operation of the above embodiment. 1... Inverter, 3... Load, 4... External power supply, 9... Synchronization command circuit, 10... Phase difference detection (phase comparison) circuit. Figure 1 Figure 3

Claims (1)

[Claims] 1. An external power source, an inverter that supplies power to a load in a switchable manner between the power source, a control means for the inverter, and a phase difference between the voltage of the power source and the output voltage of the inverter. and phase synchronization means for inputting a signal corresponding to the phase difference to the inverter control means to synchronize the inverter output voltage with the power supply voltage, wherein the signal according to the phase difference is input to the inverter control means. 1. An external power supply synchronized inverter device, comprising: means for limiting a period of time to a predetermined time width within each section divided into a plurality of sections. 2. The external power supply synchronized inverter device according to claim 1, wherein the limiting means includes means for gradually expanding the predetermined time width. 3. The external power supply synchronized inverter device according to item 1, wherein the limiting means includes means for canceling the limitation after a plurality of sections have elapsed. 4. The external power supply synchronized inverter device according to claim 1, wherein the limiting means includes means for adjusting the predetermined time width. 5. The external power supply synchronized inverter device according to item 1, wherein the plurality of intervals are half cycles of the power supply voltage. 6. Clause 5, wherein the phase difference detection means includes means for comparing the power supply voltage and the inverter output voltage, and the limiting means is means for limiting to a predetermined time width in the center of each half cycle section. External power supply synchronous type inverter device as described.