JPS61272840A - Test comprehensiveness measuring instrument for microcomputer program - Google Patents

Test comprehensiveness measuring instrument for microcomputer program

Info

Publication number
JPS61272840A
JPS61272840A JP60115716A JP11571685A JPS61272840A JP S61272840 A JPS61272840 A JP S61272840A JP 60115716 A JP60115716 A JP 60115716A JP 11571685 A JP11571685 A JP 11571685A JP S61272840 A JPS61272840 A JP S61272840A
Authority
JP
Japan
Prior art keywords
address
section
instruction
program
coverage
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP60115716A
Other languages
Japanese (ja)
Inventor
Tatsuro Yasue
安江 辰朗
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP60115716A priority Critical patent/JPS61272840A/en
Publication of JPS61272840A publication Critical patent/JPS61272840A/en
Pending legal-status Critical Current

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Abstract

PURPOSE:To measure heat comprehensiveness even when there is no room to store a measurement program in a computer system by enabling to measure the test comprehensiveness by hardware without using a measurement program. CONSTITUTION:Before starting a test, the range of address of instruction section of a program to be tested is set before hand to an address range setting section 5. When the testing of the program to be tested is started, a central processing unit 1 repeats cycle that fetches instruction of the program to be tested stored in a main memory 2 one by one and executes. An address reading section 6 detects timing of instruction fetching by the fact that a signal of a memory reading controlling line section 4 becomes on, and reads an address of the instruction that flows in an address bus 3 at that point of time. If the address is within the range indicated by the address range setting section 5, the number of times of reading is recorded in the address of a storage section 7 similar to the address of read instruction.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は、マイクロコンビエータ用のコンビエータプロ
グラムをテストする際に利用される装置関し、特にコン
ビエータプログラムのテスト網羅度を測定する装置に関
する。
DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a device used when testing a combinator program for a micro combinator, and more particularly to a device for measuring the test coverage of a combinator program. .

〔従来の技術〕[Conventional technology]

新たに製造されたコンピュータプログラムは実際の業務
で使用される前にテストされる。テストはそのコンビエ
ータプログラムが設計通りの機能と性能を満たしている
ことを確認するため複数回実施されあるいはまた長期間
連続的に実施されるが一般的であり、これら一連のテス
トの完了度合を示す一つの目安としてテスト網羅度が用
いられている。ここでテスト網羅度とはコンビニ−タブ
ログラムの各部分がテストによってどの程度実行された
か、あるいはまたどの種度参照されたかを示す値である
Newly produced computer programs are tested before being used in actual business. Tests are generally conducted multiple times or continuously over a long period of time to confirm that the Combiator program meets the designed functionality and performance. Test coverage is used as one indicator. Here, the test coverage is a value indicating to what extent each part of the convenience store program has been executed by tests, or to what degree it has been referenced.

従来テスト網羅度を測定するためにはテストしたいプロ
グラムすなわち被テストプログラムを、テスト網羅度測
定プログラムのもとで実行させる必要があった。
Conventionally, in order to measure test coverage, it was necessary to run the program to be tested, that is, the program under test, under a test coverage measurement program.

〔発明が解決しようとする問題点〕[Problem that the invention seeks to solve]

上述した従来のテスト網羅度測定プログラムによってテ
スト網羅度を測定する方法は、測定プログラムが被テス
トプログラムの動きを中断しつ\その動作状況を記録し
ていく方法であるため、中断が許されないリアルタイム
システム用のプログラムの測定には不向きであり、また
被テストプログラムと測定プログラムを同時に実行させ
得るメモリ領域が必要となるため、被テストプログラム
を実行させるのに必要なメモリだけが搭載されるマイク
ロコンビエータシステムなどでの測定は不可能であった
The method of measuring test coverage using the conventional test coverage measurement program described above is a method in which the measurement program interrupts the operation of the program under test and records its operating status. It is not suitable for measuring system programs, and requires a memory area that can run the program under test and the measurement program at the same time. Measurement using the Eta system was not possible.

〔問題点を解決するための手段〕[Means for solving problems]

本発明はマイクロコンビエータシステムでのテスト網羅
度を測定プログラムに依るのでなくハードウェアで測定
するものである。
The present invention measures test coverage in a micro combinator system using hardware rather than relying on a measurement program.

上記目的を達成するために本発明は次の構成を有する。In order to achieve the above object, the present invention has the following configuration.

即ち中央処理装置と被テストプログラムを格納している
主メモリとからなるマイクロコンピュータシステムにお
いて、被テストプログラムの命令部のアドレス範囲を設
定するアドレス範囲設定部と、中央処理装置が被テスト
プログラムの一命令を読み出すたびにその命令のアドレ
スをアドレスから読み取るアドレス読出し部と、主メモ
リと同等あるいはそれ以上のアドレス空間を持ちアドレ
ス読出し部が読み取った命令のアドレスと同一アドレス
に命令の読出し回数を記録する記憶部と、記憶部の記録
内容から網羅度を計算する網羅度計算部と、計算された
網羅度を表示する網羅度表示部とを備えるマイクロコン
ピュータプログラムのテスト網羅度測定装置である。
That is, in a microcomputer system consisting of a central processing unit and a main memory storing a program under test, an address range setting unit sets the address range of the instruction section of the program under test, and the central processing unit sets the address range of the instruction section of the program under test. An address reading unit that reads the address of the instruction each time an instruction is read from the address, and a memory that has an address space equal to or larger than the main memory and records the number of times the instruction has been read at the same address as the address of the instruction read by the address reading unit. The present invention is a test coverage measuring device for a microcomputer program, which includes a coverage calculation section that calculates coverage from the recorded contents of a storage section, and a coverage display section that displays the calculated coverage.

〔実施例〕〔Example〕

以下、本発明にかかるマイクロコンビニ−タブグラムの
テスト網羅度測定装置の動作を図面に基づいて説明する
DESCRIPTION OF THE PREFERRED EMBODIMENTS The operation of the microconvenience tabgram test coverage measuring device according to the present invention will be described below with reference to the drawings.

第1図は本発明の構成を示すブロック図である。FIG. 1 is a block diagram showing the configuration of the present invention.

テスト開始の前に被テストプログラムの命令部のアドレ
ス範囲をアドレス範囲設定部5に設定して2く。被テス
トプログラムのテストを開始すると、中央処理装置1は
主メモリ2に格納されている被テストプログラムの命令
を一つづつフェッチしては実行するというサイクルを繰
り返す。アドレス読出し部6は命令フェッチのタイミン
グをメモリ読出し制御線4の信号がONになることによ
り検出し、その時点でアドレスバス3を流れる命令のア
ドレスを読み取り、読み取った命令のアドレスがアドレ
ス範囲設定部が示すアドレス範囲内であれば、読み取っ
た命令のアドレスと同一の記憶部7のアドレスに読み出
し回数を記録する。アドレス読出し部6が上記動作をテ
スト実施中に繰り返すことにより、被テストプログラム
の各命令の読出し回数が記憶部7に記録されることにな
る。
Before starting the test, the address range of the instruction section of the program under test is set in the address range setting section 5. When testing the program under test, the central processing unit 1 repeats a cycle of fetching and executing instructions of the program under test stored in the main memory 2 one by one. The address reading section 6 detects the instruction fetch timing when the signal on the memory read control line 4 turns ON, reads the address of the instruction flowing through the address bus 3 at that point, and the address of the read instruction is set in the address range setting section. If it is within the address range indicated by , the number of reads is recorded at the same address in the storage unit 7 as the address of the read instruction. As the address reading unit 6 repeats the above operations during the test, the number of times each instruction of the program under test is read is recorded in the storage unit 7.

テスト終了後網羅度計算部8はアドレス範囲設定部5が
示すアドレス範囲内の命令読出し回数を記憶部7から得
て網羅度を計算し、計算結果を網羅度表示部9が表示す
る。
After the test is completed, the coverage calculation section 8 obtains the number of instructions read within the address range indicated by the address range setting section 5 from the storage section 7, calculates the coverage, and the coverage display section 9 displays the calculation result.

〔発明の効果〕〔Effect of the invention〕

以上説明したように本発明は、テスト網羅度を測定プロ
グラムではなくハードウェアで測定出来るため、測定プ
ログラムを格納する余裕のないマイクロコンピュータシ
ステムなどでもテスト網羅度を測定することが可能とな
る。
As explained above, the present invention allows test coverage to be measured using hardware rather than a measurement program, so that test coverage can be measured even in a microcomputer system that does not have room to store a measurement program.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本発明の構成を示すブロック図である。 1・・・・・・中央処理装置、2・・・・・・主メモリ
、3・・・・・・アドレスバス、4・・・・・・メモリ
読出し制御線、5パ。 ・・・アドレス範囲設定部、6・・・・・・アドレス読
出し部、7・・・・・・記憶部、8・・・・・・網羅度
計算部、9・・・・・・網羅度表示部。
FIG. 1 is a block diagram showing the configuration of the present invention. 1...Central processing unit, 2...Main memory, 3...Address bus, 4...Memory read control line, 5 pins. ... Address range setting section, 6 ... Address reading section, 7 ... Storage section, 8 ... Coverage calculation section, 9 ... Coverage degree Display section.

Claims (1)

【特許請求の範囲】[Claims] 中央処理装置と主メモリとからなるマイクロコンピュー
タシステムにおいて、主メモリに格納される被テストプ
ログラムの命令部のアドレス範囲を設定するアドレス範
囲設定部と、中央処理装置が被テストプログラムの一命
令を読出すたびにその命令のアドレスをアドレスバスか
ら読み取るアドレス読出し部と、主メモリと同等あるい
はそれ以上のアドレス空間を持ちアドレス読出し部が読
み取った命令のアドレスと同一アドレスに命令の読出し
回数を記録する記憶部と、記憶部の記録内容から網羅度
を計算する網羅度計算部と、計算された網羅度を表示す
る網羅度表示部とを備えるマイクロコンピュータプログ
ラムのテスト網羅度測定装置。
In a microcomputer system consisting of a central processing unit and a main memory, there is an address range setting section that sets the address range of the instruction section of the program under test stored in the main memory, and a section that sets the address range of the instruction section of the program under test stored in the main memory, and a An address reading section that reads the address of the instruction from the address bus each time it is issued, and a storage section that has an address space equivalent to or larger than the main memory and records the number of times the instruction has been read at the same address as the address of the instruction read by the address reading section. A coverage measurement device for testing a microcomputer program, comprising: a coverage calculation unit that calculates coverage from recorded contents of a storage unit; and a coverage display unit that displays the calculated coverage.
JP60115716A 1985-05-29 1985-05-29 Test comprehensiveness measuring instrument for microcomputer program Pending JPS61272840A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP60115716A JPS61272840A (en) 1985-05-29 1985-05-29 Test comprehensiveness measuring instrument for microcomputer program

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP60115716A JPS61272840A (en) 1985-05-29 1985-05-29 Test comprehensiveness measuring instrument for microcomputer program

Publications (1)

Publication Number Publication Date
JPS61272840A true JPS61272840A (en) 1986-12-03

Family

ID=14669398

Family Applications (1)

Application Number Title Priority Date Filing Date
JP60115716A Pending JPS61272840A (en) 1985-05-29 1985-05-29 Test comprehensiveness measuring instrument for microcomputer program

Country Status (1)

Country Link
JP (1) JPS61272840A (en)

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