JPS6127183Y2 - - Google Patents

Info

Publication number
JPS6127183Y2
JPS6127183Y2 JP11207781U JP11207781U JPS6127183Y2 JP S6127183 Y2 JPS6127183 Y2 JP S6127183Y2 JP 11207781 U JP11207781 U JP 11207781U JP 11207781 U JP11207781 U JP 11207781U JP S6127183 Y2 JPS6127183 Y2 JP S6127183Y2
Authority
JP
Japan
Prior art keywords
package
packages
connector part
leads
convex
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP11207781U
Other languages
Japanese (ja)
Other versions
JPS5818346U (en
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP11207781U priority Critical patent/JPS5818346U/en
Publication of JPS5818346U publication Critical patent/JPS5818346U/en
Application granted granted Critical
Publication of JPS6127183Y2 publication Critical patent/JPS6127183Y2/ja
Granted legal-status Critical Current

Links

Description

【考案の詳細な説明】 本考案はICパツケージの形状に関するもので
ある。
[Detailed Description of the Invention] The present invention relates to the shape of an IC package.

最近、ROM,RAM,CPU等から成るいわゆる
マイコン構成を内蔵した電子機器においては、装
置のより小型化、薄型化が要請されてきており、
これに伴つて、使用する各部品の小型化や部品の
最適配置等を評価して、実装面積の有効利用を図
る努力が続けられている。その中で、比較的大き
な面積を占有するROMやRAM等のICパツケージ
は、ピン配置が両側の所謂デユアルインライン型
から、ピン配置が4方向にある所謂クワツド型の
ものに置き換えられてきており、今日では、小型
の電子機器には専らクワツド型のICパツケージ
が用いられている。
Recently, there has been a demand for smaller and thinner electronic devices with built-in so-called microcomputer configurations consisting of ROM, RAM, CPU, etc.
Along with this, efforts are being made to make effective use of the mounting area by evaluating the miniaturization of each component used and the optimal placement of components. Among these, IC packages such as ROM and RAM, which occupy a relatively large area, are being replaced from the so-called dual in-line type with pin placement on both sides to the so-called quad type with pin placement in four directions. Today, quad IC packages are used exclusively for small electronic devices.

しかしながら、この様なクワツド型ICパツケ
ージを用いても、一定の面積を有効に利用するに
は限界があり、そのため、例えば多数のROMを
使用する場合には多層プリント配線基板を使用し
なければならない等の不都合があつた。
However, even if such a quad-type IC package is used, there is a limit to how effectively a certain area can be used, and therefore, for example, when using a large number of ROMs, a multilayer printed wiring board must be used. There were other inconveniences.

本考案は、上記の様な不都合を解消し、ICパ
ツケージの形状を改良することにより、実質的に
実装面積の低減を図れる様にするものである。
The present invention eliminates the above-mentioned disadvantages and improves the shape of the IC package, thereby making it possible to substantially reduce the mounting area.

以下、図面を参照して本考案の実施例につき説
明する。
Embodiments of the present invention will be described below with reference to the drawings.

第1図は本考案の実施例であるICパツケージ
をプリント基板に実装する手順を説明する図、第
2図は同ICパツケージを6個実装後の外観斜視
図、第3図は使用例を示す図である。
Figure 1 is a diagram explaining the procedure for mounting an IC package, which is an embodiment of the present invention, on a printed circuit board, Figure 2 is a perspective view of the external appearance after six IC packages are mounted, and Figure 3 is an example of usage. It is a diagram.

図において、PはICパツケージ本体であると
ともに、リードLが4方向の側面に設けられた所
謂クワツド型パツケージである。
In the figure, P is the IC package main body, and it is a so-called quad-type package in which leads L are provided on the sides in four directions.

それぞれのICパツケージの天面の中央部は凸
部Tが設けられ、また、底面の上記凸部Tに対応
する位置には凹部Oがそれぞれ設けられていて、
この凹部Oに上記凸部Tが嵌入しうるように形成
されている。
A convex portion T is provided at the center of the top surface of each IC package cage, and a concave portion O is provided at a position corresponding to the convex portion T on the bottom surface, respectively.
The convex portion T is formed so as to fit into the concave portion O.

XはパツケージPの中に封入されたシリコンチ
ツプであり、このチツプはワイヤーBでリードL
とボンデイングされている。一方、リードLは図
示の如くパツケージの壁面に沿つて貼着されてお
り、その一方は上記シリコンチツプXにボンデイ
ングされ、特に他方は前記凹部Oの内壁にあつて
円弧状に内側へ膨出形成されている。これはパツ
ケージPの凹部Oに他のパツケージPの凸部Tを
嵌入させたとき、それを弾性的に保持させるため
である。したがつて、この場合、リードLは弾性
材で形成するのが望ましい。
X is a silicon chip sealed in package P, and this chip is connected to lead L by wire B.
It is bonded with. On the other hand, the leads L are attached along the wall surface of the package as shown in the figure, one of which is bonded to the silicon chip has been done. This is so that when the convex part T of another package P is fitted into the concave part O of the package P, it is held elastically. Therefore, in this case, it is desirable that the leads L be made of an elastic material.

上記のように構成されたICパツケージPをプ
リント基板PWB上のパターンCに半田Sで固定
し、その上から5個のICパツケージPをそれぞ
れの凸部、凹部を合わせて重ねると、第2図に示
す様にプリント基板PWB上に都合6個のICパツ
ケージP1〜P6が実装されることになる。この場
合、各ICパツケージPを重ね合わせると同時に
各共通リードLが互いに接触し、電気的に接触さ
れており、したがつて重ね合せた後各パツケージ
の共通リードLをバンダ等で固定する必要はな
い。
The IC package P configured as described above is fixed to the pattern C on the printed circuit board PWB with solder S, and when five IC package P are stacked on top of it with their convex and concave parts aligned, the result is shown in Figure 2. As shown in the figure, a total of six IC packages P1 to P6 are mounted on the printed circuit board PWB. In this case, the common leads L of each IC package P are in contact with each other at the same time as they are stacked, and are in electrical contact with each other. Therefore, it is not necessary to fix the common leads L of each package with a bander or the like after stacking the IC packages P. do not have.

重ね合わせたICパツケージP、例えばROMパ
ツケージROM0〜ROMnは一般に第3図に示す様
に入出力コントローラI/O、データの一時記憶
用のRAM等を備える中央演算処理器CPUに接続
し、チツプセレクターによつて任意にアクセスす
ることができるものである。
The stacked IC packages P, for example ROM packages ROM 0 to ROMn, are generally connected to a central processing unit CPU equipped with an input/output controller I/O, RAM for temporary storage of data, etc., as shown in FIG. It can be accessed arbitrarily using the selector.

以上の様に、本考案によれば、ICパツケージ
の形状の改良により、同一位置に任意の個数の
ICパツケージを積み重ねて実装することが出
来、実装面積を大きく減少させることができる。
又、単に積み重ねるだけで電気的且つ機械的に接
続出来、したがつてICパツケージの積層数を容
易に変更することができる。更に、構造が非常に
簡単で而もリードLを弾性片としてパツケージの
固定保持用に兼用させているから、安価に製造す
ることができる。
As described above, according to the present invention, an arbitrary number of IC packages can be placed at the same location by improving the shape of the IC package.
IC packages can be stacked and mounted, greatly reducing the mounting area.
Furthermore, electrical and mechanical connections can be made simply by stacking the IC packages, so the number of layers in the IC package can be easily changed. Furthermore, since the structure is very simple and the lead L is used as an elastic piece for fixing and holding the package, it can be manufactured at low cost.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本考案の実施例であるICパツケージ
をプリント基板に実装する手順を説明する図、第
2図は同ICパツケージを6個実装後の外観斜視
図、第3図は使用例を示す図である。 PはICパツケージ、Lはリード、PWBはプリ
ント基板、Sは半田、Bはワイヤ、Cは配線パタ
ーン。
Figure 1 is a diagram explaining the procedure for mounting an IC package, which is an embodiment of the present invention, on a printed circuit board, Figure 2 is a perspective view of the external appearance after six IC packages are mounted, and Figure 3 is an example of usage. It is a diagram. P is the IC package, L is the lead, PWB is the printed circuit board, S is the solder, B is the wire, and C is the wiring pattern.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] パツケージ本体の天面の略中央部に外周壁にリ
ードを配設してなる凸状のコネクター部を設け、
また底面の上記凸状コネクター部に対応する位置
に内周壁に上記リードの一方を導いて配設してな
る凹状のコネクター部を設けると共に、上記両コ
ネクター部は互いに電気的且つ機械的に装着自在
の関係にあるように形成してなることを特徴とす
るICパツケージ。
A convex connector part with leads arranged on the outer peripheral wall is provided approximately in the center of the top surface of the package body,
Further, a concave connector part is provided on the bottom surface at a position corresponding to the convex connector part, and the concave connector part is formed by guiding one of the leads to the inner circumferential wall, and both the connector parts can be electrically and mechanically attached to each other. An IC package characterized by being formed so as to have the following relationship.
JP11207781U 1981-07-27 1981-07-27 IC package Granted JPS5818346U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP11207781U JPS5818346U (en) 1981-07-27 1981-07-27 IC package

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP11207781U JPS5818346U (en) 1981-07-27 1981-07-27 IC package

Publications (2)

Publication Number Publication Date
JPS5818346U JPS5818346U (en) 1983-02-04
JPS6127183Y2 true JPS6127183Y2 (en) 1986-08-13

Family

ID=29906418

Family Applications (1)

Application Number Title Priority Date Filing Date
JP11207781U Granted JPS5818346U (en) 1981-07-27 1981-07-27 IC package

Country Status (1)

Country Link
JP (1) JPS5818346U (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2794972B2 (en) * 1991-03-12 1998-09-10 イビデン株式会社 Leadless chip carrier

Also Published As

Publication number Publication date
JPS5818346U (en) 1983-02-04

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