JPS5961158A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPS5961158A
JPS5961158A JP57171245A JP17124582A JPS5961158A JP S5961158 A JPS5961158 A JP S5961158A JP 57171245 A JP57171245 A JP 57171245A JP 17124582 A JP17124582 A JP 17124582A JP S5961158 A JPS5961158 A JP S5961158A
Authority
JP
Japan
Prior art keywords
capacitor
pad
integrated circuit
chip
power supply
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP57171245A
Other languages
Japanese (ja)
Inventor
Tetsushi Wakabayashi
哲史 若林
Kiyoshi Muratake
村竹　清
Hiromi Yanagida
柳田　浩美
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP57171245A priority Critical patent/JPS5961158A/en
Publication of JPS5961158A publication Critical patent/JPS5961158A/en
Pending legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
    • H01L23/64—Impedance arrangements
    • H01L23/642—Capacitive arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1515—Shape
    • H01L2924/15153—Shape the die mounting substrate comprising a recess for hosting the device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/15165—Monolayer substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/161—Cap
    • H01L2924/1615—Shape
    • H01L2924/16195—Flat cap [not enclosing an internal cavity]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/1901—Structure
    • H01L2924/1904—Component type
    • H01L2924/19041—Component type being a capacitor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/30107—Inductance

Landscapes

  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Lead Frames For Integrated Circuits (AREA)

Abstract

PURPOSE:To reduce inductance while minimizing mounting density by incorporating not only an integrated circuit chip but also a capacitor for a bypass in one package. CONSTITUTION:Multilayer green sheets 5a-5d are laminated, a plurality of external leads 3 are set up to left and right sections, and the integrated circuit chip 5 and the capacitor 6 for the bypass are placed on the green sheets 5b, 5c. Leads 8 are connected to a plurality of pads 7 set up on the green sheet 5c through bonding from the chip 5, and a pad 10G for grounding and a pad 10V for a power supply are also fitted at both ends of the capacitor 6. When there are terminals 12, 11 for grounding and a power supply in the vicinity of sections where the chip 5 and the capacitor 6 are disposed, leads 8G, 8V are shortened, unnecessary inductance is not made contain, mounting density is reduced and there is no possibility of mutual pulsing noises of a plurality of integrated circuits to be generated when the leads 8G, 8V are connected directly to the pad 10G and the pad 10V through bonding.

Description

【発明の詳細な説明】 （１）発明の技術分野 本発明は半導体装置に係り、特に集積回路パッケージ内
にチップコンデンサを組め込んた半導体装置に関する。DETAILED DESCRIPTION OF THE INVENTION (1) Technical Field of the Invention The present invention relates to a semiconductor device, and more particularly to a semiconductor device in which a chip capacitor is incorporated into an integrated circuit package.

（２）技術の背景 近時、半導体装置の集積度が向上するとともに処理スピ
ードが上がってきたために、集積回路を駆動するための
電源供給時に付加するバイパス用コンデンサを接続する
ためのり一ト°線の長さ、すなわちインダクタンス成分
や、プリント基板に取りイ」りられるバイパス用コンデ
ンサ自体の大きさによって実装時に大型化する等の問題
がり１コーズアツプされてきている。(2) Background of the technology In recent years, as the degree of integration of semiconductor devices has improved and the processing speed has also increased, glue lines are used to connect bypass capacitors that are added when supplying power to drive integrated circuits. Problems such as increased size during mounting due to the length of the capacitor, that is, the inductance component, and the size of the bypass capacitor itself that is mounted on the printed circuit board, have become more and more problematic.

すなわち、従来はプリント基板上に集積回路をパッケー
ジした半導体装置を複数個ハンダ付けした場合に複数の
半導体装置に対して一つのバイパス用コンデンサを付加
して電源よりのパルス性雑音の吸収を行わせていたが、
複数の集積回路自体も個々に種々の動作を行っているた
めに集積回路自体もノイズを発生し、複数の集積回路相
互間に影響を及ぼす問題があり、集積回路をパッケージ
した複数の半導体装置の個々にバイパス用コンデンサを
イ１加するようになってきている。In other words, conventionally, when multiple semiconductor devices packaged with integrated circuits are soldered onto a printed circuit board, one bypass capacitor is added to each of the semiconductor devices to absorb pulse noise from the power supply. was, but
Since the multiple integrated circuits themselves individually perform various operations, the integrated circuits themselves also generate noise, which causes problems that affect the interconnections between the multiple integrated circuits. Bypass capacitors are now being added individually.

この場合、個々のパッケージされた集積回路に外付りの
バイパス用コンデンサを接続するためにリード線が長く
なり、不用なインダクタンスを含むことになり、実装密
度も大きくなる欠点があり、これらの問題を解決するよ
うな要望があった。In this case, in order to connect external bypass capacitors to individual packaged integrated circuits, the lead wires become long and contain unnecessary inductance, and the packaging density also increases. There was a request to solve the problem.

（３）従来技術と問題点 第１図は従来の複数の集積回路をパッケージした半導体
装置２ａ、２ｂをプリント晶析ｌ上に実装した場合の斜
視図であり、プリント基板Ｉに穿たれた透孔６へ積回路
をパッケージした半導体装置２ａ、２ｂの外部り−トを
挿入し、ハンダ付けでプリント板上の外部回路（図示せ
ず）に接続するとともに半導体装置２ａ、２ｂはプリン
ト基板上に固定され、例えば電源供給端子３ａ′。(3) Prior Art and Problems Figure 1 is a perspective view of a conventional semiconductor device 2a, 2b packaged with a plurality of integrated circuits mounted on a printed crystallizer l. Insert the external circuits of the semiconductor devices 2a, 2b with packaged circuits into the holes 6, and connect them to the external circuits (not shown) on the printed board by soldering, and the semiconductor devices 2a, 2b are mounted on the printed board. For example, the power supply terminal 3a' is fixed.

３ｂ′と接地端子３ａ、３ｂ間Ｇこそれぞれバイパス用
コンデンサ４ａ、４ｂが外部すされて、上記したように
電源よりのパルス性雑音及び集積回路２ａ、２ｂの個々
の回路より発生ずるパルス性雑音を吸収させている。Bypass capacitors 4a and 4b are connected externally between G 3b' and ground terminals 3a and 3b, respectively, to eliminate pulse noise from the power supply and pulse noise generated from the individual circuits of integrated circuits 2a and 2b, as described above. is absorbed.

しかし、上述の構成による実装構造では電源供給端子３
ａ’、３ｂ’がらコンデンサ４ａ、４ｂに至るリート°
線及び接地端子３ａ、３ｂがらコンデンサ４ａ、４ｂに
至るリート線（実際にはプリント基板にバターニングさ
れるかり一ト４ａ′。However, in the mounting structure with the above configuration, the power supply terminal 3
Leet from a', 3b' to capacitors 4a, 4b°
The wire and grounding terminals 3a, 3b lead to the capacitors 4a, 4b (actually, the wires 4a' are patterned on the printed circuit board).

４ｂ’として示す）が長くなり、不用なインダクタンス
を含むだけでなくパルス性ノイズをひろい、更に実装密
度が大となる欠点を生ずる。4b') becomes long, which not only includes unnecessary inductance, but also increases pulse noise, and also causes the drawbacks of increased packaging density.

（４）発明の目的 本発明は上記した従来の欠点に鑑み、インダクタンスを
小とし、実装密度を小とした半導体装置を提供すること
を目的とするものである。(4) Purpose of the Invention In view of the above-mentioned conventional drawbacks, it is an object of the present invention to provide a semiconductor device with low inductance and low packaging density.

（５）発明の構成 本発明の特徴とするところは、集積回路チップを収容す
るパッケージの凹部内にコンデンサを一体に組み、該凹
部を封止してなることを特徴とする半導体装置によって
達成される。(5) Structure of the Invention The feature of the present invention is achieved by a semiconductor device characterized in that a capacitor is integrally assembled in a recess of a package housing an integrated circuit chip, and the recess is sealed. Ru.

（６）発明の実施例 以下、本発明の一実施例を第２図乃至第５図について説
明する。(6) Embodiment of the Invention An embodiment of the present invention will be described below with reference to FIGS. 2 to 5.

第２図は本発明の一実施例を示す集積回路チップ並びに
バイパス用コンデンサをパンケージ内に封止した場合の
キャップを切断した平面図、第３図は第２図のＡ−Ａ’
断面矢視図であり、半導体装置乏は例えば第３図に示す
如く多層のグリンシート５ａ、５ｂ、５ｃ、５．ｄが積
層され、左右に複数の外部リート３が設けられ、集積回
路チップ５及びチップコンデンサ（バイパス用コンデン
サ）６がグリーンシート５ｂ、５ｃ上に載置され、集積
回路チップ５からはグリーンシー）５ｃ上に設けた複数
のパッド７にボンディングによってり−１８が接続され
、チップコンデンサ６の両端にも接地用のパッドＩＯＧ
と電源用のパッドＩＯＶが設りられ、集積回路チップ５
とチップコンデンサ６が配設される近傍に接地及び電源
供給用端子１２．１１がある場合にはチップコンデンサ
の接地用バノｔ”　ｉ　ｏ　ｃと電源用パッドＩＯＶに
ホンディングによって直接リード８Ｇ、８Ｖを接続させ
てもよいが、例えば集積回路チップ５の接地用のパン１
が７Ｇで示す位置にある場合等はチップコンデンサ６の
接地用パンＦ　１０　Ｇよりグリーンシート５Ｃにスル
ーボール１４を穿ら、該スルーホールを通じてグリーン
シート５ｂ上のパターンＩ５を経て外部リート−３に接
続し、更に集積回路チップ１５の接地用パット’　７　
Ｇに連接するグリーンシー１−５　Ｃ−にのパターン１
６と外部シーＦ’　３とを接続するようにするを可とす
る。FIG. 2 is a plan view with the cap cut away when an integrated circuit chip and a bypass capacitor are sealed in a pan cage, showing an embodiment of the present invention, and FIG. 3 is a cutaway plan view taken along the line A-A' in FIG.
This is a cross-sectional view taken in the direction of arrows, and the semiconductor device is formed by, for example, multilayer green sheets 5a, 5b, 5c, 5. d are stacked, a plurality of external REITs 3 are provided on the left and right, an integrated circuit chip 5 and a chip capacitor (bypass capacitor) 6 are placed on green sheets 5b and 5c, and from the integrated circuit chip 5 there is a green sheet). -18 is connected to a plurality of pads 7 provided on the chip capacitor 5c by bonding, and grounding pads IOG are also connected to both ends of the chip capacitor 6.
A pad IOV for power supply is provided, and the integrated circuit chip 5
If there is a grounding and power supply terminal 12.11 near where the chip capacitor 6 is installed, connect the lead 8G directly to the grounding terminal of the chip capacitor and the power supply pad IOV by bonding. 8V may be connected, but for example, the grounding pan 1 of the integrated circuit chip 5
is at the position shown by 7G, a through ball 14 is drilled in the green sheet 5C from the grounding pan F10G of the chip capacitor 6, and the through ball 14 is passed through the through hole to the external lead 3 via the pattern I5 on the green sheet 5b. Connect and further ground the integrated circuit chip 15' 7
Green sea 1-5 connected to G Pattern 1 to C-
6 and the external sea F'3.

上記実施例では接地用パッドの接続について説明したが
、電源パッド間どうしでもスルーホールと多層のグリー
ンシートを用いて互いに接続するようにできる。In the above embodiment, connection of grounding pads has been described, but power supply pads can also be connected to each other using through holes and multilayer green sheets.

なお、１３はパッケージを最終的に封止するキャップで
ある。Note that 13 is a cap that finally seals the package.

第４図は本発明の他の実施例を示すもので、第５図は第
４図のＢ−Ｂ　′断面図である。この場合の構成は集積
回路チップ５とチップコンデンサ６とは第２図のように
近接して配設されて以内ために集積回路チップ５の四辺
にポンディング用のパッド７を配設することができる。FIG. 4 shows another embodiment of the present invention, and FIG. 5 is a sectional view taken along line BB' in FIG. In this case, since the integrated circuit chip 5 and the chip capacitor 6 are arranged close to each other as shown in FIG. 2, pads 7 for bonding can be arranged on the four sides of the integrated circuit chip 5. can.

このために多層に積層したグリーンシート上のパターン
とスルーボールによって集積回路デツプ５の接地用パッ
ト′７Ｇとチップコンデンサ６の接地用パッドＩＯＧは
接続され、集積回路チップ５の電源用パットとチップコ
ンデンサ６の電源用パットＩＯＶも同様に接続されるが
、これらの構成は第５図には省略して示されていない。For this purpose, the grounding pad '7G of the integrated circuit deep 5 and the grounding pad IOG of the chip capacitor 6 are connected by the pattern on the multi-layered green sheet and the through ball, and the power supply pad of the integrated circuit chip 5 and the chip capacitor 6 are connected. Power supply pad IOV No. 6 is also connected in the same manner, but these structures are omitted and not shown in FIG.

集積回路チップ５の四辺よりボンディングリートを引き
出すために集積回路チップ５はキャビティ１７内に載置
し、チップコンデンサ６も同様にグリーンシート上のキ
ャピテイ１８ブ内に配設ずるようになし、キャップ１３
はシームウェルディングによって固着させるようになす
。In order to pull out the bonding leads from the four sides of the integrated circuit chip 5, the integrated circuit chip 5 is placed in the cavity 17, and the chip capacitor 6 is similarly placed in the cavity 18 on the green sheet.
are fixed by seam welding.

（７）発明の効果 以上詳唱■に説明したように、本発明の半導体装置によ
れば、集積回路チップとともにバイパス用τ１ンデンナ
も一つのパッケージに内蔵させたためにインダクタンス
を小さくすることができるだりでなく、外部よりの誘導
ハノ、等をひろう可能性は完全にパッケージされたキャ
ップ内にあるためにほとんど皆無であり、プリン１−基
板上に集積回路をパッケージした複数の半導体装置を配
設した場合にも相互に発生ずるノイズを気にする必要も
ないだ４ノでなく、実装密度も大きくできる特徴を有す
る。(7) Effects of the Invention As explained in detail above, according to the semiconductor device of the present invention, the inductance can be reduced because the bypass τ1 indenna is built into one package together with the integrated circuit chip. However, there is almost no possibility of leaking induction wires, etc. from the outside because the cap is completely packaged. In addition, there is no need to worry about mutually generated noise, and the packaging density can be increased.

【図面の簡単な説明】[Brief explanation of the drawing]

第１図は従来の集積回路をパッケージした半導体装置を
プリント基板上に実装した斜視図、第２図は本発明の半
導体装置のキャップを切断した平面図、第３図は第２図
のＡ−Ａ　′断面矢視図、第４図は本発明の他の実施例
を示す半導体装置の第２図と同様の平面図、第５図は第
４図のＢ−Ｂ　’断面矢視図である。 １・・・プリント基板、　　２．　２ａ、２ｂ・・・半
導体装置、　３．３ａ、３ｂ・・・外部り−ト、　　４
ａ’、　　４ｂ　′　−リード、　　５　・　・　・集
積回路チップ、　６・・・チップコンデンサ、７・・・
パッド、　　８・・・ホンティング用リード、　　８Ｇ
・・・接地用リート、　　８■・・・電源用リート、　
　ＩＯＣ・・・接地用バット、１０Ｖ・・・電源用パッ
ド、　　１３・・・キャップ、　１４・・・スルーホー
ル、　１５．１６・、・パターン。FIG. 1 is a perspective view of a conventional semiconductor device packaged with an integrated circuit mounted on a printed circuit board, FIG. 2 is a plan view of the semiconductor device of the present invention with the cap cut away, and FIG. 4 is a plan view similar to FIG. 2 of a semiconductor device showing another embodiment of the present invention, and FIG. 5 is a sectional view taken along line B-B' in FIG. 4. . 1...Printed circuit board, 2. 2a, 2b...Semiconductor device, 3.3a, 3b...External route, 4
a', 4b' - lead, 5... integrated circuit chip, 6... chip capacitor, 7...
Pad, 8...Honting lead, 8G
...Leat for grounding, 8■...Leat for power supply,
IOC...Grounding bat, 10V...Power supply pad, 13...Cap, 14...Through hole, 15.16...Pattern.

Claims (1)

【特許請求の範囲】[Claims] 集積回路チップを収容するパッケージの凹部内に＝１ン
デンザを一体に組み、該凹部を封止してなることを特徴
とする半導体装置。1. A semiconductor device characterized in that a =1 densifier is integrally assembled in a recess of a package that accommodates an integrated circuit chip, and the recess is sealed.
JP57171245A 1982-09-30 1982-09-30 Semiconductor device Pending JPS5961158A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP57171245A JPS5961158A (en) 1982-09-30 1982-09-30 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP57171245A JPS5961158A (en) 1982-09-30 1982-09-30 Semiconductor device

Publications (1)

Publication Number Publication Date
JPS5961158A true JPS5961158A (en) 1984-04-07

Family

ID=15919732

Family Applications (1)

Application Number Title Priority Date Filing Date
JP57171245A Pending JPS5961158A (en) 1982-09-30 1982-09-30 Semiconductor device

Country Status (1)

Country Link
JP (1) JPS5961158A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6245848U (en) * 1985-09-06 1987-03-19

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5399460A (en) * 1977-02-10 1978-08-30 Nippon Electric Co Integrated circuit device

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5399460A (en) * 1977-02-10 1978-08-30 Nippon Electric Co Integrated circuit device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6245848U (en) * 1985-09-06 1987-03-19

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