JPS61270666A - Display method for digital data - Google Patents

Abstract

PURPOSE:To judge the contents of input digital data while grasping its variation with time by forming a boundary mark at a timing position where the input digital data varies and displaying the input digital data almost at the center position of a section specified with marks. CONSTITUTION:The input data in binary code is converted by a code converting circuit 11 into data a hexadecimal code, and a counting circuit 12 for the number of continuation detects the timing where the digital data varies and also counts the number of the same digital data present in a section formed by the timing. Then, a frame generating circuit 13 generates the boundary line of the position corresponding to the timing of the variation of the digital data and the number of connection lines is determined in correspondence to the number of the same continuous digital data to determine the size of a frame. The display position of the data in hexedecimal code is displayed by a code display circuit 14 almost at the center position of the sectioned formed by boundary lines, so the visibility is improved.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method of displaying digital data suitable for use in displaying the output of a logic analyzer used for CP LJ checking and the like.

[Summary of the invention]

The invention relates to a digital data display method used for displaying the output of a logic analyzer, etc., in which a boundary line is displayed only at the timing when the digital data changes in time synchronization with the pulse waveform display, and a boundary line formed by the boundary line is displayed. By continuously displaying numerical values corresponding to the same digital data in the interval defined by the boundary lines, it is possible to easily understand the contents of the digital data while grasping the temporal changes in the data. This is a digital data display method that allows users to make judgments and display a large amount of digital data at once.

[Conventional technology]

Conventionally, when trying to analyze digital data, for example, a logic analyzer is used.

A logic analyzer is used to analyze phenomena that involve the operation of software and hardware, and generally the software operation of the system under test is monitored using an external clock (for example, the operating clock of a microprocessor). The operation of the barware is sampled asynchronously using the timing input and the internal clock of the 1'j chic analyzer using the timing input and the timing input is connected to the CRT display. It is configured to be displayed on the screen.

For example, the 8-pin l-(:1-like CF') Cl and its peripheral circuits are connected to the L1 knock analyzer, and the output of each channel is [H- ] or [I, ] is determined, and the data is analyzed over a predetermined -1-dispersion. SoshiC,
In the timing display, the output of each channel is displayed using a pulse wave system. For example, in the case of 8-bit digital data, eight pulse trains are displayed on the CRT display. Also, in stay I/display, C
For example, on the RT display, as shown in Figure 4,
It is displayed in binary and hexydecimal format, and then disassembled and displayed in mnemonic format.

[Problems that the invention attempts to solve] However, in the conventional display method, when the digital data is displayed in ST1-1, the digital data is
Because it is displayed numerically, it is difficult to understand the temporal changes in digital data. Also, when timing is displayed, the digital data is expressed by multiple (for example, 8) pulse trains, so it is difficult to understand the changes in the data itself. It was difficult to determine its meaning.

Further, when displaying both the state display and the timing display on the same screen, for example, there is a problem that the amount that can be displayed at one time is limited.

Therefore, an object of the present invention is to provide a digital display method that allows the content of digital data to be easily determined while grasping temporal changes in the data, and that also enables display of a large amount of digital data at one time. It is to provide (Y).

[Means for solving problems]

In this invention, the pulse waveform display of clock pulses or digital data and the 1-Yarakuta display of input digital data are displayed on the same screen in the same month, and the character display is performed as the input digital data changes. A digital data display comprising a boundary mark formed at a timing position and a display of the value of input digital data displayed approximately at the center of the interval defined by the boundary mark. It's a method.

[Effect]

Based on the image data, the boundary line is displayed at the same time as the pulse waveform display at the timing when the digital data changes, and the digital data that is continuously generated in the section formed by the boundary line is displayed. A corresponding numerical value is displayed at a position approximately in the center of the section formed by the boundary lines, and a connecting line is displayed between the boundary lines.

〔Example〕

An embodiment in which the present invention is applied to the output display of a logic analyzer will be described below with reference to the M plane.

In FIG. 1, the processing procedure implemented by the software of the microcomputer indicated by 1 in FIG. 2 is expressed in functional blocks for easy understanding.

In FIG. 2, a device under test to be checked, such as a CP tJ with specifications of 8 pins 1 to 1 and its peripheral circuits, is connected to the logic analyzer indicated by 2, although not shown. rHJ, "I," of each channel output of CPIJ is determined with respect to a specific clock, and a state display output corresponding to the operation of the software is generated in the logic analyzer 2, and a state display output corresponding to the operation of the hardware is generated. A corresponding timing display output is generated in the logic analyzer 2. This state display output and timing display output are supplied to the microcomputer 4 via the interface 3.

In the microcomputer 4, processing as shown in FIG. 1 is performed. Binary code input data is code-converted in a code conversion circuit 11 and converted into hexadecimal code. This output is continuous failure old number circuit 12
When the timing of changes in digital data is detected! (The number of identical digital data existing in the section formed by each timing of data change is counted.

In the frame generation circuit 13, a boundary line is generated at a position corresponding to the timing at which the digital data changes, and the number of connection lines is determined according to the number of consecutive identical digital data, and the size of the frame is determined. be done. Further, the code display circuit 14 determines that the display position of the hexadecimal code data is approximately at the center of the section formed by the boundary line.

In the image forming circuit 15, image data corresponding to the size of the frame and the display position of the hexadecimal nino F is generated in temporal synchronization with the timing display, and this image data is supplied to the display circuit 16.

That is, -Lj data processing is performed by the microcomputer 1 and the character generation circuit 4. For example, at the timing when the digital data changes, the character code C1 for displaying the boundary line is called out by the microcomputer 1 and taken into the microcomputer 1.

Furthermore, between the boundary lines, character codes 1-'C2 for displaying connection lines connecting the boundary lines are called in the same manner and are taken into the microcomputer 1.

Furthermore, a character code FC3 for displaying a hexadecimal code at a position approximately in the center of the section formed by the boundary line is similarly called out and taken into the microcomputer 1.

Character coat C obtained on microcomputer 1
I, C2, and C3 connect to C through the CRT interface 5.
CRT display 6 supplied to RT display 6
Values and lines corresponding to character codes C1, C2, and C3 are displayed on the display screen in time synchronization with the timing display.

FIG. 3 shows an example of the display screen of this embodiment.

In Fig. 3, the clock is indicated by GK, and the pulse waveform display of digital data of 8 bits I~) is shown as ■)0~D.
7, and corresponding character representations are indicated by O19. For example, in a character display CD, the border line 20 is displayed by the character code C], the connecting line 21 is displayed by the character code C2, and the hexadecimal values 22 and 23 are the character code ['C].
3 is displayed.

As is clear from Figure 3, a border line is displayed where there is a change in digital data, and where there is no change in digital data, they are regarded as one degree and displayed in one frame, and the The value corresponding to the hexadecimal coat is displayed in the center position.

Character codes C1, C2, C3 are also supplied to the printer 8 via the printer interface 7, and the values and lines corresponding to the character codes C1, C2°03 are displayed in time synchronization with the timing display as necessary. It will be printed.

In one embodiment of the present invention, a method for displaying 8-bit digital data has been described, but the present invention can be easily applied to displaying digital data with other bit numbers.

〔Effect of the invention〕

In this invention, the boundary line is displayed only at the timing when the digital data changes in time synchronization with the pulse waveform display, and the numerical value corresponding to the same digital data that is continuously generated in the section formed by the boundary line is displayed. is displayed at approximately the center of the section formed by the boundary line.

Therefore, according to the present invention, the content of digital data can be easily understood while grasping temporal changes in the digital data, and visibility is improved. Furthermore, according to the present invention, the conventional pulse waveform display G requires display of eight pulse trains in the case of 8-bit digital data, but can be reduced to one display. It can display 8 times more data at once.

[Brief explanation of the drawing]

FIG. 1 shows a functional program used to explain one embodiment of the present invention.
1 and 2 are block diagrams of one embodiment of this invention, FIG. 3 is a route map of an example of a display screen in one embodiment of this invention, and FIG. 4 is used to explain the conventional technology. This is a route map. Explanation of main symbols in the drawings 1: Microcomputer, 2: 11 Shift analyzer, 4: Character generator, 6: CRT display.

Claims (1)

[Claims] A pulse waveform display of the clock pulse or digital data and a character display of the input digital data are displayed in synchronization on the same screen, and the character display is formed at a timing position where the input digital data changes. A method for displaying digital data, comprising: a boundary mark; and a display of the value of the input digital data, which is displayed approximately in the center of an interval defined by the boundary mark.