JPS5835646A - Operation analyzing device for central processing system - Google Patents

Abstract

PURPOSE:To reduce hardware of a monitor part, by lowering or stopping temporarily the clock frequency given to a CPU during the analyzing operation to make the analysis due to software possible. CONSTITUTION:When an address bus monitor part ABS of an operation analyzing device 2 detects the address of the analysis start, a signal is sent to a clock generator CLK to lower the clock frequency. Simultaneously, the analysis start is displayed. When finding the display of the analysis start, an analyzing part 4 reads contents on an address bus, a control bus, and a data bus to perform the analysis. Since the analyzing operation is performed by software of the analyzing part 4, the speed is comparatively low. Consequently, it is necessary that the clock frequency is lowered to such speed that the analyzing operation follows the clock frequency sufficiently. Thus, the quantity of hardware in the monitor part 3 becomes small because information is not accumulated in the monitor part 3.

Description

[Detailed description of the invention] The present invention relates to an operation analysis device for a central processing system.

Conventionally, this type of operation analysis device for a central processing system is composed of hardware for monitoring the operation of a central processing unit (hereinafter referred to as CPU) and software for analyzing the monitoring results.

Monitoring the operation of the CPU requires high-speed operation, and n1 analysis requires a considerable amount of processing, so the former is realized by hardware and the latter by software.
was. In other words, the method used was to accumulate data for analysis using hardware and analyze it later. Therefore, there is a drawback that the content that can be analyzed is limited depending on the amount of data stored.

The present invention provides a clock to be applied to a CPU whose operation is to be analyzed.

The purpose of the present invention is to provide an apparatus that solves the above-mentioned drawbacks by controlling the flow rate to create time necessary for analysis and performing analysis simultaneously with the operation of the CPU.

According to the present invention, in a device connected to a path line of a central processing system to analyze system operation, when an address for starting operation analysis is detected, the frequency of the clock signal applied to the central processing unit is lowered.

or a device for analyzing the operation of a central processing system, which has means for temporarily stopping the system, and means for reading the contents of a control signal, a data bus, and an address bus, and analyzes the operation of the system from the read information. Get it.

In other words, the CPU operates in synchronization with the clock, so if you lower the clock frequency or pause it, the CPU operates in synchronization with the clock.
operation slows down or stops.

Therefore, it becomes possible to perform analysis simultaneously with the operation of the CPU.

Next, referring to the drawings, an embodiment of the present invention will be explained, consisting of Φ7 and a pass line BL. Reference numeral 2 denotes a motion analysis device according to the present invention, which includes a monitoring section 3 and an analysis section 4. Furthermore, the monitoring section includes an ABS that monitors the address bus and a CBS that monitors control signals.

It consists of a DBS that monitors the data bus and a CLK that generates clock signals. In addition, the analysis part is the CPU, memory MEM
, consisting of the display device DISP and the electronic key section KEY.
Ru.

When this motion analysis device 2 is inserted into a system 1 to be motion analyzed and its motion is started, a clock is initially supplied from CLK at a normal frequency. The ABS monitors the state of the address bus and waits for an address to appear on the address bus to begin analysis. At this time.

The control signal monitored by CBS is used as the sampling signal. The analysis start address is written into the ABS as data by the analysis unit 4.

When the ABS detects the address to start analysis, it sends a signal to CLK and lowers the clock frequency. At the same time, a message indicating the start of analysis is displayed. The analysis unit 4 monitors the ABS, and when it finds the indication that the analysis has started, it detects the ABS and CBS.

D) The contents of the address bus, control bus, and data bus are read and analyzed through the 3 S units) t-. The analysis operation is relatively slow because much of it is performed by the software of the analysis section 4. Therefore, at this time, it is necessary to lower the clock frequency to a speed that allows the analysis operation to follow sufficiently. When the analysis section 4 detects that the address at which the analysis operation ends is reached, it sends a signal to CLK to return the frequency to its original value. This causes the CPU to return to normal operation. The results of analysis in this way are stored in memo I) MEMK and displayed on device D.
Display on ISP. The start and end addresses of analysis are set using the electronic key KEY.

In this embodiment, since information is not stored in the monitoring section 3, the amount of hardware in the monitoring section 3 is reduced.

Also, since the analysis results are accumulated, the amount of information to be accumulated is
J-limit, and the amount of hardware of the analysis section 4 becomes small.

The content of the analysis is generally limited to analysis of instruction codes and accumulation of address information, but in this example, the analysis is performed by software, so it is possible to analyze the information from the address to the label (
This has the effect of easily adding functions such as conversion to a temporary name given to a fixed address, displaying the contents of a register, and counting the number of times a specific address has passed.

In this example, a method of lowering the clock frequency is adopted, but it is also possible to stop the clock when analysis starts, and then repeat the operation of outputting black and red again when the analysis of l operation cycle is completed. It has a similar effect.

In the present invention, although it is unavoidable that the CPU operation becomes slow, the influence can be minimized by determining the start and end addresses of analysis and lowering the clock rate only during that time. Furthermore, it is believed that the number of cases in which operational delay becomes a problem is actually rare.

As explained above, the present invention enables analysis by software by lowering or temporarily stopping the clock frequency applied to the CPU during analysis operation, so the hardware of the monitoring unit becomes smaller and the content of analysis can be made more detailed. This has the effect of

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing one embodiment of the present invention. CPU...Central processing unit, CLK...
Black, ri generator, ABS...Address bus monitoring section,
CBS... Control signal monitoring section %DBS...
・Data bus monitoring unit, MEM... Memo IJ-,
KEY: Electronic key section, DISP: Display section.

Claims (1)

[Claims] In a device connected to a path line of a central processing system to analyze system operation, means for lowering or temporarily stopping the frequency of clock signals given to the central processing unit when an address for starting operation analysis is detected, and a control signal , data bus, and