JPS61269705A - Programmable controller - Google Patents

Abstract

PURPOSE:To facilitate the debugging processing, etc., of a programmable controller by providing a control circuit which executes one step of a user program in response to a command from a general processor in a dedicated processor. CONSTITUTION:The one-step execution control circuit 107 which executes one step of the user program in response to a command from the general processor 9 is provided in the dedicated processor 10. When a one-step execution command for debugging, etc., is supplied from a programming console 7 to the processor 9, the processor 9 sends out 1 as both the least significant digit bit and the 1st bits of a data bus DB to access a circuit 107 at the same time. Then, an internal FF is set for a maximum time required for one step of a basic instruction and a clock pulse CP is supplied to a program counter 10. At this time, clock pulses CP are supplied to the counter by two machine cycles and one step of the basic instruction is executed in the processor 10 in response to the command from the processor 9.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of the Invention) The present invention relates to an improvement in a programmable controller that achieves increased instruction execution speed.

(Summary of the Invention) The present invention provides a scanning-type programmable controller that uses both a general-purpose processor for executing application instructions and a dedicated processor for executing basic instructions to achieve faster instruction execution speed. The controller has a built-in control circuit that enables single-step execution of a user program in response to commands from the general-purpose processor, thereby facilitating debugging and other operations in this type of combined programmable controller. .

(Prior art and its problems) FIG. 6 shows the hardware configuration of a conventional general programmable controller.

This programmable controller uses a general-purpose microprocessor 1. System memory composed of ROM2.
3. User program memory configured with battery backup or FROM, etc.; 4. I10 memory configured with RAM; 4. Crab knit 5. It is mainly composed of an output unit 6 and a programming console 7.

Note that 8 is system memory 2. User program memory 3. This is an address decoder for chip selecting the I10 memory 4.

Furthermore, as is well known, the system memory 2 stores control programs and interpreter programs that govern the basic operations of the programmable controller, and the user program memory 3 stores, for example, programs that the user can freely program. A series of commands corresponding to the set ladder diagram are stored, and input data read from the input unit 5 and output data to be sent to the output unit 6 are also stored in the I10 memory 4.

In this programmable controller, one of the general-purpose registers in the microprocessor 1 is assigned as a program counter 1a, and this program counter 1
The user program memory 3 is accessed sequentially depending on the contents of a.

Therefore, when a one-step execution command is issued from the programming console 7 during debugging or the like, one instruction specified by the program counter 1a is read from the user program memory 3, and executed according to the system program. Detecting the end of its execution,
It is sufficient to simply stop the progress of the program counter 1a.

In this way, a programmable controller that uses only the general-purpose microprocessor 1 can easily perform one-step execution processing, but on the other hand, it takes time to perform bit processing with a general-purpose microprocessor, and There are limits to output responsiveness.

Therefore, in recent programmable controllers, a dedicated microprocessor that is good at bit processing is used for basic instructions such as LD, AND, OR, and OUT, and data processing is used for applied instructions such as CNT and TIM. The configuration uses a general-purpose microprocessor that specializes in

However, in programmable controllers that use both a general-purpose processor for executing application instructions and a dedicated processor for executing basic instructions, the dedicated processor side has a built-in program counter, so the general-purpose processor side Therefore, it is difficult to manage the program counter from the start, and as a result, an extremely complicated circuit configuration must be adopted in order to enable one-step execution processing.

(Objective of the Invention) An object of the present invention is to provide a scanning-type programmable controller that uses a general-purpose processor for executing application instructions and a dedicated processor for executing basic instructions, and that uses a simple circuit configuration to process one-step execution. We aim to make this possible.

(Structure and Effects of the Invention) In order to achieve the above object, the present invention provides a scanning-type programmable controller that uses both a general-purpose processor for executing application instructions and a dedicated processor for executing basic instructions; The present invention is characterized in that a control circuit is provided in the special-purpose processor to enable one-step execution of a user program in response to a command from a general-purpose processor.

According to such a configuration, it is possible to perform one-step execution processing with an extremely simple circuit configuration and by simply performing a simple command sending process on the general-purpose processor side.

(Description of Embodiments) FIG. 1 is a block diagram showing the hardware configuration of a programmable controller according to the present invention. In this figure, the same components as those of the conventional example shown in FIG. 6 are designated by the same reference numerals, and the explanation thereof will be omitted.

This programmable controller mainly consists of a general-purpose processor 9 for executing application instructions and a dedicated processor 10 for executing basic instructions.

The dedicated processor 10 includes a user program memory 3.
program counter 101. An instruction decoder 102 for decoding instructions read from the user program memory 3. In addition to an arithmetic circuit 103 for executing the decoded instructions, a multiplexer 104 . Similarly, a multiplexer 105 and a program counter 101 . User program memory 3. A multiplexer 106 is provided for selectively connecting the data bus of the I10 memory 4 to the general-purpose microprocessor 9.

The configuration up to this point is well known in various documents, so a detailed explanation will be omitted, but in short, the dedicated processor 10 resets the program counter 101 to zero, and then sequentially reads instructions from the user program memory 3. In addition, only when this is a basic instruction, the instruction decoder 102 and arithmetic circuit 103 decode and execute it.On the other hand, when it is decoded as an application instruction, an interrupt command is given to the general-purpose processor 9, and control authority is given. Hand over to the general-purpose processor side.

Then, the general-purpose processor 9 side reads the contents of the program counter 101 at that point, accesses the user program memory 3 based on this, reads the corresponding instruction into the general-purpose processor 9, and executes the corresponding application instruction. It performs processing.

As described above, in a programmable controller that uses both a general-purpose processor for executing application instructions and a dedicated processor for executing basic instructions, the feature of the present invention is that in response to a command from the general-purpose processor 9, one of the user programs
1-step execution control circuit 10 that enables step execution
7 is provided within the dedicated processor 10.

Details of the one-step execution control circuit 107 are shown in FIG.

As shown in the figure, this step actual execution control path is connected to an address decoder 1071 that detects a specific address of the circuit.
In response to the output of this address decoder 1071,
Two D-type flip-flops 1072 and 1073 read the contents of the first bit DB1 of the data bus DB of the general-purpose microprocessor 9, respectively;
Two delay flip-flops 1074 and 1075 delay the 5TOP signal output from the flip-flop 1072 for a predetermined time, and are set by the 5TART signal output from the flip-flop 1073 and reset by the delayed 5TOP signal. an RS flip-flop 1076, an AND gate 1077 that gate-controls the program counter clock CP7 with the Q output of this flip-flop 1076, and a timing pulse generator that is alternatively reset by the RESET signal or the Q output of the flip-flop 1076. It is mainly configured with a circuit 1078.

In the above configuration, when a one-step execution command is given to the general-purpose processor 9 for debugging or the like from the programming console 7, the general-purpose processor 9 sends 1'' to both DBO and DBl of the data bus DB, and simultaneously It is sufficient to access the one-step execution control circuit 107.

The flip-flop 1076 is then held in the set state for the maximum time required for one step of the basic instruction, and supplies a clock pulse CP7 to the program counter 101 (see FIGS. 3 and 4).

Here, as shown in FIG. 5, among the basic commands, LD,
One machine cycle M1 is required for OR and AND, and two machine cycles M1 are required for OUT and KR.
, M2 is required.

Therefore, the clock pulse CP7 is equal to 2 machine cycles.
is supplied to the program counter PC, the dedicated processor 10 responds to the command from the general-purpose processor 9.
This allows one-step execution of a basic instruction within the program.

In this way, in the present invention, the DBO of the data bus DB
, the dedicated processor 1 by sending "1" to each DBI.
By giving a command to 0, it is possible to execute one step of a basic instruction within the dedicated processor 10, and the specific circuit for this purpose is simply a flip-flop and a small number of circuits, as shown in Figure 2. It is only necessary to combine the gate elements, and the dedicated processor 10 can be easily manufactured even if it is constituted by, for example, a gate array.

[Brief explanation of the drawing]

Fig. 1 is a block diagram showing the hardware configuration of the programmable controller according to the present invention, Fig. 2 is a circuit diagram showing details of the one-step execution control circuit, and Fig. 3 shows signal states of each part in Fig. 2. Time chart, Figure 4 is a time chart showing the signal status of each part in Figure 2,
FIG. 5 is a time chart 1-1 showing the relationship between each instruction and a machine cycle. FIG. 6 is a block diagram showing an example of a conventional programmable controller.

Claims (1)

[Claims] (1) In a scanning-type programmable controller that uses both a general-purpose processor for executing application instructions and a dedicated processor for executing basic instructions; executing one step of a user program in response to a command from the general-purpose processor; A programmable controller characterized in that a control circuit that enables said dedicated processor is provided within said dedicated processor.