JPS61269532A - Phase locked loop circuit - Google Patents

Abstract

PURPOSE:To obtain a voltage controlled oscillation output signal with less affected by dropout by switching an input signal during dropout period into an output signal in a phase locked loop control circuit to which a discontinuous signal is inputted due to dropout. CONSTITUTION:A selector circuit 10 selecting the output of a tank circuit 2 and an output of a voltage controlled oscillation circuit 6 is added. The circuit 10 is phase-locked in loop by an output of an envelope detection circuit 7, the output of the circuit 2 while no dropout exists selects the output of the circuit 16 when dropout takes place. An output 11 of the circuit 10 and an output 12 of the circuit 6 input to a phase comparator 3 to generate an error voltage 13 proportional to the phase difference, after the voltage is smoothed by an LPF 5, the result is inputted to the circuit 6. The circuit 6 outputs a signal 12 having a frequency proportional to the input voltage 14 and feeds back it to the circuit 10 and the comparator 3.

Description

[Detailed Description of the Invention] [Field of Application of the Invention] The present invention relates to the improvement of a phase-locked loop circuit (hereinafter referred to as a PLL circuit), which has good retention characteristics even when an input signal is lost. This relates to a PLL circuit.

[Background of the invention]

In recent years, the development of equipment for recording and reproducing digital signals has progressed rapidly. When reproducing digital signals, accurately extracting the clock signal is an important issue. For this reason, a tank circuit or a PLL circuit is used to extract the clock. However, if a discontinuous period such as a dropout occurs in the reproduced signal, not only will the signal within this period not be reproduced correctly, but even if correct data is input again.

A problem occurred in which data for a certain period of time (PLL pull-in time) would result in an error.

[Purpose of the invention]

An object of the present invention is to provide a PLL circuit that can generate continuous clocks with little two-phase fluctuation even when dropout occurs.

[Summary of the invention]

PLL circuits essentially allow sustained oscillation.

In other words, even if drip-out occurs, it is possible to generate continuous clocks with approximately the correct phase for a short period of time. However, if a signal with the wrong phase is input or the input signal stops for a long period of time, the oscillation frequency will change. To prevent this, measures have been taken such as detecting discontinuous periods of the input signal and fixing the output signal of the phase comparator. Figure 1 shows the configuration of a conventional Cronk regeneration circuit, where 1 is a data input terminal, 2 is a tank circuit, 3 is a phase comparator, 4 is a changeover switch, 5 is a low-frequency p-wave generator, and 6 is a phase comparator. is a voltage controlled oscillator (hereinafter referred to as 700 circuit).

7 is an envelope detection circuit, and 8 is a clock output terminal. The operation of this circuit will be briefly explained. An edge signal of a reproduced digital signal is input to an input terminal 1, and a clock signal is extracted by a tank circuit 2.

The amplitude of this output changes in proportion to the magnitude of the clock component in the digital signal. When a dropout occurs in the data, the envelope of the output signal of the tank circuit 2 drops rapidly, so this is detected by the envelope detection circuit 7, and the changeover switch 4 is operated based on this signal. That is, although the output of the phase comparator 3 is normally selected, the PLL circuit is prevented from operating abnormally by switching to a constant voltage Vo during the dropout period.

This conventional method has the following problems.

In other words, if the oscillation frequency fo when the changeover switch 4 is switched to the Vo side is different from the center frequency, a large phase error will occur, and the PLL after dropout
It also takes time to draw in the circuit. In other words, it was necessary to set the voltage Vo with high precision and to reduce noise and temperature changes. Furthermore, although there are commercially available products in which the entire PLL circuit is integrated into an IC, there is a drawback that it cannot be applied to these ICs.

The present invention attempts to realize stable PLL operation by switching to a signal substantially equal to the input signal, that is, the output signal of the PLL circuit to form a loop when dropout occurs.

[Embodiments of the invention]

An embodiment of the present invention will be explained below with reference to FIG. This circuit has almost the same structure as the PLL circuit shown in FIG. 1, except that a selector circuit 10 for selecting the output of the tank circuit 2 and the output of the 700 circuit 6 is added. This circuit is controlled by the output of the envelope detection circuit 7, and during the period when there is no dropout, the tank circuit 2
During the period when dropout occurs, the output of the 700 circuit 6 is selected and output. Next, the output 1 of this circuit
1 and the output 12 of the 700 circuit 6 are input to the phase comparator 3,
An error voltage 13 proportional to the phase difference is generated, smoothed by a low-frequency F wave generator 5, and then input to a 700 circuit 6. 70
0 circuit 6 receives a signal 12 with a frequency proportional to the input voltage 14.
is output to the output terminal 8, and at the same time, the selector circuit 10
and is also fed back to the phase comparator 3. The signal level used is T
In the case of TL, the selector circuit 10 may be a data selector of a TTL circuit (eg, SN74157).

It can also be realized by combining tri-state circuits.

FIG. 3 shows examples of signal waveforms at various parts of the circuit shown in FIG. 2.

The output waveform 9 of the tank circuit 2 is input to the envelope detection circuit 7, and only the period A below a certain amplitude produces a control signal 15 of 11j'. This signal controls the selector circuit 10 to switch between the input signal and the output of the 700 circuit 6. As a result, during the period A during which dropout occurs, the input signals of the 1-phase comparator 30 are exactly the same, and a signal with zero 1-phase error is output, but the output signal of the low-pass filter 5 is
The result is a smoothly connected waveform as shown in FIG.

As a result, a stable signal with little frequency fluctuation is obtained as the output signal of the 700 circuit 6, that is, the final output signal 12 of the PLL circuit.

〔Effect of the invention〕

According to the present invention, in a PLL circuit to which discontinuous signals due to dropouts etc. are input, continuous phase comparison is possible by switching the input signal during the dropout period to the output signal. A vCO output signal with less influence is obtained.

The circuit scale for realizing the present invention is very small, and since it can be realized entirely by logic circuits, it can be manufactured at low cost.

Further, although the case of a TTL signal has been described as a signal level, it goes without saying that a similar circuit can be used to realize a case of a CMO8 or ECL level.

[Brief explanation of drawings]

Fig. 1 is a block diagram of a conventional PLL circuit, and Fig. 2 is a block diagram of a conventional PLL circuit.
FIG. 3, a block diagram of a PLL circuit according to an embodiment of the present invention, is a signal waveform diagram of each part of FIG. 2. 2...Tank circuit, 3...Phase comparator, 5...Low frequency F wave device, 6...Voltage controlled oscillator, 7...Envelope detection -173=

Claims (1)

[Claims] In a phase-locked loop circuit that has a phase comparator that compares the phases of two types of signals, a low-pass filter, and a voltage controlled oscillator, there is a discontinuity detection circuit that detects discontinuous periods of the input signal, and input signal and voltage control. A phase-locked loop circuit comprising a switching circuit for switching an output signal of an oscillator and inputting the signal to the phase comparator, the switching circuit being controlled by the output of the discontinuity detection circuit.