JP2002190735A - Semiconductor integrated circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor integrated circuit for accurately and speedily synchronizing signals. SOLUTION: The semiconductor integrated circuit for detecting the phase shifting of a clock signal CK and a data signal Data is provided with delay circuits 1, 2 for generating plural judging reference period signals of different phases by shifting the phase of the supplied clock signal CK, phase judging circuits 3 and 4 for detecting the phase shifting between the clock signal CK and the data signal Data by comparing the mutual logical level of the respective judging reference period signals and the data signal Data, and a lock state judging circuit 5 for generating LK/ULK showing a phase state in accordance with the phase shifting detected by the circuits 3 and 4.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to a semiconductor integrated circuit, and more particularly to a semiconductor integrated circuit for realizing a method for synchronizing signal phases.

[0002]

2. Description of the Related Art In a conventional phase locked loop (PLL) circuit, a voltage controlled oscillator (VCO) is controlled to generate a clock signal CK having a phase difference of 0 with respect to a data signal Data. Here, generally, the phase of the data signal Data and the phase of the clock signal CK are compared by a phase comparator, and the phase difference signal output from the phase comparator as a result of the comparison is fed back to the VCO via a low-pass filter. .

Conventionally, in the process of adjusting the frequency of the clock signal CK to the frequency of the data signal Data or when the phase difference between the two signals becomes large, the time required for synchronization is reduced. PLL using a lock detection circuit and a loop gain switching circuit
A method of switching a time constant of a circuit may be adopted.

[0004] The PLL circuit is an NRZ (Non-Return).
A clock recovery circuit (Clock & Data Recovery-) that recovers a clock signal from a data signal of the “to Zero” method.
(CDR). Where N
The RZ data communication is a communication method in which the sign of data changes following only one of a timing at which a logic level of a clock signal changes from a low level to a high level and a timing at which a logic level changes from a high level to a low level. Yes, half of the clock frequency is the fundamental wave.

FIG. 1 shows a conventional lock detection circuit. As shown in FIG. 1, the data signal Data shown in FIG. 2A is generated by delaying the data signal Data shown in FIG.
Data and the clock signal Clock shown in FIG. 2B are supplied to the delay flip-flop 31. Then, if the data signal D-Data transitions during a period _TL (for example, between time T1 and time T2) in which the clock signal Clock is at a high level, the delay flip-flop 31 determines that the signal is locked.

[0006] In this case, in order to determine that it is locked,
To make the lock range symmetrical in phase advance and delay
Is a delay of the data signal Data as shown in FIG.
Total amount T _DJust clock signal Clock is at a high level
Period T_L(For example, between time T1 and time T2)
Set to half, that is, 1/4 cycle of clock signal Clock
Need to be Therefore, such conventional lock detection
The circuit requires high accuracy regarding the delay amount of the data signal Data.
Required. In addition, the lock range must be the clock signal Cl.
period T, which is a half cycle of ock_LFree to be limited to
Less degree.

Although the lock detection circuit can detect that the lock detection circuit has deviated from the lock state, when the lock detection circuit detects the non-lock state, it is determined whether the clock signal has a higher frequency than the data signal and thus has deviated from the lock state. Since the frequency of the clock signal is lower than the frequency of the data signal, it is not possible to determine whether the clock signal has deviated from the locked state. Therefore, it is necessary to separately provide a frequency counter or the like and compare the frequencies of the data signal and the clock signal.

Further, the provision of the above-described frequency counter not only increases the circuit scale but also requires a great deal of time to compare the frequencies of the data signal and the clock signal.
There is a problem that the PLL circuit cannot be quickly returned to the locked state.

[0009]

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problem, and it is an object of the present invention to provide a semiconductor integrated circuit which realizes a signal synchronization method for accurately and quickly synchronizing signals. With the goal.

[0010]

SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor integrated circuit for detecting a locked state or an unlocked state between a data signal and a clock signal, wherein the data signal and the clock signal are supplied, and the data signal or the clock signal is supplied. A first phase determination circuit that generates a first phase determination signal indicating whether a phase delay of the clock signal with respect to the data signal is within a first range by shifting at least one phase of the clock signal; A signal and a clock signal are supplied, and by shifting at least one phase of the data signal or the clock signal, a second phase determination signal indicating whether or not the phase advance of the clock signal with respect to the data signal is within a second range. A second phase determination circuit to generate;
A first phase determination signal and a second phase determination signal are supplied,
A lock state determination circuit that generates a lock state determination signal indicating a lock state or an unlock state between the data signal and the clock signal based on the first phase determination signal and the second phase determination signal. This is achieved by providing a semiconductor integrated circuit as described above.

According to such means, the phase relationship between the clock signal and the data signal can be determined by a simple configuration, more specifically, whether the clock signal is locked or unlocked with respect to the data signal. Can be accurately determined.

Here, the first phase determination signal and the second phase determination signal are supplied, and the phase delay of the clock signal with respect to the data signal in the first phase determination circuit is out of the first reference range. Based on the detected timing and the timing at which the second phase determination circuit detects that the phase advance of the clock signal with respect to the data signal has deviated from within the second reference range, the frequency of the data signal and the clock signal The semiconductor integrated circuit further includes a frequency determination circuit that generates a frequency determination signal indicating a magnitude relationship with the frequency.

The semiconductor integrated circuit compares the phase of the data signal with the phase of the clock signal and generates a comparison result signal according to the phase shift. And a selection circuit for selectively outputting a result signal or a frequency determination signal, wherein the phase comparison circuit includes a Bang-Ban
It can be a g-type phase comparison circuit.

Further, the first phase determination circuit or the second phase determination circuit may include a logic circuit having a test signal and at least one of a data signal and a clock signal as input signals.

[0015]

Embodiments of the present invention will be described below in detail with reference to the drawings. In the drawings, the same reference numerals indicate the same or corresponding parts. [First Embodiment] A semiconductor integrated circuit according to a first embodiment of the present invention is a circuit for detecting a synchronous state (lock state) or an asynchronous state (unlock state) between a data signal and a clock signal. The configuration is shown in FIG.

As shown in FIG. 3, the semiconductor integrated circuit according to the first embodiment includes delay circuits 1 and 2, phase determination circuits 3 and 4, and a lock state determination circuit 5. Here, the clock signal C is supplied to the phase determination circuit 3 and the delay circuit 2.
K is supplied, and the data signal Data is supplied to the phase determination circuit 4 and the delay circuit 1.

One input terminal of the phase determination circuit 3 is connected to the delay circuit 1, and one input terminal of the phase determination circuit 4 is connected to the delay circuit 2. The two input terminals of the lock state determination circuit 5 are connected to the phase determination circuits 3 and 4, respectively.

In general, the clock recovery circuit (CDR)
In the above, the voltage-controlled oscillator (VC
O) The timing of the data signal and the timing of the clock signal are re-aligned (also referred to as “retiming”) according to the clock signal output from O), so that the transition point of the data signal and the transition point at which the clock signal transitions from high level to low level Is defined as a locked state when the phase difference is within a certain range.

That is, as shown in FIG.
For the data signal Data shown in (a), for example, as shown in FIG. 4B, the transition point from the high level to the low level of the clock signal is from time T2 including the data change point to time T3. Is included in the range, the state is locked, and when the time is included between time T1 and time T2 and between time T3 and time T4, the state is unlocked.

Here, as means for detecting the locked or unlocked state as described above, the signal SA shown in FIG. 4C having the same frequency as the clock signal and having a different duty is used. When the signal Data transitions, a method may be considered in which if the signal SA is 1 (logical level is high), the locked state is determined, and if the signal SA is 0 (logical level is low), the locked state is determined. A circuit shown in FIG. 5 is also conceivable as a lock detection circuit for realizing such a method.

As shown in FIG. 5, the lock detecting circuit includes delay circuits 30, 32, a delay flip-flop 31, and a NAND circuit 33. The lock detection circuit having such a configuration is provided with a clock signal shown in FIG.
The clock is divided into two, and one is delayed by a time T _D1 by a delay circuit (inverting circuit) 32 as shown in FIG. 6C to generate a clock signal D-Clock. Then, by combining these two clock signals Clock and D-Clock with the NAND circuit 33, the signal _SN shown in FIG. 6D is generated, and the duty of the clock signal Clock is changed.

However, when the frequency of the data signal Data and the clock signal becomes high, the signal S including harmonics becomes high.
Since it becomes difficult to generate waveforms having different duties such as A and to adjust the phase relationship with the clock signal, a method is required that uses the waveform of the clock signal as it is.

Therefore, in the semiconductor integrated circuit according to the first embodiment, the phase shift is determined by shifting the clock signal CK shown in FIG. 4B by a different phase instead of the signal SA. Fig. 4 (d), which is the reference for
And the signals SB and SC shown in FIG. 4 (e) are generated, and these signals are compared with the changing points of the data signal Data, and the comparison result is synthesized to generate a lock state determination output signal. .

At this time, the signal SB is as shown in FIG. 4B for a time τ corresponding to a half of the phase section (from time T1 to time T2, or from time T3 to time T4) for determining unlocking. This is a signal obtained by delaying the indicated clock signal CK. The signal SC is a signal obtained by delaying the clock signal CK by a time corresponding to a half cycle of the clock signal CK and advancing the phase by a time τ corresponding to half of the phase section.

Here, it is particularly difficult to generate the signal SC shown in FIG. 4E by a method called delay. Therefore, in the semiconductor integrated circuit according to the first embodiment, the clock signal CK is inverted to generate the signal SC ′ shown in FIG. 4F, and the clock signal CK is delayed when the signal SB is generated. By delaying the data signal Data by the time to be performed, a phase relationship equivalent to the phase relationship between the clock signal CK and the signal SC is obtained.

As described above, by using a common delay circuit for generating the signal SB and a common delay circuit for generating the signal SC, a lock detection range (symmetrical) around the change point of the data signal Data can be used. The sum of those ranges is the time T
2 to time T3), and two identical circuits can be used as the phase determination means. Further, as a means for synthesizing the signals output from the two phase determining means, a circuit for obtaining a simple logical sum or logical AND is employed, and finally a signal for determining the locked or unlocked state is obtained. Can be

FIG. 7 is a circuit diagram showing a specific example of the semiconductor integrated circuit according to the first embodiment shown in FIG. As shown in FIG. 7, the phase determination circuits 3 and 4 can be configured by delay flip-flops (D-FF) 3a and 4a, respectively, and the lock state determination circuit 5
It can be constituted by the ND circuit 5a.

The semiconductor integrated circuit shown in FIG.
It can be equivalently configured as the semiconductor integrated circuit shown in FIG. That is, the semiconductor integrated circuit shown in FIG. 8 further includes a buffer 7 to which a clock signal CK is supplied and a buffer 8 to which a data signal Data is supplied, as compared with the semiconductor integrated circuit shown in FIG. , NAND circuit 5
An OR circuit 6 is provided instead of a.

As a result, according to the semiconductor integrated circuit shown in FIG.
By inverting K and the data signal Data, it is possible to easily generate a signal for determining the locked or unlocked state.

The operation of the semiconductor integrated circuit shown in FIG. 8 will be described below with reference to a timing chart shown in FIG. First, the clock signal CK shown in FIG. 9A is supplied to the buffer 7, and the data signal Data shown in FIG. 9B is supplied to the buffer 8.

The buffer 7 receives the clock signal CK.
Is inverted, and the inverted clock signal / shown in FIG.
CK (signal) is generated and supplied to the delay flip-flop 3a. The buffer 7 has an inverted clock signal / CK
(Signal) to the delay circuit 2. This delay circuit 2 inverts the supplied signal and delays it by a predetermined time,
The clock signal CK ′ (signal) shown in FIG. 9F is supplied to the delay flip-flop 4a.

On the other hand, the buffer 8 inverts the data signal Data and outputs the inverted data signal / Data shown in FIG.
(Signal) is generated and supplied to the delay flip-flop 4a. The buffer 8 supplies the inverted data signal / Data (signal) to the delay circuit 1. The delay circuit 1 inverts the supplied signal and delays the signal by a predetermined time.
The data signal Data '(signal) shown in (d) is supplied to the delay flip-flop 3a.

Here, as shown in FIG. 9D, when the data signal Data 'makes a transition from the low level (L) to the high level (H) at the time T3, the level of the inverted clock signal / CK at the time T3 changes. In response to the low level, the signal shown in FIG. 9E changes from the high level to the low level and is latched. FIG. 9D
When the data signal Data 'transits from low level (L) to high level (H) at time T5, as shown in FIG. 7, the level of the inverted clock signal / CK at time T5 is high. The signal shown in FIG. 9E transitions from a low level to a high level and is latched.

Here, at time T when the signal is at the low level,
3 to the time T5, the signal S shown in FIG.
When C is used as a criterion, it means that the clock signal CK is in an unlocked state.

Similarly, as shown in FIG. 9 (g), when the inverted data signal / Data transitions from low level (L) to high level (H) at time T4, the level of the clock signal CK 'at time T4 changes. In response to the low level, the signal shown in FIG. 9H transitions from the high level to the low level and is latched. FIG.
As shown in (g), when the inverted data signal / Data transitions from low level (L) to high level (H) at time T6, the clock signal C at time T6
According to the fact that the level of K ′ is high, FIG.
The signal shown in (h) transitions from low level to high level and is latched.

Here, at the time T when the signal is at the low level,
4 to time T6, the signal S shown in FIG.
When B is used as a criterion, it means that the clock signal CK is in an unlocked state.

The OR circuit 6 shown in FIG. 8 takes the logical sum of the signal shown in FIG. 9E and the signal shown in FIG. The signal LK / UL shown in FIG.
Generate and output K (signal).

As described above, while the signal LK / ULK is at a high level, the clock signal CK is in a locked state with respect to the data signal Data, and when the signal LK / ULK is at a low level, it is in an unlocked state.

The signal SB shown in FIG. 4D corresponds to the clock signal CK '(signal) shown in FIG. 9F, and the signal SC' shown in FIG. This corresponds to the inverted clock signal / CK (signal) shown in FIG.

As described above, according to the semiconductor integrated circuit according to the first embodiment of the present invention, the phase relationship between clock signal CK and data signal Data, more specifically, clock signal CK is applied to data signal Data with a simple configuration. , It can be accurately determined whether it is locked or unlocked. [Second Embodiment] FIG. 10 is a diagram showing a configuration of a semiconductor integrated circuit according to a second embodiment of the present invention. Here, in the semiconductor integrated circuit according to the second embodiment, similarly to the semiconductor integrated circuit according to the first embodiment, clock signal CK is locked or unlocked with respect to data signal Data. And further, the clock signal C
It has a function of determining whether the frequency of K is higher or lower than the frequency of the data signal Data.

As shown in FIG. 10, the present embodiment 2
Has a configuration similar to that of the semiconductor integrated circuit shown in FIG. 3, but is different in that the semiconductor integrated circuit further includes a frequency high / low determination circuit 9 connected to the phase determination circuits 3 and 4.

The frequency level judging circuit 9 can be constituted by a set / reset flip-flop 10 connected to the delay flip-flops 3a and 4a, as shown in FIG.

Next, the operation of the semiconductor integrated circuit according to the second embodiment will be described with reference to a timing chart shown in FIG. FIG. 12 shows a case where the frequency of the clock signal CK is lower than that of the data signal Data.

The semiconductor integrated circuit according to the second embodiment,
The operation is the same as that of the semiconductor integrated circuit according to the first embodiment, except that the set / reset flip-flop 10 generates the signal SQ (signal) shown in FIG.
Is output.

As shown in FIGS. 12A and 12B, the phase of the clock signal CK lags behind the phase of the data signal Data with the passage of time.
As shown in (e), first, at time T3, the signal output from the delay flip-flop 3a transitions from a high level to a low level. At time T6, the signal output from delay flip-flop 4a also transitions from high level to low level, and OR circuit 6 outputs a low-level signal (signal) indicating an unlocked state.

Further, at time T7, the phase of the clock signal CK approaches the phase of the data signal Data again.
The signal output from the delay flip-flop 3a goes high. Then, at time T8, the signal output from the delay flip-flop 4a also transitions from low to high and returns to the initial state.

Here, as shown in FIG.
In the set / reset flip-flop 10, a time T4 when a high-level (logical value 1) signal is input to the S terminal and a low-level (logical value 0) signal is input to the R terminal.
From the time T6 to the time T6.
From time T6 when a low-level (logical value 0) signal is input to the terminal and the R terminal, the level of the signal SQ is held at a high level from time T7. Then, a low-level signal SQ is output from time T7 to time T8 when a low-level signal is input to the S terminal and a high-level signal is input to the R terminal.

When the frequency of the clock signal CK is higher than the frequency of the data signal Data, the output of the delay flip-flop 4a changes before the output of the delay flip-flop 3a.

Therefore, the delay flip-flops 3a, 4a
The logic level of the signal SQ output from the set / reset flip-flop 10 is determined by which of the two outputs the unlocked (low level) output signal first. Whether the frequency of CK is higher or lower than the frequency of the data signal Data can be easily determined.

Further, according to the semiconductor integrated circuit according to the second embodiment of the present invention, the two phase determination circuits 3 and 4 must be both earlier than the lock state determination result obtained by transitioning the output signal. Therefore, a delay circuit for gating the signal H / L output from the frequency high / low determination circuit 9 by the unlock signal ULK output from the lock state determination circuit 5 becomes unnecessary. Since a large margin can be obtained, the semiconductor integrated circuit can be simplified and highly reliable operation can be realized. [Third Embodiment] FIG. 13 shows a structure of a semiconductor integrated circuit according to a third embodiment of the present invention. Here, in the semiconductor integrated circuit according to the third embodiment, similarly to the semiconductor integrated circuit according to the second embodiment, the clock signal CK is locked or unlocked with respect to the data signal Data. Has a function of determining whether the frequency of the clock signal CK is higher or lower than the frequency of the data signal Data. It has a function of quickly returning to the locked state based on the above determination.

As shown in FIG. 13, the third embodiment
Is a lock detection circuit 13 composed of the semiconductor integrated circuit shown in FIG. 10 and a clock signal CK.
And a data signal Data, and a selector circuit 12.

Here, the phase comparison circuit 11 compares the phases of the clock signal CK and the data signal Data and outputs a signal indicating the phase difference. The selector circuit 12 is connected to the phase comparison circuit 11, the frequency high / low determination circuit 9 and the lock state determination circuit 5, and is output from the phase comparison circuit 11 in accordance with the signal LK / ULK supplied from the lock state determination circuit 5. Signal or the signal output from the frequency high / low determination circuit 9 is selectively output as the phase frequency comparison signal CS.

The operation of the semiconductor integrated circuit according to the third embodiment will be described below with reference to the timing chart shown in FIG. The semiconductor integrated circuit according to the third embodiment operates in the same manner as the semiconductor integrated circuit according to the second embodiment. However, the phase of the clock signal CK and the data signal Data is compared by the phase comparison circuit 11, and the comparison is performed. As a result, the signal shown in FIG.

On the other hand, in the example shown in FIG. 14, the frequency of the clock signal CK shown in FIG.
Since the frequency of the data signal Data shown in FIG. 4B is higher than that of the data signal Data, the signal SQ indicating the relationship between the frequencies is supplied from the frequency level judgment circuit 9 to the selector circuit 12.

Here, as shown in FIGS. 14 (g) and 14 (j), the selector circuit 12 performs the phase comparison in the locked state where the signal supplied from the locked state determining circuit 5 is at the high level. The signal output from the circuit 11 is selectively output as the phase frequency comparison signal CS, and in the unlock state where the signal supplied from the lock state determination circuit 5 is at a low level, the frequency level determination circuit 9
Are selectively output as the phase frequency comparison signal CS. Therefore, FIG.
In the hatched portion from time T2 to time T4 shown in FIG.
Q is output from the selector circuit 12.

Here, in a general PLL circuit, the output signal of the phase comparison circuit 11 is fed back to a voltage controlled oscillator (VCO) through a low-pass filter. And
In this case, the waveform of the output signal (signal) becomes a sawtooth wave as shown in FIG. 15 when the abscissa indicates the phase advance of the clock signal CK with respect to the data signal Data, and the average value is the average value of the sawtooth. Solid line AL passing through a point (vertical scale 0.5)
Indicated by 1.

On the other hand, the phase frequency comparison signal CS output from the selector circuit 12 according to the third embodiment is the signal SQ output from the frequency level judgment circuit 9 in the unlocked state as described above. As shown in FIG. 15, a high-level signal having the size of the vertical scale 1 is obtained from time T0 to time T2 to time T4.

From this, it can be seen that the average value of the phase frequency comparison signal CS is higher than the average value of the signal composed of the sawtooth wave output from the phase comparison circuit 11 because it is indicated by the broken line AL2 in FIG.

Accordingly, since the average value of the phase frequency comparison signal CS supplied to the voltage controlled oscillator increases, the frequency of the clock signal CK is higher than the frequency of the data signal Data. The frequency of CK will be reduced more effectively.

As described above, according to the semiconductor integrated circuit according to the third embodiment of the present invention, clock signal CK generated by a voltage controlled oscillator (VCO) can be made a signal having a desired frequency faster. . [Fourth Embodiment] FIG. 16 is a circuit diagram showing a configuration of a semiconductor integrated circuit according to a fourth embodiment of the present invention. As shown in FIG. 16, the semiconductor integrated circuit according to the fourth embodiment has a configuration similar to that of the semiconductor integrated circuit according to the third embodiment shown in FIG.
(Bang-Bang Type Phase Detector) Phase Comparison Circuit 15
, Selector circuits 16 and 17 and an operational amplifier 18.

The lock detection circuit 14 has a configuration similar to that of the semiconductor integrated circuit shown in FIG. 11, and includes delay circuits 1 and 2, delay flip-flops 3b and 4b, an OR circuit 6, a set And a reset flip-flop 19.

Here, the clock signal CK and the data signal Data are supplied to the BBD phase comparator 15, and the output Up from the BBD phase comparator 15 is supplied to the selector 16.
And the output Q (signal CKL) from the set / reset flip-flop 19 is supplied. The selector circuit 17 has an output Dn from the BBD phase comparison circuit 15 and an output / Q from the set / reset flip-flop 19.
(Signal CKH). Further, the operational amplifier 18 is connected to the two selector circuits 16 and 17.

The fourth embodiment having the above configuration
Operates in the same manner as the semiconductor integrated circuit according to the third embodiment, except that the BBD phase comparison circuit 1
5 corresponds to the output Up shown in FIG. 17 (l) and the output Up shown in FIG.
7 (m) are output.

On the other hand, the set / reset flip-flop 19 shown in FIG. 16 operates according to the magnitude relationship between the frequency of the clock signal CK and the frequency of the data signal Data.
A signal CKL shown in FIG. 17J and a signal CKH shown in FIG. As a result, as shown in FIG. 17 (n), the selector circuit 16 responds to the signal shown in FIG. 17 (i) supplied from the OR circuit 6 until time T5, which is the locked state, and after time T6. The output Up is output as a signal S1, and the time T5 when the unlock state is established
The signal CKL is output as the signal S1 in the hatched portion from to the time T6.

Similarly, as shown in FIG. 17 (o), the selector circuit 17 responds to the signal supplied from the OR circuit 6 until the locked time T5 and the time T5.
6 and thereafter, the output Dn is output as the signal S2, and the signal CKH is output as the signal S2 in the unlocked state from the time T5 to the time T6.

As a result, the operational amplifier 18 subtracts the signal S2 from the supplied signal S1, and outputs a signal S3 shown in FIG. 17 (p).

As shown in FIG. 18, the output Up and the output Dn from the BBD phase comparator 15 have waveforms shown by solid lines, but the selector circuits 16 and 17 according to the fourth embodiment are unlocked. Set in the state
The signal output from the reset flip-flop 19 is output.

As a result, the average value of the signal can be changed from the level of the solid line AL1 to the level of the dashed line AL2 as in the semiconductor integrated circuit according to the third embodiment, and as a result, the voltage controlled oscillator (VCO) The generated clock signal CK can be a signal having a desired frequency faster.

As described above, according to the semiconductor integrated circuit according to the fourth embodiment of the present invention, the same effects as those of the semiconductor integrated circuit according to the third embodiment can be obtained, and a two-output phase frequency comparison circuit is formed. When the clock signal CK is in an unlocked state with respect to the data signal Data, a signal indicating no signal or an error state can be generated, so that versatility can be further improved. [Fifth Embodiment] FIG. 19 shows a structure of a semiconductor integrated circuit according to a fifth embodiment of the present invention. As shown in FIG. 19, the semiconductor integrated circuit according to the fifth embodiment includes:
Although it has the same configuration as the lock detection circuit 14 included in the semiconductor integrated circuit according to the fourth embodiment shown in FIG.
OR circuit 2 to which test signal Test is supplied to one of the input terminals
The difference is that 0 is provided in place of the delay circuit 2.

The semiconductor integrated circuit according to the fifth embodiment having such a configuration easily implements a logic test of delay flip-flops 3a and 4a as a phase determination circuit.

That is, when testing the delay flip-flop 3a, the test signal Test is fixed to 1 to inactivate the OR circuit 20. Then, by lowering the frequency of the clock signal CK, a logic test of the delay flip-flop 3a at a low frequency can be easily performed.

Similarly, when testing the delay flip-flop 4a, the clock signal CK is set to 0V.
, And the test signal Test is arbitrarily switched, whereby a logic test of the delay flip-flop 4a at a low frequency can be easily performed.

As described above, according to the semiconductor integrated circuit of the fifth embodiment of the present invention, two or more input circuits such as an OR circuit, an AND circuit, and a NOR circuit are used as a circuit for delaying a signal supplied from the outside. By using a logic circuit having an end, a signal to be delayed (for example, a clock signal CK) can be changed independently of another signal (for example, a data signal Data). Any test can be easily performed.

In the semiconductor integrated circuit according to the fifth embodiment shown in FIG. 19, normal operation can be performed without any trouble by fixing test signal Test to a low level.

As described above, according to the semiconductor integrated circuit of the present invention, the phase relationship between the clock signal and the data signal can be reduced by a simple structure, and more specifically, the clock signal can be locked to the data signal. Whether it is in the unlocked state or not can be accurately determined.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing a configuration of a conventional lock detection circuit.

FIG. 2 is a timing chart showing an operation of the lock detection circuit shown in FIG.

FIG. 3 is a diagram illustrating a configuration of a semiconductor integrated circuit according to the first embodiment of the present invention;

FIG. 4 is a diagram illustrating the operation of the semiconductor integrated circuit shown in FIG.

FIG. 5 is a circuit diagram showing a configuration of another lock detection circuit in the related art.

FIG. 6 is a timing chart showing an operation of the lock detection circuit shown in FIG.

FIG. 7 is a circuit diagram showing a first specific example of the semiconductor integrated circuit shown in FIG. 3;

8 is a circuit diagram showing a second specific example of the semiconductor integrated circuit shown in FIG.

FIG. 9 is a timing chart illustrating an operation of the semiconductor integrated circuit illustrated in FIGS. 7 and 8;

FIG. 10 is a diagram showing a configuration of a semiconductor integrated circuit according to a second embodiment of the present invention.

11 is a circuit diagram showing a specific example of the semiconductor integrated circuit shown in FIG.

FIG. 12 is a timing chart illustrating an operation of the semiconductor integrated circuit shown in FIG. 11;

FIG. 13 is a diagram showing a configuration of a semiconductor integrated circuit according to a third embodiment of the present invention.

FIG. 14 is a timing chart showing an operation of the semiconductor integrated circuit shown in FIG.

15 is a waveform chart illustrating an operation of the semiconductor integrated circuit shown in FIG.

FIG. 16 is a diagram showing a configuration of a semiconductor integrated circuit according to a fourth embodiment of the present invention.

FIG. 17 is a timing chart showing an operation of the semiconductor integrated circuit shown in FIG.

18 is a waveform chart illustrating an operation of the semiconductor integrated circuit shown in FIG.

19 is a diagram showing a configuration of a semiconductor integrated circuit according to the fifth embodiment of the present invention.

[Explanation of symbols]

1, 2, 30, 32 delay circuit 3, 4 phase determination circuit 3a, 3b, 4a, 4b, 31 delay flip-flop (D-FF) 5 lock state determination circuit 5a, 33 NAND circuit 6, 20 OR circuit 7, 8 Buffer 9 Frequency high / low judgment circuit 10, 19 Set / reset flip-flop (RS
−FF) 11 Phase comparison circuit 12, 16, 17 Selector circuit 13, 14 Lock detection circuit 15 BBD phase comparison circuit 18 Operational amplifier

Claims (5)

[Claims] 1. A semiconductor integrated circuit for detecting a locked state or an unlocked state between a data signal and a clock signal, wherein the data signal and the clock signal are supplied, and at least one of the data signal or the clock signal is provided. A first phase determination circuit that generates a first phase determination signal indicating whether the phase delay of the clock signal with respect to the data signal is within a first range, and the data signal and A second phase indicating whether the phase advance of the clock signal with respect to the data signal is within a second range by shifting the phase of at least one of the data signal or the clock signal, wherein the clock signal is provided. A second phase determination circuit that generates a determination signal, the first phase determination signal and the second phase determination signal Is supplied and generates a lock state determination signal indicating the lock state or the unlock state between the data signal and the clock signal based on the first phase determination signal and the second phase determination signal. A semiconductor integrated circuit, comprising: a state determination circuit. 2. The apparatus according to claim 1, wherein the first phase determination signal and the second phase determination signal are supplied, and a phase delay of the clock signal with respect to the data signal in the first phase determination circuit falls within the first reference range. And a timing at which the second phase determination circuit detects that the phase advance of the clock signal with respect to the data signal has deviated from within the second reference range. 2. The semiconductor integrated circuit according to claim 1, further comprising a frequency determination circuit that generates a frequency determination signal indicating a magnitude relationship between the frequency of the data signal and the frequency of the clock signal. 3. A phase comparison circuit that compares a phase of the data signal with a phase of the clock signal to generate a comparison result signal according to a phase shift, and the comparison result signal according to the lock state determination signal. 3. The semiconductor integrated circuit according to claim 2, further comprising: a selection circuit that selectively outputs the frequency determination signal. 4. The method according to claim 1, wherein the phase comparison circuit comprises a Bang-Ban
4. The semiconductor integrated circuit according to claim 3, which is a g-type phase comparison circuit. 5. The circuit according to claim 1, wherein the first phase determination circuit or the second phase determination circuit includes a logic circuit that receives a test signal and at least one of the data signal or the clock signal as an input signal. 5. The semiconductor integrated circuit according to any one of 4.