JPS61269084A - Logical circuit with data scan circuit - Google Patents

Abstract

PURPOSE:To relieve a design restriction and increase an operational speed by supplying scan data produced from a plurality of selector circuits to a scan data output terminal commonly provided to a plurality of combinational circuits. CONSTITUTION:For first latches 211A-213A for supplying or receiving data to or from combinational circuits 100-120, are provided second latches 211B-213B and selectors 3-1-3-3, the latter for selecting the output of the first and second latches in first and second modes, respectively. In an inspection operation, the output of the first latches is transferred to the second latches and the selectors are operated in the second mode. Thus, the logical restrictions of a common-mode transfer and a clutch loop can be removed and an operational speed can be increased.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Application of the Invention] The present invention relates to a logic circuit having a data scan circuit for facilitating diagnosis of the logic circuit.

[Background of the invention]

To improve the testability of large-scale logic circuits, a method is used that adds scan paths to existing circuits and divides multiple large-scale sequential circuits into small combinational circuits surrounded by latches. This will be explained below using an example.

FIG. 1 shows an example of a sequential circuit to be diagnosed. A sequential circuit can be divided into a plurality of partial circuits (combinational circuits) that do not include latches and a plurality of latches. 1st
In the figure, 100, 110.degree. 120 indicates such a combinational circuit, and latches 201-203 illustrate such latches.

710, 720, and 730 are system input terminals that receive input data to the sequential circuit 1. 740 is sequential circuit 1
This is a system output terminal that sends output data from the . Latches 201 to 203 are connected to system clock C1 (i=1
．． The values of system data D, (i=1.2 or 3) that are input to each of them when D, (i=1.2 or 3) are on are taken in and held. The combinational circuits 100, 110, 120 transmit system data expanded to system data inputted from system input terminals 720, 730 or latches 201, 202, 203, respectively, to latches 202, 203 or 203 connected to their respective output terminals. , is output to the system output terminal 740. In this embodiment, the combinational circuit (1) 100 receives data D from terminals 720 and 730. ,D
o′ is input and the combinational circuit (2) 110 becomes the latch 20.
1 output data D1 is input. Combinational circuit (3) 1
20 is the output data D2e D of the latches 202 and 203
! is input. In such a sequential circuit 1, the logical operation result D1 of each combinational circuit is stored in a latch on the output side of the combinational circuit in response to a clock, and is transmitted to the combinational circuit in the subsequent stage, whereby the system input terminal 7
A predetermined output signal corresponding to the input signal provided at 10,720° 730 can be obtained at system output terminal 740. Even if there is a feedback loop in the sequential circuit, the sequential circuit 1 operates in exactly the same way.
As the number of logic gates on the path from 0.730 to system output terminal 7408 increases, it becomes increasingly difficult to detect failures in the circuit.

A widely used method to solve this problem is the scan path method.6 In this method, access paths are added to all latches in the circuit to facilitate control and observation of the latches. . This allows each latch in the circuit to be handled as if it were a system input terminal or system output terminal, making it possible to divide one entire circuit into a plurality of combinational circuits, which greatly facilitates diagnosis. As a typical example of the scan path addition method, see Reference 1 (“A
Logic Design 5structure f
or LSI Testing”tDA Conference
ence, 1977, pp. 462-468) and the system scan method presented in Reference 2 ("Testin
g VLSI with Rando+n Accesses
s5can”.

The random scan method shown in C0NPCON, 1980, 50-52 p.

An example of the circuit configuration of the system scan method is shown in Figure 2.
All latches 201-203 in FIG. 1 are replaced with latches 211-213 with scanning functions. Latches 211, 212, and 213 with scan function are L1 latches 211A, respectively.

212A or 213A and L2 latch 211B.

212B or 213B. L1 latch 21
1A, 212A, or 213A is the system data D□ when the system clock C+ (i=1.2 or 3) is in the on state, similar to the conventional latch.

In addition to being captured and held in D21 or D3, when shift clock A is on, the inputs 270-1. L2 latch 211B
Output 270-2. Output 270- of L2 latch 212B
A person will be able to take in and retain 3. L2 latch 21
1B, 212B, or 213B is a latch provided for stabilizing the shift operation, which will be explained below.
When clock B is on, L1 latch 211A, 2
Capture and hold the output of 12A or 213A. Therefore all L1 latches 211A.

212A, 213A and L2 latch 211B, 212B
, 213B is the scan in pin SI to scan in pin SI.
Connected as a system string to out pin So. During diagnostic operation, by alternately sending shift clocks A and B, scan-in pin SI
It is possible to easily set any value to the latches 211, 212, 213 from latches 211, 212, 213.
The contents can be easily observed with the scan out pin So. By constantly turning off shift clocks A and B during normal operation, it is possible to create a moving object exactly the same as the circuit shown in FIG. 1. In other words, L1
Latches 211A, 212A.

213A is the conventional latch 201, 202° 20 of FIG.
3, L2 latches 211B and 212B.

213B becomes transparent6 An example of the circuit configuration of the random scan method is shown in FIG.

Unique addresses are assigned to all latches, and the latches with scan functions 221 to 223 replace the latches with six scan functions.Similar to the first conventional latches 201 to 203, the latches with the scan function are connected to the system clock ct (
It not only captures and holds system data c, (i=1 to 3) when i=1+2 or 3) is in the on state;
Each latch is selected and scan clock A
is in the on state, the value of scan in pin SI is 2.
80 can be captured and retained. Additionally, when each latch 221-223 is selected, its contents can be observed at scan out pin SO. Address pins AE) and address decoders 300 are added for selection of latches 221-223.

A selection signal 302-i (i=1 to 3) generated by decoding the address in the decoder 300 is distributed to the corresponding latch 221, 222 or 223, respectively. This selection signal 302-i for each latch 221 to 223
is ANDed with scan clock A to become a diagnostic clock signal, and each latch 221, 222 or 22
It is ANDed with the output signal of No. 3 and becomes a scan out signal. The scan out signals of all latches 221-223 are ORed at gate 330 and observed at scan out pin So. Latches to pay attention to during diagnostic operation 2
The decoder 30 decodes the address AD of 21, 222 or 223.
By inputting 0 and sending the scan clock A, any value can be set from the scan in pin to the latch 221, 222 or 223 of interest. Furthermore, by inputting the address AD of the latch of interest without sending out the clock A, the contents of the latch can be observed at the scan out pin SO.

By constantly turning off the scan clock A during normal operation, it is possible to operate exactly the same as the circuit shown in FIG. 1.

In a circuit having a scan path as shown in FIGS. 2 and 3, each divided combinational circuit can be tested by the following procedure.

(1) Scan the test pattern into the input side latch of the combinational circuit.

(2) Send the system clock to the output side latch and take in the system data. This is called clock advance.

(3) Scan out the captured data from the output side latch and
Compare with the expected value of 6°.

The above process is repeated for all test buttons and all combinational circuits. This type of inspection method is reliable
j (1 usually several to ensure it works)
``Logical design constraints are imposed. One of them is the prohibition of in-phase transfer. In other words, it is prohibited that the system clocks of the input side latch and the output side latch are in the same phase.For example, in Fig. 2, LL The clock C□ of the latch 211A and the clock C3 of the L1 latch 213A must not be in phase.
The clock C of latch 223 and the clock C3 of latch 223 must not be in phase. This is because the value of the input latch that has been scanned in in advance during clock advance may change, and there is a risk that this changed value will be incorporated into the output latch, so stable operation cannot be guaranteed. It is. This is the system used during inspection.
This is due to the fact that the pulse width of the clock is longer than the pulse width of the system clock during actual operation, and exceeds the minimum delay time of a signal in the combinational circuit narrowed by the in-phase latch. In other words, when the width of the system clock is short, even if the signal is an in-phase latch due to this minimum delay time, the system clock is lost by the time the signal reaches the output latch from the input latch. does not affect the signal. On the other hand, when the width of the system clock is long, even if the signal reaches from the input latch to the output latch, the system clock is not lost, so the previous signal is lost. The case where the output of a latch becomes its own input without going through another latch (one latch loop) is also prohibited for the same reason as in-phase transfer.

One of the commonly used methods to resolve such logical design constraints is, for example, Nikkei Electronics (1979, 4, 16 p., 57-79). The latch 211 in FIG.
There is a method in which 213 is configured as a mask slave and the slave latch is controlled by a clock provided for diagnosis. An example of this is shown in FIG. That is, the output of the master latch (LL clutches 211A, 212A, 213A) is not the slave latch (L2 latch) 211B.

The outputs 270-2 to 270-4 of 212B and 213B are used as system data D. Therefore, in order to capture the system data D3 output from the previous stage combinational circuit, for example 110, and transmit it to the next stage combinational circuit 120, the system clock C2 is sent out and the data D3 is fetched to the L1 latch 213A. After the shift clock is input, it is necessary to send out the shift clock B to transfer the data D3 from the L□ clutch 13A to the L2 latch 213B.
Clock B is used in both normal and diagnostic modes. In the case of such a circuit configuration, even if the system clocks C1 and C3 of the latches 211 and 213 are in phase, the above-mentioned diagnostic problem does not occur. Because,
At this time, when the system clock C3 is sent out, the system clock c1 is also sent out at the same time, and the L1 latch 2 on the input side
Although the output of L2 latch 211B may change depending on the value of system input terminal 710, since shift clock B is in the off state, the output of L2 latch 211B does not change, so the output of combinational circuit (2) 110 does not change. This is because the output D3 is not output. However, in such a mask-slave configuration device, data transfer is performed using two clocks, Ci and B, during normal operation, resulting in an increase in system delay during normal operation and delay in logic circuit operation. The disadvantage is that it reduces speed. For example, in the signal path from the system data input pin of latch 211 to the system data input pin of latch 213, latch 2
11 is the delay of the L2 latch 211B, and the relative path delay increases in the case of FIG.

In other words, there is a trade-off between easing design constraints and improving operating speed, and it is difficult to satisfy both with conventional scan circuit configurations.

[Purpose of the invention]

SUMMARY OF THE INVENTION An object of the present invention is to provide a logic circuit with a diagnostic function and a method for diagnosing the logic circuit, which satisfies both the relaxation of diagnostic design constraints and the improvement of operating speed, in order to overcome the above-mentioned drawbacks.

, □, 4; □For each first latch that supplies data to or receives data from a combinational circuit forming a logic circuit, a second latch and, in the first mode, a first latch; A selector is provided for selecting the output of the latch in the second mode.

During normal operation, the output of the first latch is supplied to the next-stage combinational circuit by operating the selector in the first mode without transferring the output of the first latch to the second latch. . This eliminates the delay in the second latch that occurs in the prior art in which data is transferred from the first latch to the second latch. Although the delay of the selector cannot be avoided, the delay of the selector can generally be made smaller than the delay of the second latch.

During the test operation, the output of the first latch is transferred to the second latch, and the selector is operated in the second mode. As a result, stable operation can be guaranteed even in a circuit including in-phase transfer and one latch loop.

[Embodiments of the invention]

An embodiment of the present invention will be described below with reference to the drawings.

FIG. 5 is an example in which the present invention is applied to the shift-scan type circuit shown in FIG. 2 or FIG. 4. In FIG. 5, the same reference numbers as in FIG. 2 or 4 refer to the same thing. What is new is that selectors 3-1 to 3-3 are added to the latches 211 to 213 in FIG. 2 or 4. The newly added selectors 3-1 to 3-3 receive the mode control signal M
1 or M2 is '1' or 10', L1 latch 2,
IIA, 212A, 213A output or L2 latch 211
The outputs of B, 212B, and 213B are selected and output, respectively.

FIG. 6 shows the configuration of this selector 3-i (i=1 to 3) in a 6M08 circuit. 41 is an inverter made of a 6M08 circuit, and 42 and 43 are tristate elements made of a 6M08 circuit.

The mode control signal M1 or M2 given to the terminal 23 is '
If it is 1', it is connected to terminal 21 and output 21 of 1 latch
is selected, and conversely, mode control signal M12 or M2 is '0'.
If so, the output of the L2 latch connected to terminal 22 is selected and output from output terminal 24.

In a CMOS circuit, 6 to 8 transistors are required to configure a slave latch, but the selector can be made with two transistors, and the path delay from the input terminal 21 to the output terminal 24 can be changed to the slave latch. It can be smaller than the path delay through the latch.

Next, the operation of the circuit having such a configuration will be explained separately during normal operation and diagnostic operation using time charts.

FIG. 7 is a time chart showing the normal operation of the circuit shown in FIG. Mode control signals M1 and M2 are constantly set to 11'. Therefore, L1 latch 211A is selected by selector 3-i.

Since the outputs of 212A and 213A are selected, the following operation is the same as the normal operation of the circuit shown in FIG.

Further, shift clock signals A and B are constantly set to '0'. In FIG. 5, the system clocks Ct, C
2. Since there is no problem even if C3 is in the same phase as described later, it is assumed that the clocks C3 are the same clock C.

At time 810, the system input signal 710°720
．． 730 has changed. The system output cuff 40 corresponding to this is the system clock C (= Cx =
By sending C2=C3) twice at times 830 and 870, it is obtained at time 890. In other words, after the system input cuff 10, 720°730 changes at 810, first the combinational circuit 1°"""""8°'°"6"°1
°? & 4: M′″830 (,:.

The first clock C is transmitted at
1. Immediately after that, L1 latch 211A
~213A output changes. L1 latch 212A and 2
The output D4 of the combinational circuit 3 changes at time 840 due to the change in the output of 13A. As a result, the system output from output terminal 740 also changes at time 850. L1 latch 211
Due to the change in the output of A, the output of combinational circuit 2 changes to time 860.
However, this effect is captured by the L1 latch 213A after the second clock C transmission time 870, causing the output D4 of the combinational circuit 3 to change at time 880, and the final system response to be output at the terminal at time 890. 740. Since the width of the system clock C applied during normal operation is sufficiently short compared to the minimum delay time between L1 latches 211A and 213A, data leakage does not occur even if the clocks of latches 211A and 213A are in phase. do not have.

In other words, when the clock is sent out at time 830, the L1 latch 21
The output of 1 is not taken into the L1 latch 213A as is. However, since the clock width that can be supplied from the tester used during the diagnostic operation is long, data skipping occurs in the case of the same phase, causing the above-mentioned diagnostic problem. However, as described below, the present invention can ensure stable operation even during diagnostic operation.

FIG. 8 is a time chart showing the operation of the combinational circuit (2) 110 in FIG. 5 during diagnosis.

The mode control signals M1 and M2 are constantly set to '1', and the selector 3-i is the L2 latch 211B, 202B.

213B output is selected. In other words, all latches 211
．． 212 and 213 have a mask slave configuration. Therefore, the following operation is the same as the operation when diagnosing the circuit shown in FIG. 910,915°930 is the scan in time, 955 is the clock advance time, 970
indicates the scan out time. Time 910,9
20°935. The data flow to 950, 965, 980, 985 shows the signal flow from the scan-in pin SI until the response to the applied signal is observed at the scan-out pin SO. . In other words, the input data given to the scan-in pin S at time 910 is taken into the L1 latch (master latch) 211A of the latch 211 at time 920 after the shift clock A is sent out at time 915. Next, when shift clock B is sent out at time 930, it is taken into L2 latch (slave latch) 211B of latch 211 at time 935. At this point, the input data setting (scan-in) for one combinational circuit 2 is completed.

At time 950 after a certain period of time, the output of the combinational circuit 2 in response to this input data is determined. Thereafter, at time 955, system clock C is sent out. Due to this.

At time 965, this data D3 is taken into the L1 latch (mask latch) 213A of the latch 213. Next, by sending shift clock B at time 970, the L of latch 213 is set at time 980.
This data D is placed in the 2 latch (slave latch) 213B.
3 is captured, which is scanned at time 985,
- Observable with out pin SO.

In such a circuit configuration, no particular problem occurs even if the system clocks C and C3 of the latches 211 and 213 are in phase. This is because when the clock C is sent out at time 955, the L1 latch (mask latch) 211 of the latch 211
The value of A at time 211A may change at time 960, but since shift clock B is off, the value of L2 latch (slave latch) 211B of latch 211 does not change. The output data D3 does not change either. Therefore, the clock C given at time 955
Even if the width of the data is large, the problem of data omission does not occur. When the shift clock B is sent at the next time 970, the output of the L2 latch (slave latch) 211B of the latch 211 changes at time 975, and the output D3 of the combinational circuit 2 changes at time 990. - Since the clock is in the off state, L1 of latch 213
The value of the latch (mask latch) 213A is taken into the L2 latch (slave latch) 213B of the latch 213 without being destroyed. Even if the latches 211 and 213 are in the same phase as described above, no problem arises in diagnosis.

Combinational circuits 1 and 3 can also be tested using exactly the same procedure.

What should be noted in the present invention is the mode control signals M1 and M2.
This is the usage of Ml is connected to the selector 3-1, 3-3 of the odd-numbered latch, for example 211, 213, in the shift string, and M2 is connected to the selector 3-2 of the even-numbered latch, for example 212. The reason for this is related to the O-cycle test and will be explained later using FIG.

FIG. 9 is an example in which the present invention is applied to the random scan type circuit shown in FIG. In FIG. 9, the same reference numbers as in FIG. 3 refer to the same items. Instead of the latches 221 to 223 in FIG. 3, the mask/slave type latches 211 to 213 and selectors 3-1 to 3-3 used in FIG.
is used, and a mode control signal M1 and scan clock signal B are newly added. Latch 211, 212゜2
13 mask latch (Ll latch) 211A.

212A, 213A correspond to latches 221, 222, 223, 6 slave latches (L2 latches) 211B, 212B, 213B and selectors 3-1 to 3-
3 is a newly added element. FIG. 9 differs from FIG. 5 in that the same mode control signal M1 is used for all selectors 3-1 to 3-3.

Note that scan-in data is supplied from terminal SI to L1 latches 211A, 212A, and 213A in parallel,
L2 latches 211B, 212B.

Selector 3-1゜3- connected to each from 213B
2.3-3 is connected in parallel to the OR gate 330 and the scan out terminal So.

However, the L1 latch to take in scan data and the L2 latch to output scan data are performed by supplying the output of address decoder 300 to AND gates 310 and 320.

Figure 10 shows a 0 cycle test 1- for the circuit of Figure 5.
This shows the procedure. 410 to 416 are processes for checking whether the shift strings from L1 latch 211A to L2 latch 211B to selector 3-1 to L1 latch 212A, etc. operate normally during diagnostic operation. be. By alternately sending out shift clocks A and B, a fault on the shift string can be detected by shifting the button input from the scan in pin SI and observing it at the scan out pin SO. However, with this alone, L1 latch 211A,
212A, 213A directly from each selector 3-1.
3-2. Failure on the path leading to the output of 3-2 cannot be checked. For this purpose, it is necessary to switch the mode control signal to '1' and select the output of the L1 latch 211. However, in this case, since the shift string does not have a master-slave configuration, there is a problem that stable shift operation cannot be guaranteed. Two types of mode control signals are used to solve this problem. Step 420
~426 is an odd numbered latch, for example, L of 211, 213
1 latch 211A.

213A to the outputs of the selectors 3-1 and 3-3, and 430 to 436 are processes for checking the paths from the L1 latch 212A of even-numbered latches, such as 212, to the outputs of the selectors. be. In each case, the width of shift clock A must be long enough to allow the scan data to pass through the L1 latch, selector, and into the next latch. Further, the number of times shift clocks A and B are transmitted may be half of that in the case of 412 to 416.

FIG. 11 shows the procedure for a 0 cycle test on the circuit of FIG. 9. 510 to 530 are processes for detecting failures on the path from L1 latch to L2 latch to selector. After selecting the address of each latch and selecting the C1 clock, the C2 clock is sent out. 540-5
60 is a process for detecting a failure on the path from the L1 latch to the selector. It is only necessary to send out the C1 clock.

〔Effect of the invention〕

The circuit configuration of the present invention has been described above. According to the present invention, the logical constraints of in-phase transfer and 1-latch loop can be resolved without significantly increasing the system delay during normal operation, and the system is stable even for circuits that include in-phase transfer and 1-latch loop. Test operation can be guaranteed.

[Brief explanation of drawings]

Figure 1 is a diagram showing an example of a sequential circuit to be diagnosed, Figure 2 is a circuit diagram in which a shift/scan circuit is added to the circuit in Figure 1, and Figure 3 is a circuit diagram in which a shift/scan circuit is added to the circuit in Figure 1. 4 is a circuit diagram with an added circuit. FIG. 4 is a circuit in which the latch in the circuit of FIG. 2 is masked and slaved. FIG. 5 is a circuit configuration diagram in which the present invention is applied to the circuit of FIG. 2. FIG. 6 shows a circuit diagram of a selector used in the present invention. FIG. 7 is a time chart of the circuit shown in FIG. 5 during normal operation, and FIG. 8 is a time chart of the circuit shown in FIG. 5 during diagnostic operation. FIG. 9 is a circuit diagram in which the present invention is applied to the circuit of FIG. 3. FIG. 10 is a flowchart showing the O-cycle test procedure for the circuit of FIG. 5, and FIG. 11 is a flowchart showing the O-cycle test procedure for the circuit of FIG. 9. 100-120...Combination circuits 201-203...Latch 211-223...Latch with scan function 710-
730...External input terminal 740...External output terminal 3...Selector 300...Address decoder'ylt Ward

Claims (1)

[Scope of Claims] 1. A plurality of combinational circuits, each connected to a system data input terminal or a system data output terminal of one circuit of the plurality of combinational circuits, each in response to an input system clock signal; a plurality of first latch circuits that take in system data that is input to the input device, and each of which takes in scan data that is input in response to a first scan clock that is input; and each one of the plurality of first latch circuits; a plurality of second latch circuits connected to the plurality of second latch circuits that capture scan data or system data output from the corresponding first latch circuit in response to an input second scan clock; circuits, each of which is provided corresponding to one set of first and second latch circuits, and in response to a mode signal, the first latch circuit of each set is
a plurality of selection circuits that cut off the data output from the latch circuit and the data output from the second latch circuit and supply them to one of the plurality of combinational circuits, the plurality of first latches The circuit is connected to the scan data input terminal such that scan data input from the scan data input terminal provided in common to the plurality of combinational circuits is supplied to the plurality of first latches, and The selection circuit is connected to the scan data output terminal so that the scan data output from the plurality of selection circuits is supplied to the scan data output terminal provided in common to the plurality of combinational circuits. A logic circuit with a certain data scanning circuit. 2. The output terminal of each of the plurality of selection circuits is connected to the plurality of first selection circuits.
The plurality of first and second latch circuits constitute a shift register provided between the scan data input terminal and the scan data output terminal. is something,
A logic circuit having a data scan circuit according to the first term. 3. The plurality of first latch circuits are connected in parallel to the scan data input terminal, and the logic circuit is connected to the input first latch circuit in parallel.
selectively supplies the first scan clock input in response to the address signal of the plurality of first latch circuits to one of the plurality of first latch circuits; A logic circuit having a data scan circuit according to claim 1, further comprising means for selectively supplying the output of a selection circuit connected to the latch circuit to the scan data output terminal.