JPS61267174A - Vector processor - Google Patents

Abstract

PURPOSE:To execute efficiently the vector processing of a processing including the recursion calculation and to execute the processing at high speed by keeping a waiting condition until the previous processing is completed when the writing/ reading conflict presence/absence information is present, and executing successively the processing. CONSTITUTION:A conflict information preparing circuit 900 writes the vector data based upon the list type for the same area on a main memory 100, investigates, after that, whether the data are read or not, for respective elements of the vector data and prepares the reading/writing conflict presence/absence information. The reading/writing conflict presence/absence information is stored in a vector executing control register 700, based upon the information, an executing control circuit 800 controls a series of the vector processing to which the vector data are related, and when the conflict is present, the circuit controls to process successively as the waiting condition until the previous processing is completed. On the other hand, when the conflict is absent, the waiting condition is not obtained, the control is executed to process continuously.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Application of the Invention] The present invention relates to a vector processor that can perform vector processing at high speed, and particularly to a vector processor that can efficiently process recursion operations.

[Background of the Prophecy]

In order to expand the scope of vector processing, Cray
Hitachi's CraY-1, Hitachi's 8-810. Fujitsu VP-
Vector processors such as 100/200 are equipped with various functions. This includes a function that performs list processing based on in-direct addressing at high speed using vector processing.

but, DO10I=1. N.

10 A(LX(I))=A(LY(I))+B(I
) for different I, I'.

Indexes LX(I) and LY(I') or LX(
If I and LY(I) are equal, then the above D
If an attempt is made to simply perform vector processing on the O statement in a continuous manner using control variables from 1 to No in the conventional manner, correct results may not be obtained. Note that an operation in such a case is called a recursion operation. For this reason, the problem is that high performance cannot be obtained because each part of the control variable engineering is processed sequentially using general instructions, as if it were processed by a general-purpose processor, instead of sequentially executing it using vector instructions. was there.

[Object of the Invention] In view of these problems, an object of the present invention is to realize a vector processor with high processing performance by performing vector processing including recursion operations as efficiently as possible and executing them at high speed. It is said that

[Summary of the invention]

Write vector data based on a list format to the same area on the main memory, and check whether to read it after that for each element of the vector data, and based on this write/read conflict existence/non-existence information, the vector data If there is a conflict, a series of related vector processes are controlled to be processed sequentially in a waiting state until the previous process is completed, and if there is no conflict, they are not placed in a waiting state and are processed continuously as usual. Let it be controlled.

[Embodiments of the invention]

Hereinafter, the present invention will be explained in detail with reference to Examples, but first a detailed explanation of the present invention will be given.

FIG. 1 is an example of a program for explaining an example of operation in the present invention.

FIGS. 2(a) and 2(b) show numerical examples of index data LX(I) and LY(I) in the program example of FIG. 1. It is assumed here that the number N of elements to be processed is 15, and each index value indicates an element number of vector data A.

LY (5) is 15, but LX (Yuri is also 15, so list vector data A (
15) (list vector data A is on the main memory), it is necessary to read out the list vector data A(15) using LY(5) from the main memory. That is, for control variables I=1 to 4, there is no need to be aware of writing/reading to/from the main memory, and conventional vector processing is possible. However, the processing after I=5 is started after waiting for the completion of the processing for I=4, and the processing after I=13 is started after waiting for the completion of the processing for I=12.

Note that it is also possible to perform control to wait for the end of the processing for I=-11 and then start the processing for I=12 and after.
There is no particular difference, and either is fine.

FIG. 2(C) shows read/write conflict presence/absence information, which is a feature of the present invention, created based on the numerical example shown in FIG. This information is created corresponding to control variables 1 to 15, and the value 110 specifies whether a wait state is necessary or not.

That is, the process of the corresponding control variable whose value is set to 1 is placed in a waiting state, and control is performed such that it waits for the previous process to finish before restarting.

FIG. 3 is a diagram showing an embodiment of the present invention.

In the figure, 100 is the main memory, 200 is the scalar processing unit %30
0 is a vector processing unit, 400 is an instruction control unit, 500 is a memory access control unit, 600 is a vector register unit,
700 is a vector execution control register (vECR) that stores the above-mentioned read/write conflict presence/absence information;
00 is VECR,.

An execution control circuit controls the execution of vector processing based on a value, 900 is a conflict information creation circuit that inputs index data and creates read/write conflict presence/absence information, and 1000 is an arithmetic processing unit.

Next, the vector of process 2 (see FIG. 1) shown in FIG.
A method of creating the above-mentioned conflict presence/absence information will be described based on the instruction sequence. The outline of vector processing is as follows. First, preprocessing for executing a vector instruction is performed using a scalar instruction. This preprocessing includes setting address information (address information when accessing the main memory 1oo) to a group of address registers in the memory access control unit 500. Next, the scalar processing device 20
When 0 decodes the BXVP instruction, it activates the instruction control unit 400 to start processing the vector instruction sequence. Command control unit 4
00 takes in the exact instruction string specified by the EXVP instruction via the scalar processing device 200. Then, the fetched instructions are sequentially decoded and vector instructions are processed until a VEND instruction appears. FIG. 5 shows a conflict information creation circuit that creates conflict presence/absence information. In the figure,
610/620 can store 16 elements of data)
A/ Register VR()/VRI, R, 100~R1
15 is a vector index register (VXR) L100 to L11 that can store index data of 16 elements.
5 is a latch for R100 to RIJ5, C100NC
115 is a matching circuit for 'PL10o to R115, G
100 to G115 are AND gates provided corresponding to C100 to C115, R116 is a register, and G116
is an OR gate, 700 is a vector execution control register (V
ECR).

First, the index vector LX stored in the main memory 100 is sequentially converted into 15 elements VB, O by instruction 1 in FIG.
, instruction 2 sequentially reads 15 elements of index vector)yLY to the VRI. Next, the 1 read to VTLO by instruction 3
The 5-element index vector LX is stored in register R100.
~Transfer to R114. In this case, the main memory 100
However, a method of directly reading the data to the registers R100 to R114 is also conceivable.

Finally, instruction 4 is processed, but prior to processing, all latches L100 to L115 are cleared to 0. FIG. 6 shows a part of the processing process of instruction 4 according to the numerical example of FIG. 2. The processing contents of instruction 4 will be explained below based on FIG. 5 while referring to FIG. do.

(1) Step 1: Read vector index LY(1) from vector register vR1 and register R116
to set. At this time, since the latches L100 to L115 are all 0, the gate G100NG115 is not opened and 0 is output from the gate G116, and 0 is stored in the first element of VECR.

(2) Step 2: From vector register VRI to LY(
2) is read and set in register R116, and at the same time, latch L100 is set to 1. At this time, gate G100 opens, but since the values of register 8116 and R100 do not match, 0 is output from coincidence circuit C100, so 0 is output from gate G116 and 0 is stored in the second element of VECR. be done.

(3) Step 3: Vector register VB, LY from 1
(8) is read and set in register R116, and at the same time, latch LIOI is set to 1. At this time, the game) GIOI also opens, but - several circuits C100 and C101
Since 0 is output from G16, 0 is output from Gl 16 and 0 is stored in the third element of VECR.

(4) Step 4: Vector register V'RI to LY
(4) is read and set in register R116, and at the same time, latch L102 is set to 1. At this time, the gate GLO2 is also opened, but - several circuits C100 to ClO2
Since all 0s are output from , 0 is stored in the fourth element of VECR.

(5) Step 5: Vector register VR, 1 to LY
(5) is read and set in register 8116, and at the same time, it is set in latch L103kl and gate G103 is also opened. At this time, since 1 is output from the minus number circuit ClO3, 1 is stored in the fifth element of VECR.

(6) Step 6: From vector register VRI to LY(
6) and set it in register R116.

At the same time, set latch L104 to 1 and
G104 also opens. At this time, - number circuits 0100 to C10
Since all O's are output from 4, 0 is stored in the 6th element of VECR.

The processing proceeds in the same manner, and finally, conflict presence/absence information as shown in FIG. 2(C) is stored from the first element to the 15th element of VECR.

Although this embodiment uses a dedicated vector execution control register, it is also possible to use a mask register held by current vector processors.

It is also possible to perform (for example, logical) calculations between different types of information with and without information, and use the results of this calculation.
In this case, it is desirable to share it with the mask register.

FIG. 7 shows an execution control circuit based on the vector execution control register VEC3. In the figure, 700 is a vector execution control register VBCB%L810 is a vector execution control mode latch, R800-B, 804 is a register, 820 is an address count up circuit, 821 is a glass 1 circuit, 82
2 is a search circuit, 823 is an adder, 824 is a comparator, 8
830-5833 are selectors, 1840. ,! 841°1850-1856 are signal lines.

Vector instruction sequence (based on the program example shown in Figure 1)
(see Figure 4) and the numerical example shown in Figure 2.
The operation of the figure will be explained below. Note that the number of processing elements for each vector instruction in the vector instruction sequence of processing 1 to processing 3 is all 15.
(that is, the loop control variable is 1 to 15), and this value is set on the signal line t840 when the scalar processing device 200 issues an activation command to the instruction control unit 400 to start processing the vector instruction sequence.
At the same time, the start address of the vector instruction string is set in register R800 via signal line t841 and selector 8830. Furthermore, at the same time, latch L810 is cleared to 0. However, the value set in register FL803 is the number of processing elements minus 1. That is, the value 14 is set in register R803. It is assumed that processing 1 and processing 3 include recursion calculations and that conventional vector processing is possible.

In the execution of each instruction of process 1 and instructions 1 to 4 of process 2, the number of processing elements is determined as follows. selector 5833
The starting element number is from the selector 5832, the ending element number is from the selector 5832, and the signal line t855. The command is transferred to the instruction control unit 400 via t854, but now the latch L810 is 0.
Therefore, 0 is selected as the starting element number, and 14, which is the value of register R803, is selected as the ending element number. Note that the element number 0 here is the loop control variable I=1.

It is assumed that element number 14 corresponds to engineering=15.

At the same time, the start address of the vector instruction sequence (the address of the start instruction of process 1) is transferred to the instruction control unit 400 via the signal line t853. That is, in this case, each instruction means that 15 elements can be vector-processed consecutively at once.

Each instruction of process 1 and instructions 1 to 4t of process 2 are decoded and executed sequentially from the beginning of the instruction sequence, but when instruction 5 is decoded,
Although the details are omitted, latch L810 is set to 1 after waiting for the previous instruction to finish.

Also, register R802 is set to -1. Note that at this time, it is assumed that a set signal is transferred from the instruction control 1i400 to the latch L810 via the signal line t820. Further, at the same time as the set signal, the address of the instruction 5 is transferred to the instruction control unit 400 via the signal line t852. Then, the address is counted up to point to the address of the next instruction 6, and set in the register R, 800 via the selector 5830. After that, the value of -1 set in the register R802 is changed to the plus 1 circuit 802.
1 is added to the value O, which is set in the register R801 and simultaneously transferred to the search circuit 822 and adder 823. In the search circuit 822, the plus 1 circuit 821
The value output from the VECR 700 is made to correspond to the element number of the VECR 700, the number of successive 0's appearing from the element number next to the specified element number is counted, and the value is added to the adder 823.
In this case, the value 3 is output. Then, the adder 823 adds the value 0 output from the plus 1 circuit 821 and the value 3 output from the search circuit 822.
The value 3 is set in register R804. register R8
04 and the value of register R803 are compared by comparator 824,
When the value of register R804 is greater than or equal to the value of register R803, 1 is output to signal line t856.

In this case, the comparator 824 outputs 0, and the selector 5
The value 3 of register R804 is transferred to register R8 via 831.
Set to 02. Since the latch L810 is set to 1, the selector 8833 outputs the value 0 of the register R8010 as the starting element number, and the selector 5832 outputs the value 3 of the register R802 as the ending element number, which are transferred to the instruction control unit 400. At the same time, the address of instruction 6 set in register R800 is set to signal line t.
853 to the instruction control unit 400, and then
The instruction control unit 400 starts processing from instruction 6. Although details are omitted, it is assumed that once instruction 10 is decoded, decoding of the next instruction is inhibited.

That is, instructions 6 to 9 indicate that vector processing can be performed continuously for control variables I=1 to 4.

Decoding instruction 10. Then, it waits for the previous processing to complete and then performs the following operations. Note that instruction 10 is not executed. As mentioned above, the value 3 of the register R802 is incremented by 1 in the plus 1 circuit 821 to become the value 4, and is set in the register R801, and at the same time, the search circuit 822
, are transferred to adder 823. The search circuit 822 then outputs the value 7 to the adder 823, and the plus 1 circuit 82
The value 11 is added to the value 4 output from 1 and is sent to register R.
804. Then, since the comparator 824 outputs 0 as before, the value of the register R804 is 11.
is set in register R802 via selector 5831. After that, since the latch L810 is set to 1, the value 4 of the register R801 is set as the starting element number, and the value 11 of the register R802 is set as the ending element number to the instruction control unit 4.
At the same time, the address of instruction 6 set in register R800 is transferred again to instruction control unit 400, and instruction control unit 400 sequentially starts processing from instruction 6. Then, when instruction 10 is decoded, the following operation is performed after waiting for the completion of the previous processing. Note that instruction 10 is not executed. The value 12 is set in register R801, and the value 15 is set in register R804 (however, VEC
The value of RO element number 15 contains the previous calculation result, but it is assumed to be 0 here. Note that there is no particular problem even if it is 1). Since comparator 824 outputs 1 this time, the value 14 in register R, 803 is set in register R, 802 via selector 5831.

After that, start element number 12, end element number 14, instruction 6
The address is transferred to the instruction control unit 400, and processing starts sequentially from instruction 6. Then, I decode instruction 10,
This time, since the signal line t856 is 1 (indicating that the required number of elements have been processed), the processing of this command is performed as follows. That is, a reset signal is transferred to the latch L810 via the signal line t851, and the latch L810 is reset to O. At the same time, the address of instruction 10 is transferred to the address count up circuit 820 via the signal line t852, the address is counted up, and the address of the next instruction (the address of the first instruction in process 3) is sent to the selector 583.
0 to register R800. Thereafter, the instruction sequence in process 3 is executed in the same manner as in process 1 described above.

〔Effect of the invention〕

As explained above, according to the present invention, for example, the -DO
Even if there is a recursion operation in the lv-p, the processing of all DO loops including the recursion operation can be vector-processed at once. It is more efficient than conventional vector processors, and because the recursion calculation section can perform vector processing, albeit partially, it is possible to achieve faster processing than conventional vector processors.

[Brief explanation of the drawing]

FIG. 10 is a diagram showing an example of a program for explaining the present invention in detail, FIG. 2 is a diagram showing a numerical sequence based on the program sequence of FIG. 1, and FIG. 3 is an outline of an embodiment of the present invention. FIG. 4 is a flowchart of processing based on the program sequence shown in FIG. 1, and FIG. 5 shows a conflict information creation circuit for creating write/m output conflict presence/absence information, which is a feature of the present invention. FIG. 6 is a diagram showing an example of calculation based on the creation circuit of FIG. 5, and FIG. 7 is a diagram showing an execution control circuit based on write/read conflict presence/absence information, which is a feature of the present invention. Stem 1 Figure stone 2 Figure (L) ())) (C) Tomi 3 Figure

Claims (1)

[Claims] 1. A vector processor having a function of reading and writing vector data from a main memory based on a list format, which writes the vector data to the same area on the main memory, and then Detects whether to read or not for each element of the vector data and determines whether there is a write/read conflict.
Conflict generation means for outputting as no information; storage means for storing the write/read conflict presence/absence information output from the generation means; based on the write/read conflict presence/absence information stored in the storage means; , if there is a conflict in a series of vector processing related to the vector data, control is performed so that the processing is performed sequentially in a waiting state until the previous processing is completed;
A vector processor characterized in that it has vector instruction execution control means for controlling the execution of vector instructions so that they are processed continuously without being placed in a waiting state when there is no waiting state. 2. The vector instruction execution control means controls execution of a series of vector processing based on the write/read conflict presence/absence information stored in the storage means, or ignores the conflict presence/absence information. The vector processor according to the first term has a switching means for controlling execution of vector processing.