JPS61265899A - Multilayer printed circuit board - Google Patents

Multilayer printed circuit board

Info

Publication number
JPS61265899A
JPS61265899A JP10858085A JP10858085A JPS61265899A JP S61265899 A JPS61265899 A JP S61265899A JP 10858085 A JP10858085 A JP 10858085A JP 10858085 A JP10858085 A JP 10858085A JP S61265899 A JPS61265899 A JP S61265899A
Authority
JP
Japan
Prior art keywords
circuit board
printed circuit
inner layer
reference hole
multilayer printed
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP10858085A
Other languages
Japanese (ja)
Inventor
正光 青木
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Kyocera Chemical Corp
Original Assignee
Toshiba Chemical Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Chemical Corp filed Critical Toshiba Chemical Corp
Priority to JP10858085A priority Critical patent/JPS61265899A/en
Publication of JPS61265899A publication Critical patent/JPS61265899A/en
Pending legal-status Critical Current

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  • Production Of Multi-Layered Print Wiring Board (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。
(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【発明の詳細な説明】 技術分野 本発明はプリント配線基板として使用されている多層プ
リント基板に関し、特に多層プリント基板の内M基準孔
に関する。
TECHNICAL FIELD The present invention relates to a multilayer printed circuit board used as a printed wiring board, and more particularly to an inner M reference hole of a multilayer printed circuit board.

[発明の技術的背景とその問題点] 一般に多層回路基板を製造するにあたっては各内層回路
基板の導体パターン及び最外層の導体パターンが所定の
上下の位置関係を保持していることが要求される。
[Technical background of the invention and its problems] Generally, when manufacturing a multilayer circuit board, it is required that the conductor patterns of each inner layer circuit board and the conductor pattern of the outermost layer maintain a predetermined vertical positional relationship. .

そのため外層回路を形成するにあたっては、内層回路基
板の一部に基準孔マークを入れ・多層成形後、ドリル等
によってその基準孔マークを露出させ、この露出した基
準孔マークを目視しながら所定の位置に外層回路パター
ンを形成していた@しかし多層プリント基板は内層回路
基板の両面にプリプレグ及び銅箔を配置し、これを加熱
加圧して一体成形したものであるので銅箔面から内層回
路基板の基準孔マークの位置を検出するのは困難であっ
た。また内層回路基板の基準孔マークの位置の検出を容
易にするために離型テープを基準孔マークにつけて一体
成形した後、ふくらみ部分をねらって切削加工して露出
させる方法があるが、積載する際に離型テープが位置ず
れを起こし内層回路に付いたりするという問題があり、
また離型テープを配置する場合には作業性が悪くなり、
特にマス・ラミネーション方式で製造するには作業性の
点で大きな弊害となる等の間mがあった。
Therefore, when forming the outer layer circuit, a reference hole mark is placed in a part of the inner layer circuit board, and after multilayer molding, the reference hole mark is exposed with a drill, etc., and the reference hole mark is placed in the specified position while visually checking the exposed reference hole mark. However, since multilayer printed circuit boards are made by placing prepreg and copper foil on both sides of the inner layer circuit board and molding them together by heating and pressing, it is possible to form the outer layer circuit pattern from the copper foil surface. It was difficult to detect the position of the fiducial hole mark. Also, in order to make it easier to detect the position of the reference hole mark on the inner layer circuit board, there is a method of attaching mold release tape to the reference hole mark and molding it, and then cutting the bulge to expose it. There is a problem that the release tape may become misaligned and stick to the inner layer circuit.
Also, when placing the release tape, workability becomes worse,
In particular, when manufacturing by mass lamination, there are problems in terms of workability.

[発明の目的] 本発明は以上のような問題点を解消するためになされた
もので、内層回路基板の露出面に基準孔ヲ設けることに
よって外層回路の形成が容易な多層プリント基板を提供
することを目的とする。
[Object of the Invention] The present invention has been made to solve the above-mentioned problems, and provides a multilayer printed circuit board in which an outer layer circuit can be easily formed by providing a reference hole on the exposed surface of the inner layer circuit board. The purpose is to

[発明の概要] すなわち本発明の多層プリント基板は両面にプリプレグ
が配置された内層回路基板を少なくとも一枚有する多層
プリント基板において、前記各内層回路基板は前記多層
プリント基板の側面にその一部が露出しており、その露
出部には基準孔が各内層回路基板について少なくとも一
箇所膜けられていることを特徴とする。
[Summary of the Invention] That is, the multilayer printed circuit board of the present invention is a multilayer printed board having at least one inner layer circuit board with prepreg arranged on both sides, and each of the inner layer circuit boards has a portion thereof on a side surface of the multilayer printed board. The inner layer circuit board is exposed, and at least one reference hole is formed in the exposed portion of each inner layer circuit board.

本発明は内層回路基板の基準孔が積層板の側面から露出
していることを特徴としているので使用するプリプレグ
としては樹脂フローの少ない低フロータイブのものを用
いる必要がある。またフローした樹脂が基準孔に到達し
ないために、内層回路基板は少なくとも1011以上プ
リプレグより長くしておくことが好ましい。
Since the present invention is characterized in that the reference hole of the inner layer circuit board is exposed from the side surface of the laminate, it is necessary to use a low-flow prepreg with little resin flow. Further, in order to prevent the flowed resin from reaching the reference hole, it is preferable that the inner layer circuit board is at least 1011 times longer than the prepreg.

[発明の実施例] 次に本発明を実施例によって説明する。[Embodiments of the invention] Next, the present invention will be explained by examples.

実施例1 520 +nx 330 nuex 0 、41m(7
)両面フリント基板の端部に基準孔2を開け、この基準
孔2を露光する際の位置合せとして利用して内層回路3
を形成し、内層回路基板1を得た。次いでこの内層回路
基板1を第1図のように6枚配置し、その両面を第2図
に示すように1050msx105105Oのプリプレ
グ4で挾み、最外層に銅箔5を配置した。この際内層回
路基板に設けられた基準孔2はプリプレグ4の外側に出
るように配置する。次いでこの積層板をステンレス板に
挾み、加熱加圧成形することによって4層プリント基板
6を製造した。
Example 1 520 +nx 330 nuex 0, 41m (7
) A reference hole 2 is made at the end of the double-sided flint board, and the inner layer circuit 3 is used to align the reference hole 2 during exposure.
was formed to obtain an inner layer circuit board 1. Next, six of these inner layer circuit boards 1 were arranged as shown in FIG. 1, both sides of which were sandwiched between prepregs 4 of 1050 ms x 105105 O as shown in FIG. 2, and a copper foil 5 was placed on the outermost layer. At this time, the reference hole 2 provided in the inner layer circuit board is arranged so as to come out to the outside of the prepreg 4. Next, this laminate was sandwiched between stainless steel plates and molded under heat and pressure to produce a four-layer printed circuit board 6.

実施例2 実施例1で得られた41IIプリント基板を使用し、次
のようにして6層プリント基板を製造した。
Example 2 Using the 41II printed circuit board obtained in Example 1, a six-layer printed circuit board was manufactured in the following manner.

4層プリント基板を基準孔を残してパネルサイズに加工
し、この基準孔を利用してロータリー印刷法により外層
に液体レジストを塗布した後、エツチングして回路を形
成した。次いでこの411回路基板をプリプレグで挾み
、最外層に銅箔を配置し、実施例1と同様に一体成形し
て6層プリント基板を製造した。
A four-layer printed circuit board was processed into a panel size leaving a reference hole, and a liquid resist was applied to the outer layer using the rotary printing method using the reference hole, and then etched to form a circuit. Next, this 411 circuit board was sandwiched between prepregs, copper foil was placed on the outermost layer, and integrally molded in the same manner as in Example 1 to produce a 6-layer printed board.

実施例3 実施例1の方法で製造した4層プリント基板を基準孔を
残してパネルサイズに加工した後、この基準孔を利用し
てロータリー印刷法により外層に液体レジストを塗布し
た俵、エツチングして片側のみ回路を形成した。次いで
この片側に回路形成された471プリント基板7を第3
図に示すように回路形成された面を内側にし、間にプリ
プレグ16を挾んで2枚重ね、それぞれの基準孔8を固
定ガイド孔として利用して位置ずれ防止用の孔を開け、
ここにズレ防止用ビン9を立てて一体成形することによ
り8wIJプリント基板1oを製造した。
Example 3 A four-layer printed circuit board manufactured by the method of Example 1 was processed into a panel size with reference holes left, and then using the reference holes, a bale with liquid resist applied to the outer layer by rotary printing was etched. A circuit was formed only on one side. Next, the 471 printed circuit board 7 with the circuit formed on one side is attached to the third
As shown in the figure, stack two sheets with the circuit-formed surface facing inside, sandwiching the prepreg 16 between them, and use each reference hole 8 as a fixed guide hole to drill a hole to prevent positional shift.
An 8wIJ printed circuit board 1o was manufactured by erecting a bottle 9 for preventing displacement and integrally molding the board.

実施例4 520 +an+x 330 mg+x 0 、1 m
s+の内層材に回路を形成するにあたり、研磨ライン及
び現像−エッチングー剥離ラインを流す際に基準孔をガ
イド孔として利用した。従来は内層材が0.1msと薄
いタメ・ラインでの巻き込みが発生し使用に限度があっ
たが・この方法を利用すると移送用頭付きベルトニより
スムーズに流すことができた・実施例5 600vsx500+mx0.3msの内層材に基準孔
を4箇所設け、内層回路を形成したものを2枚用意した
。次いで第4図に示すようにこれらの内層回路基板11
の両面にプリプレグ12を挾み最外層に銅箔13を配置
した後、各内層回路基板11の基準孔14をピンで止め
、位置ずれを防止しながらステンレス板に挾み、加熱加
圧成形して6層プリント基板15を製造した。
Example 4 520 +an+x 330 mg+x 0 , 1 m
When forming a circuit on the inner layer material of s+, the reference hole was used as a guide hole when passing a polishing line and a developing-etching-peeling line. Conventionally, the inner layer material was as thin as 0.1 ms, and there was a limit to its use due to the occurrence of entanglement in the line. - By using this method, it was possible to flow more smoothly than with a belt with a head for transfer. - Example 5 600 vs x 500 + m x 0 Two sheets were prepared in which four reference holes were provided in the .3ms inner layer material and inner layer circuits were formed. Next, as shown in FIG. 4, these inner layer circuit boards 11
After sandwiching the prepreg 12 on both sides and placing the copper foil 13 on the outermost layer, the reference holes 14 of each inner layer circuit board 11 are fixed with pins, and the inner layer circuit board 11 is sandwiched between stainless steel plates while preventing misalignment, and heated and press-formed. A six-layer printed circuit board 15 was manufactured.

[発明の効果] 以上説明したように、本発明によれば内層回路基板には
その露出部に基準孔が設けられているので多層プリント
基板製造模においてはこの基準孔を利用して回路形成を
容易に行うことができる。
[Effects of the Invention] As explained above, according to the present invention, since the inner layer circuit board is provided with a reference hole in its exposed portion, the reference hole can be used to form a circuit in a multilayer printed circuit board manufacturing model. It can be done easily.

また本発明の多層プリント基板は、これを2枚以上積層
して多層プリント基板を製造するに際しては位置ずれ防
止用の固定ガイド孔としても利用できるなど、多目的に
利用することが可能であり、特に多層成形の場合にはそ
の都度基準孔を露出させるような面倒がなく、一度作成
した基準孔をその目的によって最終工程まで利用できる
という利点を有する。
Furthermore, the multilayer printed circuit board of the present invention can be used for a variety of purposes, such as being able to be used as a fixing guide hole to prevent misalignment when two or more boards are laminated to produce a multilayer printed circuit board. In the case of multilayer molding, there is no need to expose the reference hole each time, and there is an advantage that the reference hole once created can be used up to the final process depending on the purpose.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本発明の一実施例である4層プリント基板を概
念的に示す平面図、第2図はその断面図、第3図は本発
明の他の一実施例である8層プリント基板を概念的に示
す断面図、第4図は本発明のさらに別の一実施例である
6層プリント基板を概念的に示す断面図である。 1.11・・・内層回路基板 2.8.14・・・基準孔 3・・・・・・・・・・・・内層回路 4.12.16・・・プリプレグ 5.13・・・銅箔 6.7・・・・・・4ffプリント基板9・・・・・・
ズレ防止用ビン 10・・・・・・8層プリント基板 15・・・・・・6層プリント基板 出願人     東芝ケミカル株式会社代理人弁理士 
 須 山 佐 − 第1図 第3図 第2図 第4図
Fig. 1 is a plan view conceptually showing a 4-layer printed circuit board which is an embodiment of the present invention, Fig. 2 is a sectional view thereof, and Fig. 3 is an 8-layer printed circuit board which is another embodiment of the present invention. FIG. 4 is a cross-sectional view conceptually showing a six-layer printed circuit board which is still another embodiment of the present invention. 1.11... Inner layer circuit board 2.8.14... Reference hole 3... Inner layer circuit 4.12.16... Prepreg 5.13... Copper Foil 6.7...4ff Printed circuit board 9...
Misalignment prevention bin 10... 8-layer printed circuit board 15... 6-layer printed circuit board Applicant: Toshiba Chemical Co., Ltd. Representative Patent Attorney
Satoshi Suyama - Figure 1 Figure 3 Figure 2 Figure 4

Claims (1)

【特許請求の範囲】[Claims] (1)両面にプリプレグが配置された内層回路基板を少
なくとも一枚有する多層プリント基板において、前記各
内層回路基板は前記多層プリント基板の側面にその一部
が露出しており、その露出部には基準孔が各内層回路基
板について少なくとも一箇所設けられていることを特徴
とする多層プリント基板。
(1) In a multilayer printed circuit board having at least one inner layer circuit board with prepreg arranged on both sides, a portion of each inner layer circuit board is exposed on the side surface of the multilayer printed circuit board, and the exposed portion is A multilayer printed circuit board characterized in that at least one reference hole is provided in each inner layer circuit board.
JP10858085A 1985-05-21 1985-05-21 Multilayer printed circuit board Pending JPS61265899A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP10858085A JPS61265899A (en) 1985-05-21 1985-05-21 Multilayer printed circuit board

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP10858085A JPS61265899A (en) 1985-05-21 1985-05-21 Multilayer printed circuit board

Publications (1)

Publication Number Publication Date
JPS61265899A true JPS61265899A (en) 1986-11-25

Family

ID=14488415

Family Applications (1)

Application Number Title Priority Date Filing Date
JP10858085A Pending JPS61265899A (en) 1985-05-21 1985-05-21 Multilayer printed circuit board

Country Status (1)

Country Link
JP (1) JPS61265899A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6428890A (en) * 1987-07-23 1989-01-31 Risho Kogyo Kk Manufacture of multi-layer (over 4 layers) printed wiring board
WO2013058287A1 (en) * 2011-10-17 2013-04-25 旭硝子株式会社 Method for manufacturing coupled printed circuit board and coupled printed circuit board

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS50133460A (en) * 1974-04-15 1975-10-22
JPS5426698A (en) * 1977-07-30 1979-02-28 Matsushita Electric Works Ltd Alarm unit using ultrasonic waves
JPS56155596A (en) * 1980-05-02 1981-12-01 Fujitsu Ltd Method of manufacturing multilalyer printed board

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS50133460A (en) * 1974-04-15 1975-10-22
JPS5426698A (en) * 1977-07-30 1979-02-28 Matsushita Electric Works Ltd Alarm unit using ultrasonic waves
JPS56155596A (en) * 1980-05-02 1981-12-01 Fujitsu Ltd Method of manufacturing multilalyer printed board

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6428890A (en) * 1987-07-23 1989-01-31 Risho Kogyo Kk Manufacture of multi-layer (over 4 layers) printed wiring board
WO2013058287A1 (en) * 2011-10-17 2013-04-25 旭硝子株式会社 Method for manufacturing coupled printed circuit board and coupled printed circuit board

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