JPS61265652A - Data transfer controlling system - Google Patents

Abstract

PURPOSE:To simplify the constitution of a circuit by providing a controlling circuit for bundling each data transfer request signal corresponding to each other between each mode in plural modes, determining a priority order between the bundled data transfer request signals, and sending out a permitting signal. CONSTITUTION:When a switching signal is applied to show encoding from a signal line 118, a data transfer request signal is applied from signal lines 27-29, by which a priority order is determined, and permission control of data transfer to a line memory 9 from a 3-state buffer 8, and data transfer to latching circuits 3, 4 from a memory 9 is executed. Also, when the switching signal is applied to show decoding from the signal line 118, the data transfer request signal is applied from signal lines 30-32, by which a priority order is determined, and a permission control of data transfer to the memory 9 from a buffer 6 and to a latching circuit 5 from the memory, and data transfer to a latching circuit 7 from the memory 9 is executed.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to an improvement in a data transfer control method for controlling image data transfer for encoding and decoding in a facsimile machine, for example.

[Technical Background of the Invention] Conventionally, an image data transfer unit for encoding and decoding of a facsimile machine has been configured as shown in FIG.

In the figure, 1 indicates an interface section connected to a half-duplex encoding/decoding section, and 2 indicates an interface section connected to a photoelectric conversion section and a printer section. The interface section 1 is provided with latch circuits 3 to 5 and a 3-state buffer 6, and the interface section 2 is provided with a latch circuit 7 and a 3-state buffer B. ,
Reference numeral 9 indicates a line memory in which image data is stored, and this line memory 9 is connected to the latch circuits 3 to 5.7 and the 3-state buffer 76.8 via a data bus 10. The latch circuits 3 and 4 are for transferring image data for encoding, and from the latch circuit 3, CUR
The image data of the line to be encoded is sent out via RENT LINEll, and the latch circuit 4 sends REFER
Reference line image data necessary for encoding using the MR (Modified READ> method) is sent via the ENCE LINE 12. Also, decoded image data is sent to the 3-state buffer 76 via the CURRENT LINE 13. At the same time, the latch circuit 5 sends out reference line image data necessary for decoding using the IR method (via the REFERENCE LINE 14). On the other hand, from latch circuit 7, P
The image data to be printed out is sent out via fL.
, image data read from the original is sent to the 3-state buffer 8 via the PIX LINE 16. In the above, the image data sent to the latch circuits 3-5, 7 is from the line memory 9, and the image data sent to the 3-state buffer 6.8 is stored in the line memory 9. In the above data transfer, in order to control the data transfer, the decoding request reception circuit 17,
Encoding request reception circuit 18, timing control circuits 19-2
4. AND gates 25 and 26 are provided. When no request signal arrives as an H level on the signal lines 2T to 32, the signals outputted from the decoding request reception circuit 17 and the encoding request reception circuit 18 via the signals 33 to 38 are at the L level. , the signals outputted from the timing control circuits 19 to 24 via the signal lines 39 to 50 are at H level. Therefore, the signal output from AND gate 25.2B is also at H level, and reading and writing of line memory 9 is prohibited.

In the device having the above configuration, when decoding is performed, a data transfer request is made to the PIX LINEt5 via the signal line 27, and an I? EFFERENCE
A data transfer request is made to LINE 14, and signal line 29
A data transfer request is made from the CURRENT LINE 13 via the CURRENT LINE 13.

Also, during encoding, the PIX LI
A data transfer request is made from NE16, and REFERENCE L is made via signal line 31 (a data transfer request is made to NE12, and CUT?RENT is sent via signal line 32).
A data transfer request to LINE II is made.

For example, when a data transfer request signal arrives at the signal line 27 (when it goes to H level), the signal on the signal line 33 goes to H level, and goes to L level via signal lines 39 and 40 at the timing shown in FIG. Then, a signal returning to the H level is output. Therefore, if an address is given to the line memory 9 when the signal on the signal line 39 is at L level, the read enable terminal RD of the line memory 9 receives an L level signal from the AND gate 26, so Image data is output to the latch circuit 10, and the image data is taken into the latch circuit 7 at the timing when the signal on the signal line 40 transitions from the L level to the H level. Similarly, signal line 2
8, the image data in the line memory 9 is fetched into the latch circuit 5, and when the signal arrives at the signal line 29 as H, the image data of the 3-stages 1 to 6 are transferred to the line memory. 9. Further, data transfer control is similarly performed during encoding.

[Problems in the Background Art] As described above, in the conventional data transfer control system, control at the time of decoding and control at the time of encoding are handled independently, so that the receiving circuits (17, 18) and A large number of timing control circuits (33 to 38) are required, resulting in a complicated configuration.

However, when only one of the decoding and encoding data transfers is performed, it is considered possible to halve the number of circuits that perform data transfer control. Also,
When configuring the decoding request reception circuit and the encoding request reception circuit, consider the characteristics of the interface section 1 connected to the encoding/decoding section and the interface section 2 connected to the photoelectric conversion section and the printer section. There is a need. In the interface section 2 of a facsimile machine of the GI [I standard,
Data transfer requests occur at predetermined time intervals. In other words, the reading speed by the charging conversion section and the printing speed by the printer section are constant, and the required data transfer request occurs at predetermined intervals. On the other hand, in the interface unit 1, data transfer requests occur randomly. In other words, the speed of encoding and decoding changes depending on whether the image data contains many white bits or many black bits, and how long the black/white connection continues. Data transfer requests will occur randomly.

Therefore, while data transfer requests originating from the interface unit 1 of a facsimile machine or the like based on the GI [I standard are normally granted with priority, requests originating from the interface unit 2 are granted priority at predetermined intervals. By allowing this, efficient data transfer becomes possible.

[Object of the Invention] The present invention was made in view of the drawbacks of the conventional data transfer control method as described above, and its purpose is to provide a data transfer control method that can simplify and downsize the circuit configuration. is.

[Summary of the Invention] Therefore, the present invention includes first and second systems that generate data transfer requests, and a data memory used for data transfer with the first or second system, In a data transfer control method in which data is transferred between the system, the second system, and the data memory using different data transfer modes of a plurality of modes, data transfer request signals corresponding to each other between the modes of the plurality of modes are provided. The above object is achieved by bundling the data transfer request signals together and providing a control circuit that determines the priority among the bundled data transfer request signals and sends out a permission signal to control the data transfer.

[Embodiments of the Invention] FIG. 1 shows an image data transfer unit for encoding and decoding of a facsimile machine that employs the system of the present invention.

In this figure, the same elements as those in the configuration of FIG. 5 are given the same numbers and their explanations will be omitted. 101 to 103 indicate OR gates. ORGATE 101 has PIX LIN
A data transfer request signal to E15 is applied via signal line 27, and a data transfer request signal from PIX LINE1B is applied via signal line 30.

ORGATE 102 has REFERENCE LINE
A data transfer request signal to REFERENCE LINE 14 is applied via signal line 28, and a data transfer request signal to REFERENCE LINE 12 is applied via signal line 31. Furthermore, ORGATE 103 has CURRENT LIN
A data transfer request signal from E13 is applied via signal line 29, and a data transfer request signal to CURRENT LINEll is applied via signal line 32. The outputs of the OR games 1-101 to 103 are given to input terminals 11 to I3 of the priority order determining circuit 104. When encoding/decoding, assuming that data transfer request signals are not applied to the signal line 28 (or 31) and the signal line 29 (or 32) at the same time, the priority determination circuit 104 is configured as shown in FIG. Ru. Signal 217 from input terminal ■1
is output, a signal 218A is output from the input terminal 2, and a signal 128B is output from the input terminal I3.

Signal 218A and signal @218B become signal 218 via OR gate 226. 201 and 202 indicate F/Fs for request signal latching, and 203, 204, and 205 indicate F/Fs for outputting acceptance signals. 206 indicates a timer;
It outputs an L level signal with a predetermined time width in a predetermined cycle, and outputs an H level signal at other times. 207～
213 represents an AND gate, and 214 to 216 represent inverters, which determine the priority of the request signals 217 and 218 in two ways. One priority order is selected by the timer 206 from these two priority orders. 219
, 220 indicate AND gates, AND gate 219 is for providing a signal to clear F/F 201, and AND gate 220 is for providing a signal to clear F'/F 202. Further, 221 indicates a clock signal, and the clock signal 221 is F/F2O
3,F/F204. It is given to the clock terminal of F/F2O3. 222 indicates a clear signal, and when the clear signal 222 becomes L level, F/F201 to F/F
All 2O3 are cleared. Furthermore, 223 indicates an OR gate, and the OR gate is for transmitting the signals outputted from the Q terminals of F/F2O3 and F/F2O3 as a signal 224.

When the request signal 217 becomes H level, the F/F 20
An H level signal is output from the α terminal of the AND gate 20γ, and this signal is applied to one input terminal of the AND gate 20γ. Since the other input terminal of AND gate 207 is given an H level signal from timer 206, AND gate 207 outputs an H level signal, and this signal is given to one input terminal of AND gate 209. It will be done. At this time, F/F2 is input to the other input terminal of AND gate 209.
Since the H level signal is applied from the terminal 01t, the AND gate 209 outputs the H level signal. When this H level signal is given to the D terminal, F
/F2O3 outputs an H level signal from the α terminal at the rising edge of the clock signal 221. This H level signal is output via the OR gate 223 as a signal @224. F
When an H level signal is output from the α terminal of /F201, an L level signal is given from the inverter 215 to one input terminal' of the AND gate 212, so the output signal of the AND gate 212 becomes L level. . As a result, the AND gate 210 prohibits passage of the H level signal output from the α terminal of the F/F 202. Also,
H level request signal 2 output from OR gate 218
18 arrives earlier than the request signal 217, F
An H level signal is output from the α terminal of the F/F202, and H level signals are applied to the input terminal of the AND gate 210 from the α terminal of this F/F 202, the AND gate 212, and the α terminal of the F/F2O3. It will be done. As a result, F
, /F20/! D @ child is AND gate 210 to H
A high level signal is given, and an H level acceptance signal 22 is sent from the α terminal of the F/F 204 at the rising edge of the clock signal @221.
5 is output. At this time, an L level signal is output from the α terminal of the F/F 204 to one input terminal of the AND gate 209, and an L level signal is given to the D terminal of the F/F 203, so that the request signal 211 reception is prohibited.

In this way, when receiving the request signal 217, the F/F 201
The signal output from the α terminal of the F/F 204 puts the Antogelt 210 in a disabled state and prohibits the reception of the request signal 218, whereas the reception of the request signal 218 is sometimes performed by the signal output from the α terminal of the F/F 204, which activates the AND gate 209. The reception of the request signal 217 is prohibited as a prohibited state. Therefore, when the request signal 217 and the request signal 218 conflict,
Before the L level signal is output from the α terminal of F/F 204, the H level signal is output from the α terminal of F/F 201 and the AND gate 210 is inhibited, so the request signal 217 is accepted with priority. .

On the other hand, when the timer 206 outputs an L level signal, the request signal 218 takes priority over the request signal 217, and when there is a conflict between the request signal 217 and the request signal 21 &, the request signal 218 is accepted, and when there is no conflict, the request signal 218 is accepted earlier. The output request is accepted. Specifically, it is as follows. When the request signal 217 becomes H level, the timer 206
Since the output signal of AND gate 208 is at L level, an H level signal is output from AND gate 208, and this signal is applied to one input terminal of AND gate 211. Furthermore, since the other input terminal of the AND gate 211 is given an H level signal from the AND gate 213,
An H level signal is applied from the AND gate 211 to the D terminal of the F/F 205, and the F/F2O3 outputs an H level signal from the α terminal at the rise of the clock signal @221. This H level signal is output as a signal 224 via the OR gate 223. At this time, F/F
An L level signal is sent from the α terminal of 205 to AND gate 2.
10, and an L level signal is applied to the D terminal of the F/F 204, and reception of the request signal 218 is prohibited. Next, or gate 22
6 to H level request signal 218 is given,
H level acceptance signal 2 from α terminal of F/F 204
The operation until the timer 25 is output is the same as when the output signal of the timer 206 is at the H level, so a description thereof will be omitted. However, the following points are different. An H level signal is output from the α terminal of the F/F 202, inverted by the inverter 216, and an L level signal is given to one input terminal of the AND gate 213, thereby reducing the L level signal output from the AND gate 213. is applied to one input terminal of AND gate 211. Therefore, the trubel signal is applied to the D terminal of F/F2O3 from the AND gate 211, and reception of the request signal 217 is prohibited.

In this way, when receiving the request signal 217, F/F2O3
The signal output from the a terminal of the F/F 202 turns the AND gate 210 into a disabled state and prohibits reception of the request signal 218, whereas the signal output from the Q terminal of the F/F 202 turns the AND gate 211 on when the request signal 218 is received. The reception of the request signal 217 is prohibited as a prohibited state. Therefore, request message @
217 and the request signal 218, when the F/F
Before the torque signal is output from the page terminal of 2O3,
Since the trubel signal is output from the Q terminal of the F/F 202 and inhibits the AND gate 211, the request signal 21
8 will be accepted with priority.

Further, the signal 225 is applied to one input terminal of the AND gate 227.22&. A signal 218A is applied to the other input terminal of the AND gate 227, and a signal 2188 is applied to the other input terminal of the AND gate 228. Then, the output signal 22 of the AND gate 227
9 is the output signal 2 of the AND gate 228 to the output terminal 02.
30 is applied to the output terminal 03, and a signal 224 is applied to the output terminal 01. Output signal of priority determination circuit 104 @10
5 to 107 are timing control circuits 108 to 110, respectively.
is applied to the input terminal IN of. The timing control circuits 108 to 110 have the same configuration, and are composed of an inverter 301, a shift register 302, an AND gate 303, and an F/F 304, as shown in FIG. Input terminal I
The signal given to N is the signal line 305, the inverter 30
Q is applied to the A and B terminals of the shift register 302 through the signal line 306, and the clock is applied through the signal line 306.
It is shifted to the A-QD terminal. shift register 302
The output signal of the QA terminal is given to the CLR terminal of F/F 30d. Further, the output signal of the QB terminal of the shift register 302 is outputted from the output terminal OB via the signal line 308. The signal line 307 is connected to the PR terminal of F/F304.
The Trubel signal and the QD terminal signal of the shift register 302 are applied via an AND gate 303,
Further, the clock terminal CK is grounded. Therefore,
When a 1'' level signal arrives at the input terminal IN, a signal as shown in (39) in FIG. 6 is output from the output terminal OA via the signal line 309 in synchronization with the clock on the signal line 306. , output terminal O via signal line 308
A signal such as (40) in FIG. 6 is output from B.

Output terminal 0AOB of timing control circuits 108 to 110
The signals outputted via the signal lines 111 to 116 are
It is applied to input terminals 1 to I6 of the selector 117. A switching signal for encoding/restoring is applied to the A/B terminal of the selector 117 via a signal line 118.

The latch circuits 3 to 5, 7.3 are connected to the output terminals A1 to A6 of the selector 117 through signal lines 39 to 50 from 81 to B6.
A signal is output to state buffer 76.8, permitting data transfer by the circuit.

FIG. 4 shows the selector 117. Logic circuit 400A~
Since the logic circuits 400C have the same configuration, only the logic circuit 4008 will be described. A signal given from the A/B terminal via the signal line 406 is directly applied to the OR gates 401 and 4.
02, and the same signal is also provided to the OR gate 1103.4od via the inverter 405.

The signal at input terminal 11 is applied to OR gates 401 and 403 via signal line a07, and the signal at input terminal I2 is applied to OR gates 402 and 404 via signal line 408. The output of OR gates 401 to 404 is signal line 4
Output terminal A1.09-412. A2. B1゜B2
is given to. Therefore, the input terminal 11 of the selector 117. Signals such as (39) and (40) in FIG.
When the restoration switching signal indicates encoding (trubel), the encoding/decoding switching signal output from the output terminals Bl and B2 and given via the signal line 118 indicates decoding (trubel).
torque), the output terminal A1. Output from A2.

The image data transfer unit for encoding and decoding of the facsimile machine configured according to the method of the present invention as described above operates as follows.

If the data transfer request signal is applied from the signal line 27 or the signal lines 28 and 29 while the switching signal is applied from the signal line 118 in a manner that indicates encoding (trubel), as explained in FIG. Priorities are determined in this order, and data transfer from the 3-state buffer B to the line memory 9 and data transfer from the line memory 9 to the latch circuits 3 and 4 are permitted and controlled. Also, signal line 1
As explained in FIG. 2, when the switching signal from 18 is switched to indicate decoding (L level), the data transfer request signal is given from the signal line 30 or the signal lines 31 and 32. Priorities are determined in this order, and data transfer from the three-state buffer 76 to the line memory 9, from the line memory 9 to the latch circuit 5, and from the line memory 9 to the latch circuit 7 are permitted and controlled.

As described above, according to this embodiment, data transfer for decoding and encoding can be performed by halving the circuit that performs conventional data transfer control. Although the number of selectors 117 is increased, the number of priority determination circuits and timing control is not as large as that of a decrease in the number of paths, and the overall configuration can be simplified and downsized.

In this embodiment, three timing control circuits are used, and the logic circuits in the selector 117 (, l100A to 4) are used.
00C), but if multiple signals are not active and output from the priority determining circuit 104 at the same time, the timing control circuit and the logic circuit in the selector are each made into one circuit, and the configuration is further changed. Simplification and miniaturization can be achieved.

[Effects of the Invention] As described above, according to the present invention, the configuration of a circuit that performs data transfer control can be simplified and miniaturized.

Therefore, the present invention is suitable for reducing the size and cost of the device.

[Brief explanation of the drawing]

Figure 1 is a block diagram of the main parts of a facsimile machine that adopts the method of the present invention, Figures 2 to 4 are block diagrams of the main parts of Figure 1, and Figure 5 is a block diagram of the main parts of a facsimile machine that uses the conventional data transfer control method. FIG. 6 is a block diagram of the main parts of the device and a timing chart of control signals for read/write, latch, and output enable. 1.2... Interface section 3-5, 7... Latch circuit 6.8... 3-state buffer 9... Line memory 25, 26... AND gates 27-32... Data transfer Request signals 107-103...OR gate 104...Priority determination circuits 108-110...Timing control circuit 117...
Selector Agent Patent Attorney Book 1) Takashi Figure 3

Claims (4)

[Claims] (1) first and second systems that generate data transfer requests;
a data memory used for data transfer with the first or second system, and a plurality of data transfer modes different between the first system, the second system, and the data memory; In a data transfer control method for transferring data, data transfer request signals that correspond to each other in each of the plurality of modes are bundled together, priorities are determined between the bundled data transfer request signals, and a permission signal is sent. A data transfer control method characterized by providing a control circuit that sends out. (2) The data transfer control system according to claim (1), wherein the control circuit sends out a permission signal based on a signal for selecting a desired mode from a plurality of modes. (3) A patent claim characterized in that the first system is a system that generates a data transfer request signal at predetermined time intervals, and the second system is a system that generates a data transfer request signal at arbitrary intervals. The data transfer control method described in item (1) or item (2). (4) The control circuit according to any one of claims (1) to (3), wherein the control circuit changes the priority order among the bundled data transfer request signals at a predetermined period. Data transfer control method.