JPS6313628B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an image processing apparatus such as a facsimile machine, and more particularly to data transmission and reception of an image processing apparatus that divides image data by intermittently operating the motor of an image processing scanner and a printer. This relates to control circuits.

2. Description of the Related Art Conventionally, there has been known a device in which a computer and a facsimile are combined and the facsimile is operated under the control of the computer. FIG. 1 shows the block structure of such a device. A dedicated interface unit 3 for controlling the facsimile 2 is provided between the central processing unit (CPU) 1 of the computer and the facsimile 2, and the facsimile 2 receives control signals such as a power-on signal, a read signal, and a print signal. , motor stop signal, etc. are input.

The computer stores the image data sent from the facsimile 2 and performs predetermined image processing, but when the amount of image data from the facsimile 2 becomes large, it cannot be processed by the main memory of the computer. For this reason, in the past, the image data was divided by intermittently operating the facsimile scanner and printer motor, which made it possible to process a large amount of image data even if the main storage device 4 had a small area. There is. That is, the image data is divided by sending a motor stop signal from the computer to the facsimile 2, and the divided image data is loaded into the main storage device 4 and subjected to image processing, that is, enlargement, reduction, encoding, etc. After image processing, the motor is stopped and the next image data is loaded into the main storage device 4, which is repeated.

Such conventional devices have a drawback that when image data of one image is divided and processed, data is missing or duplicated near the point where the motor is stopped.
That is, as shown in FIG. 2, even when the motor is started, it does not reach a steady constant speed immediately, and even when stopped, it continues to move for a while due to inertia. As a result, when the motor is started, data overlaps such as overreading and overwriting occur, and when the motor is stopped, data is missing such as reading and writing, resulting in disturbances in the reproduced image as shown in Figure 3. .

The present invention eliminates the above-mentioned drawbacks of the conventional device, and even when a large amount of image data is divided and processed by intermittent operation of the motor, it is possible to prevent image data from being duplicated or missing when the motor is started or stopped. An object of the present invention is to provide an improved data transmission/reception control circuit for an image processing device.

The present invention is characterized by a first shift register into which a motor start signal is input;
A first switch circuit that selects one of the parallel outputs of this first shift register, a second shift register that receives the motor stop signal, and selects one of the parallel outputs of this second shift register. one of the parallel outputs of the first shift register selected by the first switch circuit is output as an image data transfer start signal, and one of the parallel outputs of the first shift register selected by the first switch circuit is outputted as an image data transfer start signal; One of the parallel outputs of the two shift registers is output as an image data transfer stop signal.

Embodiments of the present invention will be described below based on the drawings.

FIG. 4 is a block diagram of a control circuit according to an embodiment of the present invention. This circuit is located in a circuit portion that controls the motor and data transfer of the image processing scanner, and it is assumed that a circuit with a similar configuration is also provided for the image processing printer.

In Fig. 4, shift registers 11 and 12 are serial inputs, and 8 is a bit parallel output (A~
The motor start signal from the computer is input to the input terminal IN of the shift register 11, and the input terminal IN of the shift register 12 is input to the input terminal IN of the shift register 11.
A motor stop signal is input to. Further, the motor start signal is passed through the inverter 13 to the Noah gate 14.
one input of the motor, and a motor stop signal to the other input. The output of the NOR gate 14 is guided as a motor control signal to a motor drive circuit of an image processing scanner.

The motor drive circuit starts the motor when the motor control signal from the Noah gate 14 is at a "high" level,
Stops at "low" level. Therefore, when the motor start signal on the input side is "high" and the motor stop signal is "low", the motor control signal becomes "high" and the motor starts moving.

The input terminal IN and each output terminal A to H of the shift register 11 are connected to each switch 1 of the switch circuit 15.
Switch circuit 1 is connected to one end of each switch 5 ₀ to 15 ₈ , and the other end of each switch 15 ₀ to 15 ₈ is connected in common.
The output is 5. The output from the switch circuit 15 is sent as a data transfer start signal to the data transfer control circuit of the image processing scanner.

Similarly, for the shift register 12, its input terminal IN and each output terminal A to H are connected to one end of each switch 16 ₀ to 16 ₈ of the switch circuit 16, and the output from the switch circuit 16 is sent to the data transfer control circuit. Send as a transfer stop signal. Furthermore, a line clock with a period of one scanning line is input to the clock input terminals CK of the shift registers 11 and 12, and a motor start signal and a motor stop signal are sent out in synchronization with this line clock.

Next, the operation of this control circuit will be explained.

First, based on the characteristic diagram shown in FIG. 2, desirable delay times t ₁ and t ₂ for starting and stopping data transfer with respect to starting and stopping the motor are determined. Next, one of the switches of the switch circuit 15 is selected in correspondence with the determined delay time _t1 , and one of the switches of the switch circuit 16 is selected in correspondence with the delay time _t2 . In this embodiment circuit, switch 151 is selected for switch circuit 15, and switch circuit ₁
For No. 6, the switch 16 ₂ is selected to make these switches 15 ₁ and 16 ₂ conductive.

In the initial state, the motor start signal and the motor stop signal are "low", so the motor control signal is "low" and the motor is stopped.

When the computer starts the motor and the motor start signal goes high, the motor control signal goes high and the motor starts.

This motor start signal is also input to the input terminal IN of the shift register 11, shifted by the line clock input to the clock input terminal CK, and sequentially sent from the output terminal A to the output terminal H. Since the line clock is sent out in synchronization with the cycle of one scanning line, the output terminal A becomes "high" after one line time has elapsed after the motor start signal is input to the input terminal IN, and the second line clock After the elapse of time, the output terminal B becomes "high".

Outputs from these output terminals are sent to a switch circuit 15 in the data transfer control circuit of the image processing scanner.
is sent as a data transfer start signal.
Therefore, even if the motor is started by the motor start signal, data transfer by the data transfer control circuit is not performed at the same time, and data transfer starts after one line time when the output terminal A becomes "high". As a result, data transfer is performed after the motor speed becomes constant, and data duplication can be prevented.

At the end of the data transfer, the motor stop signal becomes "high" and the motor is braked, and the motor eventually stops. This motor stop signal is also input to the input terminal IN of the shift register 12, and in the same manner as described above, the output terminal B becomes "high" after the elapse of two lines, and this output is sent to the data transfer control circuit as a data transfer stop signal. and the data transfer ends. Therefore, data transfer must be stopped only after the motor has completely stopped.
Missing data can be prevented.

In this embodiment, the circuit shown in FIG. 4 is provided in the image reading section scanner and the printer, respectively.
The present invention is not limited to this, and the circuit shown in FIG. 4 may be used in common for a scanner and a printer, or two switch circuits 15 and 16 connected to shift registers 11 and 12 may be provided. Then, these two switch circuits may be connected to a scanner and a printer, respectively.

Furthermore, in this embodiment, the period of the line clock is set to the period of one scanning line, so the data transfer delay time can only be changed in units of one line time. By further subdividing, it is possible to create delay times in even smaller units.

As described above, according to the present invention, even when the scanner of the image processing device and the motor of the printer are operated intermittently to perform division processing of image data, duplication or omission of data is prevented when the motor is started or stopped. This will no longer occur, and high-quality reproduced images can be obtained. Moreover, since the present invention is equipped with two shift registers for starting and stopping the motor, the delay times for starting and stopping the motor can be set separately, and the output terminal of the shift register can be set using a switch circuit. Since the delay time can be freely selected and changed, it is possible to flexibly absorb differences in delay time depending on the facsimile machine type, differences in characteristics of motors, etc.

[Brief explanation of the drawing]

Figure 1 is a block diagram of a system that combines a computer and a facsimile. Figure 2 is a speed characteristic diagram of the motor. FIG. 3 is a diagram for explaining the disturbance in the reproduced image that occurs when the motor starts and stops. Fourth
The figure is a block diagram of a control circuit according to an embodiment of the present invention. 11, 12...Shift register, 15, 16...Switch circuit.

Claims (1)

[Claims] 1. The drive motor is controlled intermittently by a motor start signal and a motor stop signal from an external processing device, and image data is transmitted and received to and from the image processing device when the drive motor is operating. An image processing device that performs division processing includes a first shift register to which the motor start signal is input and shifted by a clock signal, and a first switch circuit to select one of the parallel outputs of the first shift register. , a second shift register to which the motor stop signal is input and shifted by a clock signal, and a second switch circuit for selecting one of the parallel outputs of the second shift register, One of the parallel outputs of the first shift register selected by the circuit is output as the image data transfer start signal, and one of the parallel outputs of the second shift register selected by the second switch circuit is output as the image data transfer start signal. A data transmission/reception control device for an image processing device, characterized in that the signal is output as a signal to stop transferring the image data.