JPS60136880A - Picture processing device - Google Patents

Abstract

PURPOSE:To generate a color copy in an extremely short time from a color picture data input by providing an extended bus independently from a main bus, and executing a transfer of a picture data onto the extended bus. CONSTITUTION:This color copying machine has two independent bus lines, namely, a main bus line 1 and an extended bus line 2. The bus lines 1, 2 are managed separately by an extended bus control circuit 3. The main bus line 1 executes a control of the whole copying machine, and the extended bus line 2 is constituted of an extended address 2A, an extended data bus 2D and an extended control bus 20C. Also, a color processing circuit 9, an address generating circuit 10, a picture memory 11 and a picture outputting circuit 12 are connected to each bus, respectively. A color picture information supplying part is constituted of a color original input device 7 and the color processing circuit 9.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to an image processing apparatus used in an apparatus capable of obtaining a color copy in a short time after inputting image data.

[Technical background of the invention and its problems]

In recent years, with the progress of color printer technology, various research and development efforts are underway toward the practical application of color copying machines. There are two types of color copying machines: one that photoelectrically converts original image information and forms a color image through electrical processing, and the other that forms a color image using chemical processing (similar to conventional copying machines).
i! There is an rAO method. Compared to the latter method, the former method currently has disadvantages such as high noise and low resolution, but on the other hand, it does not require chemical processing and can perform a variety of processing in image formation. It is attracting a lot of attention because of its characteristics such as:

By the way, in a color copying machine using such electrical processing, a color image data supply section, a color processing circuit, a color image output section, an image memory, etc. are all integrated into one CPU (Central Processor).
It is controlled by a main control circuit consisting of a ral processing unit, and performs various arithmetic processing and the like.

That is, a large amount of image data supplied from a color image data supply section is once stored in an image memory, and then color processing operations such as color difference signal generation and gamma correction are performed by software. For this reason, it takes a lot of time to obtain a color copy after inputting a color original, resulting in a problem that it is not practical as a color copying machine.

Therefore, a method has been proposed in which the above color processing calculations are performed in real time to shorten the time from color image data input to color copy generation. Conventionally, in color copying machines that perform calculation processing in real time, the entire device was managed by a single CPU, so the transfer of image data between the input/output device and memory or between memories was performed using DMA (Direct). Mcymory Acc
ess) was performed using the core troller. However, D
MA controllers are typically only capable of transferring up to 64 bytes of image data in a single Fast Mode transfer. Moreover, since the DMA controller shares the same bus as the CPU, if a large amount of image data is transferred between an input/output device and memory or between memory and memory in the fastest mode, the CPU will be stuck for a long time. A situation may arise in which the function stops. Unfortunately, it is not possible to transfer a large amount of image data when each input/output device is in operation, and it takes a long time from inputting color image data to producing a color copy.

[Purpose of the invention]

The present invention has been made based on the above-mentioned circumstances, and its purpose is to be able to transfer image data even when it is controlled by a color image circuit, thereby making it possible to input color image data. An object of the present invention is to provide a highly practical image processing device that can generate color copies in an extremely short time.

[Summary of the invention]

The present invention provides a color image data supply unit that supplies image data, an image memory that temporarily stores this image data, and an image data between colors that receives image data read from the image memory and obtains a color image. Transfer is performed via an extension path provided independently from the main path between the color image data supply section and color image output section and the main control circuit, and the extension path during image data transfer is The present invention is characterized in that management is performed by an expansion bus controller, and an address generation circuit determines the address of the image memory when the expansion path selects the image memory.

〔Effect of the invention〕

According to the present invention, an expansion path is provided independently of the main bus, and the data between the expansion bus supply section and the color image output section is not restricted in any way from accessing the color image output section. Image data can be transferred arbitrarily without any need. Therefore, even if the amount of image data transferred at one time is increased compared to the conventional art, the main control circuit will not be stopped for a long time, and as a result, high-speed data transfer can be performed. As a result, color copies can be generated in an extremely short time from the time image data is input.
It is possible to provide an image processing device that is extremely practical.

[Embodiments of the invention]

DESCRIPTION OF THE PREFERRED EMBODIMENTS An example in which an image processing apparatus according to an embodiment of the present invention is applied to a color copying machine will be described below with reference to the drawings.

The color copying machine according to this embodiment has two independent pass lines, namely a main pass line 1 and an extended pass line. Both of these 9-sline lines 112 are managed separately by the extended 14-score control circuit 3. The main pass line J includes a CPU that controls the entire copying machine through this pass line L, and also sets various transfer parameters necessary for transferring image data at the expansion/second line stage, gives a transfer start command, etc. 4
is connected.

Main path line 1 is main address /4 path 1A,
Main data bus 1D and main control bus 1C
An input device control circuit 5 and an output device control circuit 6 are connected to each of these buses. C
The PU 4 controls the color document input device 7 and the color printer 8 via the main/line L1 input device control circuit 5 and the output device control circuit 6, respectively.

On the other hand, the extended i-path line 2 is connected to the extended address bus 2A,
It is composed of an expansion data bus 2D and an expansion control bus 2D. A color processing circuit 9, an address generation circuit 10, an image memory 11, and an image output circuit 12 are connected to each of these buses. The color original input device 7 and the color processing circuit 9 constitute a color image information supply section, and the image output circuit 12 and the color printer 8 constitute a color image output section.

In a color copying machine having such a configuration, when a startup command is given from the CPU 4 to the color document input device 7 via the input device control circuit 5, the color document input device 7 prints the surface of the color document in, for example, three colors. Information on the document is read by scanning it with an image sensor through a filter,
Each color signal is output to the color processing circuit 9. The color processing circuit 9 converts these color signals into a luminance signal and two color difference signals using, for example, a T separation circuit, and performs arithmetic processing such as gamma correction to generate image data. .

The image data generated in this manner is transferred to the image memory 1) in predetermined units via extended path lines. The transfer operation at this time will be described in detail below with reference to FIGS. 2 and 3.

First, in the address register 20 in the expansion bus control circuit 3 shown in FIG. 2, addresses of image data transmitting and receiving circuits, which are set in advance by the CPU 4, are respectively stored. In this state % CPU
4 outputs the start command shown in FIG. 3 to the command yff-) 22 via the main bus buffer 21 of the extended path control circuit 3. The expansion bus control circuit 3 that has input the start command uses the address control circuit #23 to change the address of the sending side circuit stored in the address register 20 to the color processing circuit 9 and the image output circuit 12 (hereinafter referred to as "input/output circuit"). ) or the image memory 11, and if it is an input/output circuit, it is output to the address generation circuit. Further, when the sending side circuit is the image memory 11, the extended address bus 2A is set to high impedance, and the extended address bus 2A is brought under the control of the address generation circuit 10, which will be described later. In this example, since the transmission side circuit is the color processing circuit 9, the expansion/gas control circuit 3 selects the color processing circuit 9.

On the other hand, the read/write switching circuit 25 selects the read/write signal line ~W connected to the upper 6 transmission side circuit.

The read/write timing control circuit 26 detects the falling edge of the start pulse input from the command line 22, delays it for a predetermined period, and then lowers the Yozuna I10 read pulse shown in FIG. . As a result, the image data in the color processing circuit 9 is output onto the extended data bus 2D. After a predetermined period of time has elapsed since the start of outputting image data, the color processing circuit 9 outputs Ilo as shown in FIG.
-Extend the XACK signal to the XAC of the path control circuit 3
It is transmitted to the K control circuit 27. After receiving the I10-XACK signal, the XACK control circuit 27 generates a latch signal having a predetermined width of four pulses as shown in FIG. 3, and outputs this latch signal to the latch circuit 28. The latch circuit 28 inputs and launches the data on the expansion data bus 2D via the expansion bus buffer 24 in response to the latch signal.

When the above-mentioned 2-XACK signal rises, the XACK control circuit 22 detects this and causes the address control circuit 23 to shift to control of the receiving circuit. Since the receiving circuit address in the address register 20 is a number corresponding to the image memory 11, the address control circuit 23 puts the extended address bus 2D in a high impedance state.On the other hand, the read/write switching circuit 25 , the receiver selects the side circuit, that is, the signal line νW connected to the image memory 11. The read/write timing control circuit 26c and the Il detected by the xACK control circuit 27
o - After a predetermined period of delay from the rising edge of the XACK signal, the memory write signal shown in FIG. 3 falls. This memory write signal is input to the image memory 1 and also given to the address generation circuit 10.

The address generation circuit 10 is configured as shown in FIG. 4, for example. That is, the command data 31 includes the starting address TP of the image memory 11 shown in FIG. The number of lines XN in the vertical direction of the image, the number YN of lines in the vertical direction of the image, and information representing the transfer mode are stored. On the other hand, the memory write signal from the expansion path control circuit 3 mentioned above is
The expansion i% of the address generation circuit 1o is inputted to the data control circuit 33 via the z4 spafer 32. First, a leading address TP is set in the address counter 34.

The address set in the address counter 34 is transferred to the extended address bus 2A via the extended/nas buffer 32.
is output to.

As a result, the image memory 11 has the address generation circuit 1
The mental image data latched in the extended path controller 3 is loaded into the storage area specified by 0). After the image memory 11 completes the capture of this image data, it sends the memory XACK signal shown in FIG. 3 to the extended path control circuit 3. Expansion bus control circuit 30X
The ACK control circuit 27 is connected to the memory XAC
The falling edge of the K signal is detected, and the memory write signal output from the read/write timing control circuit 26 is stopped.

This completes the transfer of 1 byte of image data. Further, when the memory XACK signal rises, the XACK control circuit 27 switches the address control circuit 23 to the sending side again, and new image data is transferred.

By the way, the address generation circuit 1O mentioned above sequentially specifies the addresses of the image memory 11 during the process of image transfer. Two asog/down/counters shown in FIG. 4, ie, XN counter 35 and YN counter 36, are used to update the address. On the other hand, the command port stores information indicating the transfer mode as described above.

As this transfer mode, for example, there are four modes shown in FIGS. 6(a) to 6(fd). That is, in the figure, ra) is a standard transfer, (b) is a vertically reversed transfer, (cl is a horizontally reversed transfer, and fω is a vertically and horizontally reversed transfer.) The address generation circuit 1O uses the XN counter 35 according to the specified transfer mode. , YN counter 36 is counted up or down, respectively.For example, in the case of mark transfer, the XN counter 35 and YN counter 36 are both counted up, and in the case of vertical inversion transfer, for example,
The XN counter 35 is increased and the YN counter 36 is decreased. In addition, at this time, the start address TP
are set to addresses corresponding to each transfer mode, as shown in FIG. In this case, image data is transferred from the image memory 11 to the image output circuit 12 by standard transfer. This transfer is also similar to the above! is carried out on the extended path line 3 according to the process.

When the image data is thus transferred from the color processing circuit 9 to the image memory 11, the same image data is then transferred from the image memory 11 to the image output circuit 12. When the image output circuit 12 receives image data, it generates an ink density signal from this image signal and outputs this ink density signal to the color printer 8. As a result, the color printer 8 generates a color copy.

As described above, according to this embodiment, the expansion path control circuit transfers image data from the color processing circuit 9 to the image memory 11 and from the image memory 11 to the image output circuit 12 without depending on the control of the CPU 4. This is done independently under the control of 27. Moreover, the extended path line 2 to which image data is transferred is provided independently of the main path line L used by the CPU 4. Therefore, image data can be transferred even while the CPU 4 is accessing the color original input device 7 and the color printer 8.

Further, according to this embodiment, the number of data that can be transferred in one burst transfer is determined by the number of bits of the XN counter 35 and YN counter 36 in the address generation circuit 10, so the number of data to be transferred can be set arbitrarily in advance. Therefore, the number of data transferred at one time can be increased compared to the conventional method. Moreover, as mentioned above, 4 CPUs are used during the data transfer period.
Since the operation of step 4 is not restricted, there is no problem even if a large amount of image data is transferred at once.

Further, in this embodiment, since the addresses generated by the address generation circuit 10 are updated in the order according to the transfer mode, special measures are required especially for the color original input device 7 and the color printer 8. Transfer can be performed in any transfer mode, such as horizontally reversed or vertically reversed, without adding any additional information.

Furthermore, "0" data is stored in the latch circuit 28 in the extended path control circuit 3, and the data is stored in the image memory 11 according to the address from the address generation circuit 10.
By sequentially storing the "0" data, the entire image memory can be erased very easily.

Note that the present invention is not limited to the above embodiments,
For example, even if multiple image memories are connected to an expansion path line and image data is transferred between the image memories or between multiple input/output devices and the multiple image memories, the expansion path line is used to transfer image data between the image memories or between multiple input/output devices and the multiple image memories. good. In this case, for example, if the latch circuit 28 in the expansion path control circuit 3 is made to latch a plurality of image data as shown in FIG. It is possible to transfer.

Further, in the above embodiment, when storing image data in the image memory 11, the image data is stored in the order according to the transfer mode, but when outputting from the image memory 11,
The data may be read in an order depending on the transfer mode.

In the above-described embodiment, the present invention is applied to a color copying machine in particular, but the present invention can also be applied to, for example, a device that reads still image information from a disk device and obtains a hard copy. be.

In short, the present invention can be implemented with various modifications within the scope without departing from the gist thereof.

[Brief explanation of drawings]

Fig. 1 is a block diagram of a color copying machine according to an embodiment of the present invention, Fig. 2 is a block diagram of an extended path control circuit of the color copying machine, and Fig. 3 is for explaining the operation of the color copying machine. Figure 4 is a block diagram of the address generation circuit of the color copying machine, Figure 5 is a diagram for explaining the correspondence between the image memory and images of the color copying machine, and Figure 6 is the same. FIG. 3 is a diagram for explaining a transfer mode of a color copying machine. ! ...Main pass line, 1A...Main address bus, 1D...Main 7'-ptZ bus, IC...
・Main control path, mutual...extended path line,
2 people: extended address bus, 2D: extended data bus, 2C: extended control path, 7: color original input device, 8: color printer.

Claims (2)

[Claims] (1) A color image data supply unit that supplies image data, an image memory that temporarily stores this image data, and a color image that receives the image data read from this image memory and obtains a color image.The color image data supply unit An expansion path for transferring image data independent of the main path between the color image output unit and the main control circuit is provided, and an expansion path control circuit for controlling the expansion path, An image processing apparatus comprising: an address generation circuit that determines an address of the image memory when selecting a memory. (2) The address generation circuit is one of the preset standard, vertically reversed, horizontally reversed, and vertically and horizontally reversed.
Image processing device 4 according to claim 1, wherein the image processing device updates addresses in an order based on two transfer modes.