JPH0981722A - Method and device for image processing - Google Patents

Abstract

PROBLEM TO BE SOLVED: To enable simultaneous recording by absorbing a difference between transfer speeds of image data to a plurality of external recording devices and improving the read efficiency of the image data. SOLUTION: The image data inputted from a host computer 115 are stored in a frame memory 104 and a decision unit 111 finds the ratio of the image transfer speeds of copying machines (1) 113 and (2) 114; and a memory controller 103 reads the image data out of the frame memory 104 to FIFOs (1) 105 and (2) 106 at the image transfer speed ratio, and the image data are sent from image processing parts (1) 107 and (2) 110 and input/output buffers (1) 109 and (2) 110 to the copying machines (1) 113 and (2) 114 and printed at the same time.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image processing method and apparatus having a data transfer function with an external device such as a host computer or a copying machine.

[0002]

2. Description of the Related Art Conventionally, data is received from an external device holding various data such as a host computer, image data is formed on a frame memory based on the received data, and image processing is performed on these image data. There is an image processing apparatus that transfers image data to an external printing apparatus such as a copying machine and outputs an image.

In recent years, the number of process technologies used in digital copying machines has increased, and the processing speed of digital copying machines has also changed. Therefore, each copying machine has an interface function, and different copying machines have different interface functions. The image data developed on the frame memory is transferred and simultaneously printed.

FIG. 2 is a block diagram showing the configuration of this type of image processing apparatus. As shown, the device is a CPU
201, external I / O interface 202, frame memory 204, memory controller 203, FIFO2
05, a FIFO 206, an image processing unit 207, an image processing unit 208, an output buffer 209, and an output buffer 210, a host computer 211 that creates image data and transfers it to the apparatus, a copying machine 212 for printing an image, and a copy. Machines 213 are respectively connected.

The processing procedure of the present apparatus having the above configuration will be described below with reference to the flowchart shown in FIG.

First, according to an instruction from the host computer 211, image data is transferred from the host computer 211 to the image processing apparatus 200 (step S10).
1). The image data is the external I / O interface 202.
It is received by the CPU 201 via the and stored in the frame memory 204 (step S102). This process is repeated until the image data transfer from the host computer 211 is completed (step S103). When all the image data from the host computer 211 is stored in the frame memory 204, the printing operation to the copying machine is started according to the instruction from the host computer 211 (step S104).

First, the CPU 20 is sent to the memory controller 203 so as to read the image data to the copying machine 212.
1 performs register setting. Here, the memory controller 203 having the register set confirms that the contents of the FIFO 205 are empty (step S105), and transfers the image data from the frame memory 204 to the FIFO (step S106). The FIFO is used to absorb the difference between the operation clock of the CPU and the transfer speed of the image data to the copying machine. When the transfer of the image data to the FIFO 205 is completed, the image data is transferred to the FIFO.
After being transferred from O205 to the image processing unit 207 and subjected to necessary image processing such as enlargement or reduction (step S1).
10), the image data is transferred to the copying machine via the output buffer 209 (step S111).

At the same time when the transfer of the image data to the above-described FIFO 205 is completed, the CPU 201 sets a register in the memory controller 203 so that the memory controller 203 reads the image data to the copying machine 213. Here, the memory controller 203 having the register set confirms that the contents of the FIFO 206 are empty (step S107), and transfers the image data from the frame memory 204 to the FIFO 206 (step S108). The image data transferred to the FIFO 206 undergoes the same image processing as the image data transferred to the FIFO 205 (step S11).
2) and transferred to the copying machine 213 (step S11)
3).

The above process is repeated to repeat the frame memory 2
When all the transfer of the image data from 04 is completed (step S109), the image is printed from each copying machine.

[0010]

However, the above-mentioned conventional example has the following drawbacks.

1) When the transfer speed of image data to the copying machine connected to the image processing apparatus is much lower than the transfer speed to the copying machine, it takes a long time to transfer the image data to the copying machine. As a result, transfer of image data to the FIFO is delayed.

2) When an image data read clock from the FIFO to the corresponding image processing unit is generated in the image processing apparatus, its frequency becomes a fixed value, and that portion is changed for each copying machine having a different image data transfer speed. It needs to be remade.

The present invention has been made to solve the above problems, and absorbs the difference in the image data transfer rates to a plurality of external recording devices to improve the reading efficiency of image data and simultaneously record images simultaneously. An object of the present invention is to provide an image processing method and apparatus that can perform the image processing.

[0014]

In order to achieve the above object, the image processing method of the present invention has the following steps.

That is, an input step of inputting image data from an external device, a storing step of storing the image data input by the input step in a storage means, and an image transfer speed of a plurality of external recording devices are used to determine the distance between the external recording devices. Of the image transfer speed ratio, and a transfer step of reading the image data stored in the storing step based on the determination result of the determining step and transferring the image data to each external recording device.

In order to achieve the above object, the image processing apparatus according to the present invention has the following configuration.

That is, input means for inputting image data from an external device, storage means for storing the image data input by the input means, and image transfer between the external recording devices based on the image transfer rates of the plurality of external recording devices. A determination unit that determines the speed ratio and a transfer unit that reads the image data stored in the storage unit based on the determination result of the determination unit and transfers the image data to each external recording device are provided.

In such a structure, the difference in the image data transfer rates to a plurality of external recording devices is absorbed, the efficiency of reading image data from the storage means is improved, and simultaneous recording is performed.

[0019]

Embodiments of the present invention will be described below in detail with reference to the drawings.

FIG. 1 is a block diagram showing the schematic arrangement of the image processing apparatus according to the first embodiment. In the figure, 101
The CPU shown in FIG. 6 controls each part inside the image processing apparatus, and controls various operations by reading the program stored in the ROM shown at 112. 1
Reference numeral 02 denotes an external I / O interface for receiving image data and the like from an external device such as a host computer shown at 115, which is under the control of the CPU and is used for transmitting / receiving data in accordance with the data transfer mode of the external device. It is a thing. Reference numeral 116 denotes a work RAM for temporarily holding data and the like required when the CPU executes the program. 103 is a memory controller,
4 is for controlling the frame memory when performing DMA transfer to the frame memory that stores the image data shown in FIG. FIFOs 105 and 106 are for absorbing the speed difference between the operating speed of the CPU and the image data transfer speed to the copying machine.

Reference numerals 107 and 108 are for performing image processing such as enlargement and reduction on the image data read out from the frame memory, and selection of enlargement and reduction, and change of the proportion thereof are instructed by the CPU. can do. 10
Reference numerals 9 and 110 denote input / output buffers for outputting the image data processed by the image processing unit to the copying machine side and inputting the image scanned by the copying machine to the image processing unit. Reference numeral 111 denotes a determiner which receives a synchronous clock for image transfer from an external device such as a copying machine shown by 113 and 114, which is connected to the image processing device, and which synchronizes the synchronous clock of each external device within a certain period. Determine the number, C
It is for notifying the PU.

The operation of the apparatus according to the first embodiment having the above configuration will be described below.

FIG. 4 is a flow chart showing the operation in this embodiment. First, the host computer 115
Host computer 115 is triggered by an instruction from
The image data is transferred to the image processing apparatus 100 (step S201). Next, this image data is external I
It is transmitted to the CPU 101 via the / O interface 102, and is expanded on the frame memory 104 by the CPU 101 (step S202). Then, the image data is repeatedly received from the host computer 115, and the image data is stored in the frame memory 104 (step S203).

Next, when all the image data from the host computer 115 is stored in the frame memory 104, the printing operation is started according to the instruction from the host computer 115 (step S204). CPU 101
Reads the number of image transfer clocks of each copying machine connected to the image processing apparatus within a certain time from the determiner 111, and from this, the ratio of the image transfer speeds of each copying period connected to the image processing apparatus. To calculate.

Here, the details of the judging device 111 will be described. FIG. 5 is a diagram showing a schematic configuration of the judging device, and shows an example in which two copying machines are connected. Image transfer clocks used for synchronous transfer of image data are input to the image processing apparatus from a plurality of copying machines connected to the image processing apparatus. The image transfer clocks are respectively connected to counters inside the determiner 111, and the clocks are counted here. In addition, the host computer 115
When an image printing instruction is issued from the controller 503, the controller 503, which controls the inside of the determiner 111, outputs a reset signal to the counters 501 and 502, and the count-up of the image transfer clock is newly started. Two counters 50
Outputs of 1 and 502 have decoders of 504 and 505, respectively, and when the output value from each of the counters 501 and 502 reaches a predetermined value, the decoded signal is given to the controller 503 inside the determiner 111. . When the decoded signal is transmitted to the controller 503,
The controller 503 instructs each of the counters 501 and 502 to stop the count-up operation.
In each of the counters 501 and 502, the counted value is written in the ports 506 and 507 inside the determiner 111. Then, when the controller 503 notifies the CPU 101 of the completion of the count-up, it reads the values of the two ports 506 and 507 and calculates the ratio of the transfer rates of the two copying machines connected to the image processing apparatus.

In this way, when the CPU 101 calculates the ratio of the transfer rates of the two copying machines connected to the image processing apparatus, the CPU 101 then causes the memory controller 10 to operate.
3 is set (step S205). As a result, the memory controller 103 requests the right of the address bus and the data bus from the CPU 101 (step S206),
105, 106 when the CPU 101 gives up the bus right
The image data is transferred to the FIFO shown in (step S2)
08). At this time, as described above, the memory controller 103 changes the ratio of the transfer of the image data to each copying machine according to the transfer speed ratio between the copying machines obtained by the CPU 101.

Here, the transfer control of image data by the memory controller 103 will be described in detail. FIG. 6 is a diagram showing a schematic configuration of the memory controller 103. Here, an example is shown in which two copying machines are connected to the image processing apparatus. In the figure, reference numeral 601 denotes a CPU bus interface, which has data latch and input / output buffer functions for connecting to the CPU bus. 602 is DRA
It is an M bus interface and has an input / output buffer function for connecting to a DRAM address, a data bus, and control signals such as RAS and CAS. Reference numeral 603 is a refresh controller, which performs control for refreshing at the specified refresh timing of the DRAM. Reference numeral 604 is a wait state controller for causing the DRAM to perform a read / write operation in accordance with the bus cycle of the CPU bus. 605 is DM
A controller, DRAM instead of CPU 101
Read and write operations from and to the DMA are performed. Reference numeral 606 is for decoding with the signal from the above-mentioned DMA controller 605 to generate an enable signal to the FIFO of 105 and 106.

Reference numerals 607 and 608 are base address registers, which are used to input / output data to / from the DRAM. Reference numerals 609 and 610 are registers into which the number of image transfer synchronization clocks of individual copying machines within a fixed time is written. Reference numerals 611 and 612 are counters, which are incremented when data for one pixel is input / output from the DRAM. Reference numerals 613 and 614 are comparators, and each register 609 and 610 and each counter 611 and 6
The output values of 12 are compared, and when they match, a signal for clearing the counter and for causing the DMA controller to switch the base address register is output.

Next, the control of the memory controller will be described in detail. FIG. 7 is a flowchart showing the control procedure of the memory controller. As mentioned above, C
When the PU 101 calculates the image transfer rate of each copying machine,
The value is written in the register of the memory controller 103. Here, two copying machines are connected to the image processing apparatus, which are a copying machine and a copying machine, respectively. If the ratio of the image transfer rates of the copying machine is 3: 1, "3" is written in the register and "1" is written in the register (step S301). register,
When the value is written in, the memory controller 103 requests the bus right from the CPU 101 (step S302). Then, the CPU 1 requested for the bus right
When 01 terminates the current job and abandons the bus right, the memory controller 103 acquires the bus right on behalf of the CPU (step S303). next,
The memory controller 103 reads out the head address of the image data to be output to the copying machine, which is written in the work RAM 116 in advance, and stores it in the base address register inside the memory controller 103 (step S304). . Specifically, the base address register stores the start address of the image output to the copying machine, and the base address register stores the start address of the image output to the copying machine.

When a value is written in the base address register, image data transfer to the copying machine is started. First, image data is transferred to the copying machine. The DMA controller 605 inside the memory controller 103
A signal is output to the decoder 606 so that the O105 is enabled, and the decoded result is stored in the FIFO105.
Is connected to the enable terminal (step S305).
Then, the DMA controller 605 reads the data from the address indicated by the base address register and writes the value in the FIFO 105 (step S30).
6). When the data transfer for one pixel is completed, the DMA controller 605 increments the value of the base address register and sets it to the address where the image data to be read next is stored (step S307). Next, D
The MA controller 605 increments the value of the counter 611 (step S308), and repeats the above operation until the comparator 613 determines that the value of the counter 611 and the value of the register 609 match (step S309).

Next, the comparator 613 causes the counter 6
When it is determined that the value of 11 and the value of the register 609 match, the DMA controller 605 sends a signal to the decoder 606 so that the image data can be output to the FIFO 106, and the decoded signal enables the FIFO 106. It operates (step S310). Then, the DMA controller 605 reads the address where the image data is stored from the base address register and transfers the extracted image data to the FIFO 106 (step S311). When the transfer to the FIFO 106 is completed, the values of the base address register and counter 612 are incremented (step S31).
2, S313). Similar to the image transfer to the copying machine 113, the image transfer to the FIFO 106 is repeated until the value of the counter 612 matches the value of the register 610,
When the values of the counter 612 and the register 610 match, the next operation is performed.

The above-described operation is performed for all images in each FIFO.
Repeat until output is completed for. Each FIFO
After being subjected to image processing by each image processing section, the image data transferred to each of the copying machines are transferred to each copying machine via each input / output buffer, and printed.

As described above, depending on the image transfer rate written in the register, the FIFO,
The ratio of the image data written to is different, and the one recognized as having a high image transfer speed by the CPU has a large transfer amount of the image data within a certain period, and the one recognized by the CPU as having a low image transfer speed. The transfer amount of image data within a fixed period is reduced.

Therefore, even when a copying machine having a low image transfer speed is connected, the efficiency of accessing the DRAM can be improved without keeping the copying machine having a high image transfer speed waiting. Optimal simultaneous printing can be realized for the connected copying machine.

Although only two copying machines have been described in the embodiment, simultaneous printing can be realized by the same means even when two or more copying machines are connected.

[Second Embodiment] Next, a second embodiment of the present invention will be described in detail with reference to the drawings. FIG. 8 is a block diagram showing the schematic arrangement of the image processing apparatus according to the second embodiment. In addition, the same reference numerals are given to those having the same functions as those in the first embodiment, and the description thereof is omitted here.

The difference from the first embodiment is that a display controller 801 for connecting the display 804 to the CPU 101 and a VRAM 802 for storing the image data displayed on the display 804.
And a hard disk 803 for storing the state of the image processing apparatus.

The speed of the image transfer clock peculiar to the copying machine does not change, and once it is set in the image processing apparatus, it is not necessary to change the value until the copying machine is changed. Then, using the display controller shown in 801, a setting screen of the copying machine to be connected is prepared as shown in FIG. 9, and the copying machine is set with the keyboard shown in 805.
The set contents are stored in a nonvolatile recording medium such as a hard disk 803 inside the image processing apparatus. Then, when the image data in the frame memory 104 is output to a copying machine connected to the image processing apparatus, the CPU 101 stores the image data transfer rate of each copying machine stored in the nonvolatile recording medium such as the hard disk 803. Read
The image transfer rate between the copying machines is calculated, and the calculation result is set in the register in the memory controller 103.
Image data is transferred in the same manner as in the above embodiment.

The present invention may be applied to a system composed of a plurality of devices "host computer, interface, printer, etc." or to a device composed of a single device "copier". . Further, it goes without saying that the present invention can also be applied to a case where the program according to the present invention stored in a storage medium is implemented by being supplied to a system or an apparatus.

[0040]

As described above, according to the present invention, it is possible to absorb the difference in the image data transfer rates to a plurality of external recording devices, improve the reading efficiency of image data, and perform simultaneous recording. Becomes

[0041]

[Brief description of drawings]

FIG. 1 is a block diagram showing a schematic configuration of an image processing apparatus according to a first embodiment.

FIG. 2 is a block diagram showing a configuration of a general image processing apparatus.

FIG. 3 is a flowchart showing a processing procedure of the apparatus having the configuration shown in FIG.

FIG. 4 is a flowchart showing an operation in the first embodiment.

5 is a diagram showing a schematic configuration of a determiner shown in FIG.

FIG. 6 is a diagram showing a schematic configuration of the memory controller shown in FIG. 1.

FIG. 7 is a flowchart showing a control procedure of the memory controller.

FIG. 8 is a block diagram showing a schematic configuration of an image processing apparatus according to a second embodiment.

FIG. 9 is a diagram showing a setting screen of a copying machine to be connected in the second embodiment.

[Explanation of symbols]

 100 image processing apparatus 101 CPU 102 external I / O interface 103 memory controller 104 frame memory 105 FIFO 106 FIFO 107 image processing unit 108 image processing unit 109 input / output buffer 110 input / output buffer 111 decision unit 112 ROM 113 copying machine 114 copying machine 115 Host computer 116 Work RAM

Claims (6)

[Claims] 1. An input device for inputting image data from an external device, a storage device for storing the image data input by the input device, and an image transfer between the external recording devices according to an image transfer speed of a plurality of external recording devices. Image processing comprising: a determination unit that determines a speed ratio; and a transfer unit that reads out image data stored in the storage unit based on the determination result of the determination unit and transfers the image data to each external recording device. apparatus. 2. The determination means receives a synchronization signal for image data transfer from a plurality of external recording devices, and determines an image transfer speed ratio between the external recording devices. The image processing device described. 3. The image processing apparatus according to claim 1, further comprising setting means for setting image data transfer rates of a plurality of external recording devices. 4. An input step of inputting image data from an external device, a storing step of storing the image data input in the input step in a storage means, and a step of storing the image data between the external recording apparatuses according to an image transfer speed of the plurality of external recording apparatuses. Of the image transfer speed ratio, and a transfer step of reading out the image data stored in the storing step based on the determination result in the determining step and transferring the image data to each external recording device. Image processing method. 5. The determining step receives a synchronization signal for image data transfer from a plurality of external recording devices, and determines an image transfer speed ratio between the external recording devices. The described image processing method. 6. The image processing method according to claim 4, further comprising a setting step of setting image data transfer rates of a plurality of external recording devices.