JPH0134426B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a facsimile encoding circuit, and more particularly to an encoding circuit for a facsimile machine having an original reading section that scans an original at a constant speed in the main scanning direction.

Conventionally, this type of facsimile encoding circuit has had a configuration as shown in FIG. 1, for example. 1st
In the figure, 1 is a document reading section, 2, 3a, 3
b, 4a, 4b, 5, 6, and 7 are elements constituting a line memory section that temporarily stores image signals for each scanning line, 8 is a change point detection circuit, 9 is a run length counter, and 10 is a clock generator. 11 is a control circuit that performs encoding, and 12 is a modulation section. Although the details are omitted here, the image signal P1 generated in the original reading section 1 is sequentially stored in the memory elements 3a and 3b, and is stored in the line memory sections 2, 3a, 3b, 4a, 4.
When the image signal P1 is written to the memory element 3a for each scanning line under the control of the control circuit 11, the image signal P of the previous scanning line is sent from the memory element 3b.
2 and writing the image signal P1 to the memory element 3b, the image signal P of the previous scanning line is read from the memory element 3a.
It operates by reading 1. Such a temporary storage circuit for image signals is generally used in facsimile codes that have an original reading section that performs main scanning at a constant speed, since it is necessary to start and stop reading out image signals in order to perform encoding. In encoding, it is essential to match the image signal generation speed from the document reading section and the image signal readout speed for encoding. During encoding, the change point from white to black or from black to white in the image signal P2 read from the line memory section is detected by the change point detection circuit 8, and the number of pixels between the change point and the next change point is detected. is counted by a run length counter 9 to determine the run length. The control circuit 11 reads the value of the run length counter 9 every time the change point detection circuit 8 detects a change point, encodes the run length, and sends encoded data to the line via the modulation section 12.

SUMMARY OF THE INVENTION An object of the present invention is to eliminate the redundant part, that is, the run length counter, existing in the conventional encoding circuit described above, and to provide a cheaper and more reliable encoding circuit.

According to the present invention, in a facsimile encoding circuit having an original reading unit that scans an original at a constant speed in the main scanning direction and a storage circuit that temporarily stores image signals from the original reading unit, an image signal stored in the storage circuit is provided. In order to read out the image signal pixel by pixel, the output of the address counter that provides the read address to the memory circuit is directly input.
It is connected to a control circuit that executes encoding, and every time a change point occurs in the readout image signal, the control circuit outputs the readout address counter output (Q _o-1 ) at the time of the previous change point.
By configuring the system to encode the difference (Qn - Q _o-1 ) between the current change point and the read address counter output (Qn) as a run length, the circuit scale is smaller than that of conventional encoding circuits. An inexpensive and highly reliable encoding circuit can be obtained.

Next, embodiments of the present invention will be described with reference to the drawings. Referring to FIG. 2, this embodiment includes a document reading section 1, a write clock switching section 2, memory elements 3a and 3b for two lines, and memory elements 3a and 3b.
address selectors 4a and 4b respectively connected to
, a write address counter 5, a read address counter 6, a data selector 7 connected to the outputs of the storage elements 3a and 3b, and a change point detection circuit 8 connected to the output image signal P2 from the data selector 7.
, a clock generation circuit 10, a control circuit 11,
It includes a modulation section 12. The control circuit 11 includes a CPU 115,
It includes a RAM 116, a ROM 117 storing programs and a code table, an output port 111, an input port 112, input ports 113 and 114, and a modulation section interface 118. Output port 11
1 are address selectors 4a, 4b, write clock switching unit 2, data selector 7, read counter 6,
It is connected to the change point detection circuit 8 and controls its operation. The input port 112 inputs the output of the change point detection circuit and the state of the document reading section. The input port 113 receives the output P2 of the data selector and the upper three bits of the read address counter. Input port 114 inputs the lower 8 bits of the read address counter. The modulation unit interface is modulation unit 1
2 and includes a P/S (parallel-to-serial) conversion circuit.

According to this embodiment, the document reading section 1 scans the document at a constant speed in the main scanning direction, generates a binary image signal P1, and generates a binary image signal P1 along with a write clock CK1 and a phase signal PH indicating the start of a scanning line. Output. The write address counter 5 is cleared by the phase signal PH, counts the write clock CK1, and outputs the write address (Q). Memory elements 3a and 3b each have 1
Capacity that can store pixels for scanning lines (in this example,
The binary image signal P1 is sequentially written in synchronization with the write clock according to the output of the write address counter, and the image signal for one scanning line is stored.
During this writing, the write clock CK1 is outputted to only one of the clocks 3a or 3b by the select output S from the output port 111 by the write clock switching section. Further, when the write clock switching section 2 outputs the write clock CK1 to the write address counter 4a, 4b, the selector 4a selects and outputs the write address WA to the storage element 3a, and the selector 4b selects and outputs the write address WA to the memory element 3a. Address RA is output to storage element 3b. Further, when the write clock switching unit 2 is outputting the write clock CK1 to the memory element 3b, the selector 4b selectively outputs the write address WA to the memory element 3b, and the selector 4a outputs the read address RA to the memory element 3a. is configured to print. Further, the read data selector 7 also receives the select output S from the output port 111.
When the address selector 4a is selectively outputting RA, the read data from the storage element 3a is selectively output, and when the address counter 4b is selectively outputting the RA, the read data from the memory element 3b is selectively output.
That is, to summarize the operations of the above-mentioned parts, when the select output S from the output port 111 writes the image signal P1 from the document reading section 1 to the memory element 3a, the image signal of the previous scanning line is written from the memory element 3b to P2. When reading the image signal P1 into the storage element 3b,
It operates to read out the image signal of the previous scanning line from the memory element 3a to P2. As a result, even if the image signal from the original reading section 1 is input at a constant speed for each scanning line, the reading of the image signal can be started and stopped independently of the operation of the original reading section 1.

Now, the control circuit 11 is a processor circuit in which the CPU 115 operates according to a program stored in the ROM 117, and its configuration and operation are well known, so the details of its internal operation will be omitted.
The initial select output S is set so that the memory element 3a is in the write mode and the memory element 3b is in the read mode, and the phase signal PH from the document reading section 1 is monitored to complete writing of the image signal for one scanning line. Knowing this, the select output S is inverted to set the memory element 3a to the read mode and the memory element 3b to the write mode, and at the same time output a read start signal ST from the output port 111 to clear the read address counter 6 and detect the change point. Initialize circuit 8. Next, input the read start signal ST.
When turned off, the read address counter counts the clock CK2 from the clock generating circuit 10, sequentially increments the address, and the image signal in the memory element 3a is read out. At the same time, the change point detection circuit 8 searches for a change point from white to black in the image signal P2 in synchronization with the clock CK2, and outputs a change point detection signal CH when a change point from white to black occurs. In response to the change point detection signal CH, the read address counter 6 stops counting. Control circuit 11
is the change point detection signal CH via the input port 112.
Knowing that is turned on, input ports 113 and 11
4, the image signal P2 at that time and the value RA of the read address counter are read. Find the difference between the current RA value Qn and the previous RA value Q _o-1 (initial value is 0), encode this as a run length, and then
The value Qn of RA is stored as Qo _-1 at a predetermined address in the RAM 116, and a restart signal RS is output. The change point detection circuit 8 turns off the change point detection signal CH by the restart signal RS,
Starts the next change point detection operation. The read address counter 6 also restarts address counting when the change point detection signal CH turns OFF. Thereafter, the above operations are repeated in the same manner until the encoding for one scanning line is completed. When the encoding of one scanning line is completed, the control circuit 11 monitors the phase signal PH, and when the image signal for the next one scanning line has been written to the storage element 3b, it inverts the select output S and outputs the signal to the storage element 3b. The image signal is read out from 3b and encoded by repeating the above-described operation, and the image signal of the next scanning line is controlled to be written into the storage element 3a.

FIG. 3 shows a circuit example of the change point detection circuit 8.
It is clear that the circuit of FIG. 3 allows the operation described above.

The data encoded in the above manner is stored in RAM
116 and is temporarily stored in the modulator interface circuit 11 in response to the clock CK3 from the modulator.
8 to the modulator as image information data D, which modulates the image information and outputs it to the line.

According to this embodiment, it is possible to encode the image signal as explained above, and the run-length counter used conventionally is not required, so the circuit is simplified and the encoding is more economical than the conventional one. A circuit is obtained.

As explained above, the present invention is configured so that the output of the read address counter can be input to a control circuit composed of a CPU, a ROM that stores programs and code tables, a RAM that temporarily stores data, etc. , it is possible to omit the conventionally used run-length counter, and this has the effect of realizing an encoding circuit that is more economical and more reliable than conventional circuits.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an example of a circuit according to the prior art, FIG. 2 is a block diagram showing an embodiment of the present invention,
FIG. 3 is a logic circuit of a change point detection circuit. DESCRIPTION OF SYMBOLS 1... Original reading section, 2... Writing clock switching section, 3a, 3b... Storage section, 4a, 4b... Address selector, 5... Writing address counter, 6
... Read address counter, 7 ... Read data selector, 8 ... Change point detection circuit, 9 ... Run length counter, 10 ... Clock generation circuit, 11
...Control circuit, 12...Modulation section.

Claims (1)

[Claims] 1 A document reading section that scans the original image at a constant speed in the main scanning direction, a memory circuit that temporarily stores the image signal from this document reading section, and a memory circuit that reads the image signal one pixel per scanning line from this memory circuit. an address counter that supplies a read address for outputting the image signal; a change point detection means that detects a change point from white to black and from black to white in the image signal read from the memory circuit; and a control circuit that executes encoding. The control circuit reads the output Qn of the address counter every time a change point detection signal is generated, and reads the output Qn of the address counter when the change point detection signal occurs at the nearest point before that _. Difference from ₁ (Qn−Q _o-1 )
A facsimile encoding circuit that performs run-length encoding.