JPS6329473B2 - - Google Patents

Description

Detailed Description of the Invention The present invention predicts an image signal such as a facsimile signal from an already scanned image signal, and divides the prediction error signal obtained as a prediction result into two groups according to the state of surrounding image signals. The present invention relates to a decoding device that decodes codes that are divided into two parts and coded with different code assignments.

Conventionally, this type of encoding method uses magazine
The paper “Some Extensions of Ordering Techniques” in the October 1978 issue of BSTJ (Vol57, No.8)
for Compression of Two−Level Facsimile
As written on page 3066 of ``Pictures'', there is a decoding device that temporarily stores one line of code in a buffer memory and rearranges the prediction error signal while decoding the code.However, this decoding device However, since the code indicating the dividing point for dividing into two groups is not sent to the receiving side, it is not easy to detect the dividing point and the device is complicated and expensive.

An object of the present invention is to eliminate the above-mentioned drawbacks, and by commonly using a selection signal indicating which prediction error signal has been selected in the encoding device as a code representing the division point of the two groups, one of the synchronization signals By adding the code to the decoder and sending it, the amount of transmitted code does not increase, and in the decoding device, the division point at which the code allocation is switched when decoding the code that has entered the decoder is the point at which the synchronization signal is decoded. It can be easily detected by doing so. Therefore, unlike conventional decoding devices, the decoding device can be separated into three parts: a predictor, an array converter, and a decoder. Moreover, it can be performed with almost the same circuit configuration as the predictor and array converter, so circuit inspection is also possible. A simple and inexpensive device can be provided.

According to the present invention, a plurality of prediction error signals and prediction error signals are generated from an original image, a selection signal for selecting one set of prediction error signals and a prediction state signal from among them is generated, and the selected prediction error signal is predicted. A decoding device that divides into two groups according to a state signal and a selection signal, encodes the divided prediction error signals with separate code assignments, and decodes the code created by the encoding device that simultaneously encodes the selection signal. means for obtaining a selection signal by decoding a received signal; means for decoding a prediction error signal with two types of code assignment according to the selection signal; and means for decoding the prediction error signal according to the prediction state signal according to the decoded prediction error signal. An image signal decoding apparatus is provided, characterized in that it is comprised of means for array-converting the predicted state signal, and means for generating an original image and the prediction state signal from the array-converted prediction error signal.

Next, the present invention will be explained in detail using the drawings. FIG. 2A shows an embodiment of an encoding device that produces codes to be decoded by the decoding device of the present invention. In the figure, a sampled and binarized image signal is applied to terminal 1. Assuming that the sample value of the image signal applied to terminal 1 is X, this sample value X is converted into prediction error signals Y ₁ and Y ₂ and prediction state signals S ₁ and S ₂ in predictors 2 and 2', respectively. . The comparison circuit 3 counts the number of prediction errors in the prediction error signals Y ₁ and Y ₂ and selects the prediction state signal S corresponding to the prediction error signal Y with the least prediction error. The array converter 4 separates the prediction error signal Y into two groups according to the prediction state signal S,
By further converting the array, the prediction error signal is
Y' is data compressed and encoded by an encoder 5, and a compression code C is outputted to an output terminal 5.

FIG. 2B is a block diagram showing an embodiment of the predictor 2 shown in FIG. 2A, and is an example of the configuration for prediction suitable for a character portion using the reference pixels shown in FIG. 1A. In the figure, a sampled and binarized image signal is applied to terminal 1. Letting the sample value applied to terminal 1 be X, this sample value X is supplied to shift register 12b, line memory 11 and exclusive OR gate 15. shift register 12
In b, the signal X is delayed by 2 to 4 samples, and the output terminal has reference pixels g,
Sample values G, H, and I of h and i are obtained. The line memory 11 delays the signal by about one line (equivalent to about 4096 samples), and by further delaying the output of the line memory 11 with the shift register 12a, the output terminals have pixels a, b, c, d, e. , f sample values A, B, C, D, E, and F are obtained. Sample values A, B of the reference pixels obtained in this way,
C, D, E, F, G, H, I are applied as addresses of read-only memories 13 and 13',
At its output terminal there is a predicted value P ₁ and a predicted state signal S
occurs. Predicted value P ₁ is exclusive OR gate 1
5 and the prediction error signal Y ₁ is obtained at the output terminal 16 . The embodiment of the predictor 2' in FIG. 2A has a circuit configuration substantially the same as that in FIG. 2B, and uses the reference pixels in FIG. 1B as reference pixels, and is suitable for predicting halftone photographs.

The prediction signal and prediction state signal used here are determined as follows. The predicted signal is 2 for the reference pixels shown in Figures 1A and 1B.
Value reference pixels a, b, c, d, e, f, g, h,
The probability of occurrence of white or black is determined in advance for all combinations of i, that is, ²⁹ combinations of reference pixels, and the one with the higher probability of occurrence is selected as the prediction error signal. The prediction state signal is a signal used to separate the prediction state signal into two states.Similar to the prediction signal, the prediction error signal has a 5% probability of misprediction for all combinations of ²⁹ reference pixels. When it is above, it is set as state S ₀ , and when it is below 5%, it is set as state S ₁ .

FIG. 2C is a block diagram showing one embodiment of the comparison circuit of FIG. 2A. The prediction error signals Y ₁ and Y ₂ applied to terminals 16 and 16' are predicted by counters 21a and 21b in units of one block (one scanning line of 4096 pixels is divided into four equal parts, and one block has 1024 pixels). The number of blocks is counted and simultaneously input into one block memory 23. Similarly, predicted state signals S ₁ and S ₂ applied to terminals 17 and 17' are input to one block memory 23. 1
Prediction error signal input to block memory 23
Y ₁ , Y ₂ and predicted state signals S ₁ , S ₂ are each 1
It is block delayed and output to multiplexer 24. The outputs of the counters 21a and 21b are compared in blocks by a comparator 22, and a selection signal M for selecting the smaller value is outputted to the multiplexer 24. The multiplexer 24 selects the prediction error signal Y and the corresponding prediction state signal S according to the selection signal M, and outputs them from terminals 25 and 26. At the same time, this selection signal M is output from terminal 27 to the encoder.

FIG. 2D is a block diagram illustrating one embodiment of the array converter 4 of FIG. 2A. First, the prediction error signal Y applied from the terminal 25 is written into the 1-line memory 33a according to the prediction state signal S, and the prediction error signal Y' whose arrangement has been converted according to the prediction state signal S from the 1-line memory 33b is coded. The operation when the data is read into the device 4 will be explained. These operations are performed in units of one scanning line, that is, four blocks. First, multiplexer 34a selects writing counters 35a and 35b by control signal 48, and multiplexer 34a selects writing counters 35a and 35b.
b selects the reading counter 35C by the control signal 47, and the multiplexer 34
C selects the 1-line memory 33b.
Counters 35a, 35b, and 35c are clocked at addresses 0, 4095, and 0, respectively, by a load signal 45 generated by a timing control circuit 36 at the beginning of a block from a clock 41 and a line synchronization 42 (generated in units of 4096 pixels as one scanning line of 4096 pixels). is loaded. When the prediction state signal S input from the terminal 26 is at a high level, that is, when the prediction error signal belongs to the first group, the counter 35a is counted up by the clock 43, and the multiplexer 34a outputs the control signal 50. Therefore, the counter 35a is selected and the prediction error signal Y is sequentially written in the one-line memory 33a from address 0 toward the higher end. When the prediction state signal is at a low level, that is, when the prediction error signal belongs to the second group, the clock 44 controls the counter 3.
5b is counted down and multiplexer 34
a selects the counter 35b and writes the prediction error signal Y in the one-line memory 33a in order from address 4095 toward the lower one. Through these operations, the prediction error signal Y is divided into two groups depending on the level of the prediction state signal S and written into the one-line memory 33a. At this time, the multiplexer 34b selects the readout counter 35C, and the contents of the 1-line memory 33b, that is, the predicted error signal Y' whose arrangement has been converted, is sent from address 0 to address 4095 according to the readout clock 46 of the encoder 5. The signals are sequentially read out and sent to the encoder 5 via the multiplexer 34C. This read operation is
It is performed continuously, and one line memory 33a
and 33b continuously send out the sequence-converted prediction error signal Y' to the encoder 5 by alternately performing read and write operations.

Next, the operation of the run-length encoder used as an example of the encoder 5 in FIG. 2A will be described.
The run-length encoder 5 performs encoding in units of one scanning line (four blocks), and the encoding is performed in the following procedure. First, four blocks of selection signals in block units are combined and added to the synchronization part as a combination code indicating which prediction error signal has been selected in each block unit. Next, the 0 of the prediction error signal Y′ sent from the array converter 4
The first run-length code is used for encoding up to the k-th code, and the second run-length code is used for the k+1st to 4095th codes. The value of k is automatically determined depending on the value of the combined signal, that is, which prediction error signal is selected. In other words, since the number of prediction errors in the prediction error signal Y' is very different between the text portion and the photo portion, the boundary between group 1 and group 2 differs greatly depending on which predictor is selected for each block. Therefore, the boundaries k ₁ and k ₂ of the text area and the photo area are determined in advance for each block. Of the 4-bit selection signal input to the encoder 5, the number m of selected text part prediction error signals and the number n of selected photograph parts are determined respectively, and k is determined by calculating k=mk ₁ + nk _2. is used as the boundary value for one scan line. The above value of k is a value that is much closer to Group 1 than the value obtained by averaging various papers. That is, in group 1, the run length is generally longer than in group 2, and the boundaries are slightly
It has been experimentally confirmed that when the casing is placed on the side, there are fewer runs with mismatched code assignments, resulting in a higher compression ratio.

FIG. 2E is a diagram for explaining the operation of the encoding device shown in FIG. 2A, and shows a case where the number of pixels in one scanning line is 15 for simplicity of explanation. In the prediction error signal Y shown in the figure, the shaded portion represents a prediction mismatch, and the other portion represents a prediction match, and in the prediction state signal S, the shaded portion represents the prediction state of the first group, and the other portion represents the prediction state of the second group. The prediction error signal Y input from the terminal 10 in FIG. 2C is divided into two states by the prediction state signal S input from the terminal 11. In other words, the second
As shown in the prediction error signal Y' in Figure D, when the prediction error signal Y' belongs to the first group, it is arranged from the beginning of the line, and when it belongs to the second group, it is arranged from the end of the line. Ru. The prediction error signal Y' is then divided into two groups by the value of k and encoded using separate run-length codes. Here, if k = 10, the prediction error signal Y' from Y _o,1 to Y _o,13 is the first run-length code, and from Y _o,15 to Y _o,3 is the second run-length code. A code is assigned. In an actual encoder, the period up to prediction mismatch is encoded as one run, so Yn _-1 to Yn _-12 is a run with a run length of 9, and Y _o,13 to Y _o,10 is a run with a run length of 4. As a run, Y _o,7 and Y _o,3 have a run length of 1
Run lengths 9 and 4 are counted as runs of
A run of run length 1 and 1 is assigned a second run length code.

FIG. 3A is a block diagram showing an embodiment of the decoding device of the present invention. In the figure, a compression code C input from a terminal 106 is decoded by a decoder 105. This decoder 105 is a decoder that decodes the prediction error signal Y' encoded by the encoder 5 of FIG. 2A. Next, the prediction error signal Y' is array-converted by the array converter 104 in accordance with the prediction state signal S output from the prediction circuit 103, and is inputted as the prediction error signal Y to the prediction circuit 103. Prediction circuit 10
3, a sample value X of the original image signal is created from the prediction error signal Y and the prediction signal, and at the same time, a prediction error signal S is also created.

FIG. 3B is a block diagram illustrating one embodiment of array converter 104 of FIG. 3A. This array converter 104 is circuit-wise identical to the array converter 4 of FIG. 2A, so the details of its operation will be omitted. The difference in function is that the prediction error signal Y' is input to generate the original prediction error signal Y. That is, the prediction state signal S is sent from the predictor 103, and the prediction error signal S is sent from the decoder 105.
The original prediction error signal by inputting Y′
Y′ is created.

FIG. 3C is a block diagram illustrating one embodiment of prediction circuit 103 of FIG. 3A. In the figure, a predictor 102a is a predictor corresponding to predictor 2 in FIGS. 2A and 2B, and a predictor 102b is a predictor corresponding to predictor 2'. Multiplexer 1
Sample value X of the decoded image signal which is the output of 20
is supplied to the shift register 12b, line memory 11 and predictor 102b. The signal X is delayed by 2 to 4 samples in the shift register 12b, and sample values G, H, and I are obtained at the output terminal. The line memory 11 delays the signal by about one line, and by further delaying the output of the line memory with the shift register 12a, sample values A, B, C, D, E, and F are obtained at the output terminals. Sample values A, B, C, D obtained in this way,
E, F, G, H, I are read only Memory 13
and 13', and generates a predicted value P ₁ and a predicted state signal S ₁ at its output terminal. The predicted value P ₁ is exclusive ORed with the prediction error signal Y by the exclusive OR gate 15, and the sample value X ₁ is obtained.
is obtained. The predictor 102b also generates the sample value X ₂ and predicted state signal S ₂ in a similar manner. The multiplexer 120 selects 1 according to the selection signal M applied to the terminal 118 (which signal is obtained by decoding the synchronous part in the decoder 105).
Sample values X and predicted state signals S are selected in block units and output from terminals 101 and 117.

Although the embodiments of the present invention have been described above, these embodiments do not impose any limitations on the present invention.
In other words, although the block length is fixed in this embodiment, it is of course possible to make it variable, and it is also possible to use other methods for rearranging the blocks. Of course, the conversion and encoding can be done with one block instead of multiple blocks.

As described above, the decoding device of the present invention easily detects the dividing point on the decoding device side by adding a selection code representing the dividing point to the synchronization signal and sending it. Unlike the prediction device, the predictor
It can be separated into three parts: the array transformer and the decoder, and the predictor and array transformer are the predictor of the encoding device,
It can be done with almost the same circuit configuration as the array converter, so
A simple and inexpensive device for circuit inspection can be provided.

[Brief explanation of the drawing]

FIG. 1A is a diagram showing the arrangement of reference pixels used for predicting the character part, FIG. 1B is a diagram showing the arrangement of reference pixels used for predicting the photograph part, and FIG. 2A is a diagram showing the arrangement of reference pixels used for predicting the photograph part. FIG. 2B is a diagram showing an embodiment of the predictor shown in FIG. 2A; FIG. 2C is a diagram showing an embodiment of the comparison circuit shown in FIG. 2A; FIG. 2D is a diagram showing an embodiment of the array converter of FIG. 2A, FIG. 2E is a diagram for explaining the operation of the encoder, and FIG. 3A is a diagram showing an embodiment of the decoding device of the present invention. FIG. 3B is a diagram showing an embodiment of the array converter of FIG. 3A.
FIG. C is a diagram showing an embodiment of the prediction circuit of FIG. 3A. In the figure, 2, 2', 102a, 102b are predictors, 103' is a prediction circuit, 3 is a comparison circuit, 4,
104 is an array conversion circuit, 5 is an encoder, 105 is a decoder, 11 is a line memory, 12a, 12b are shift registers, 13, 13' are read-only memories, 15 is an exclusive OR gate, 21a, 21
b is a counter, 22 is a comparator, 23 is 1 block memory, 24 is a multiplexer, 33a, 33b
34a, 34b, 34c are multiplexers, 35a, 35b, 35c are counters, 36 is a timing control circuit, and 120 is a multiplexer.

Claims (1)

[Claims] 1 Create a plurality of prediction error signals and prediction state signals from the original image, generate a selection signal for selecting one set of prediction error signals and prediction state signals from among them, and select the selected prediction error signal as the prediction state signal. The received signal is divided into two groups according to the signal, and the divided prediction error signals are encoded with different code assignments, and the received signal is decoded by the decoding device that decodes the code created by the encoding device that simultaneously encodes the selected signal. means for obtaining a selection signal by decoding the
means for decoding the prediction error signal with two types of code assignment according to the selection signal; means for array-converting the decoded prediction error signal according to the prediction state signal; An image signal decoding device comprising an original image and means for generating the predicted state signal.