JPS6364949B2 - - Google Patents

Description

[Detailed description of the invention]

The present invention relates to a multi-value image signal encoding device that significantly reduces the amount of information required for transmitting or storing a multi-value image through encoding, and a multi-value image signal decoding device paired therewith. Predictive encoding is an effective encoding method for multilevel image signals. This is the image signal S that has already been input.
(hereinafter simply referred to as S or reference image signal) predicts the currently input image signal and generates an error signal g.
=x^-x^ (x is the predicted signal of x). Conventionally, a linear prediction method based on a linear combination of S has often been used for x^. For example, when 4 pixels a, b, c, and d in FIG. 1 are used as S, the linear prediction method is x^=m ₁ ·a+m ₂ ·b+m ₃ ·c+m ₄ ·d. Here, m ₁ , m ₂ , m ₃ , and m ₄ are coefficients, and their magnitudes indicate the strength of the correlation of each pixel with x^. Further, in FIG. 1, the dotted line indicates the main scanning line of the image, along which the image is scanned from left to right, and when the right end is reached, scanning continues from the left end of the main scanning line below. The images are photoelectrically converted into image signals in scanning order and applied to an encoding device. The linear prediction method has been widely used due to its simple structure, but in order to make more effective predictions, it is necessary to
Furthermore, it is necessary to examine the level of the reference image signal in detail and make non-linear predictions without being limited to linear ones. Considering this, an efficient prediction method is to determine the optimal prediction signal x^ for each S and write it into memory. This will be referred to as prediction method A hereinafter. According to this prediction method A, the state of S is examined in detail to determine x, so the accuracy is higher than that of the linear prediction method. When S consists of 4 pixels a, b, c, and d in FIG. 1, and each pixel is an 8-level signal, the predictive encoding circuit based on prediction method A is as shown in FIG. In Figure 2, the multivalued image signal is 3 per pixel.
It is expressed in bits and input to a 3 (1+2) bit shift register 10. Here, l is the number of pixels per main scanning line. Already input pixel a,
b, c, d (3 bits per pixel) are for prediction
Added to ROM11 as address data,
Based on this, the ROM 11 outputs the prediction signal x^ of the input pixel x as data. The exclusive OR circuits 12, 13, and 14 take the exclusive OR of x (3 bits) and x^ (3 bits), and obtain the prediction error signal g=
Outputs (g ₁ , g ₂ , g ₃ ) (3 bits). here g ₁
is the MSB and _g3 is the LSB. There is also a method of setting g=x-x^, but this method is avoided here because it requires a sign bit to indicate the sign of g. Although there are various methods for encoding the prediction error signal g, one-dimensional run-length encoding method, which is widely used for encoding black-and-white binary facsimile image signals, may be used. This encodes the length of a white pixel (white run) and the length of a black pixel (black run), but when applied to a prediction error signal, it encodes the length of a prediction error signal and the length of a prediction. Considering that the length of the error continues to be encoded, in the example shown in Figure 2, each bit of the prediction error signal is encoded.
Each of g ₁ , g ₂ , and g ₃ may be one-dimensional run-length encoded. The advantage of using one-dimensional run-length encoding is that you can encode multi-value image signals by using a binary image signal encoder already installed in a facsimile, etc., and switching only the predictor to use for multi-value image signals. There is. If the number of 0's in each signal sequence g _i (i=1 to 3) is always greater than 1, efficient data compression can be performed by one-dimensional encoding. However, g _i (i=1 to 3) generated in the predictive encoding circuit of FIG. 2 does not always have such a property. Let me explain this with a concrete example. Under the condition that the reference image signal is S, the next input image signal is x
(0 to 7), that is, the conditional probability of x with respect to S is expressed as P(x|S). S=(a,
b, c, d) are S ₁ (4, 3, 4, 5) and S ₂ =
P(x|S) when (2, 7, 6, 1) is shown in Tables 1 and 3. FIGS. 3 and 4 are graphs of P(x|S ₁ ) in Table 1 and P(x|S ₂ ) in Table 3. When S=S ₁ , P(x|S) shows a unimodal distribution centered on level 4 as shown in Figure 3, so
It is appropriate to set x^=4. When S=S ₂ , P
(x|S) is level 2 and level 6 as shown in Figure 4.
Since it is a bimodal distribution with two peaks, it is difficult to determine x^, but let's take the midpoint between them and set x^ = 4. g = (g ₁ , g ₂ , g ₃ ) is determined by the exclusive OR of x and x^, but it is expressed as P in Tables 1 and 3.
It is shown in the column below (x|S). From Tables 1 and 3, the probability that g _i (i=1 to 3) is 0 can be calculated.
For example, when S = S ₂ , the probability that g ₁ = 0 is P (g ₁ =
O | S ₂ ) is P where g ₁ = 0 in Table 3.
Find the sum of (x|S ₂ ) and P(g ₁ =0|S ₂ )=P(x=4|S ₂ )+P(x=5|
S ₂ ) + P (x = 6 | S ₂ ) + P (x = 7 | S ₂ ) = 0.05 + 0.1 + 0.25 + 0.1 = 0.
It is found as 5. The probability that g ₂ =0 and g ₃ =0 can be similarly determined from the sum of the corresponding P(x|S). g _i (i=1~3) is 1

【table】

【table】

【table】

[Table] A certain probability can be found by subtracting the probability that g _i is 0 from 1. P (g _i = 1 | S) = 1 - P (g _i = 0 | S) S = P obtained in this way for S ₁ and S ₂
(g _i |S) are shown in Tables 2 and 4. S=S ₁
As shown in Table 2, when , the probability that g ₁ is 0 is the highest, and the probability that g ₂ and g ₃ are 0 decreases in this order.
On the other hand, when S=S ₂ , as shown in Table 4, g ₃ has the highest probability of being 0, g ₁ has an evenly split probability of being 0 and 1, and g ₂ has a higher probability of being 1 than 0. . For S=S _1, where the distribution of P(x|S) is unimodal, the probability that g ₁ is 0 is high, and the probability that g ₁ is 0 decreases in the order of g 2 and g ₃ , and the expected g _i However, for S=S ₂ , where the distribution of P(x|S) is bimodal, the probability that g ₂ is 1 is higher than 0, and its stochastic property was expected. It is not suitable for one-dimensional run-length encoding. An object of the present invention is to improve the method of generating a prediction error signal, generate a prediction error signal that is compatible with one-dimensional run-length encoding, and use one-dimensional run-length encoders that have already been developed for binary image signals. The purpose of this invention is to provide a multilevel image signal encoding/decoding method that makes it possible to effectively encode a prediction error signal using an encoder having almost the same configuration as the above. According to the present invention, the order in which the actual signal value of the next input image signal x matches the predicted value is detected based on the already input image signal S, and a plurality of prediction values corresponding to the order are detected. generating a prediction error signal and predictively encoding the image signal x; generating a mode signal indicating a high probability that each of the prediction error signals is 0 based on S and the compression-encoded prediction error signal; A multilevel image signal encoding method that compresses and encodes each prediction error signal after grouping it based on each mode signal corresponding to it, and an image signal S that has already been decompressed and predictively decoded and a prediction error signal that has been decompressed and decoded. A multi-level image signal decoding system that generates a mode signal based on the prediction error signal, expands and decodes the prediction error signal corresponding to the mode signal from the compression code, and comprises S and a multilevel image signal decoding method that predictively decodes the image signal An encoding/decoding scheme for value image signals is obtained. Furthermore, according to the present invention, based on the already input image signal S of N (2 ^n-1 <N2n) values, N signal values for predicting the next input image signal x are arranged in order of prediction accuracy. means for arranging, means for detecting the order in which the actual signal value of the image signal x matches among the arranged signal values, and at most n prediction error signals e _i (corresponding to the order); 1i
n) for predictively encoding the image signal _{x ;}
= 1, it occurs based only on S, and 2in
When S and i-1 prediction error signals e _j (1
ji-1); and means for compressing and encoding each of the prediction error signals e _i (1in) after grouping them based on the corresponding mode signals M _i (1in). The encoding device generates a mode signal M1 based on the N (2 ^n-1 < N2n) value image signal S that has already been expanded and predictively decoded, and compresses _the prediction error signal _e1 corresponding to the mode signal _M1 . means for decompressing and decoding the mode signal M _i from S and i-1 prediction error signals e _j (1j
means for decompressing and decoding the prediction error signal e _i compressed code generated based on the mode signal M _i based on S and at most n prediction error signals e _i (1i
A multi-value image signal decoding device that is paired with the above-mentioned multi-value image signal coding device is obtained, which has means for predictively decoding the N-value image signal x based on n). The present invention will be explained in detail below using the drawings. FIG. 5 is a block diagram of a device showing a concrete example of the encoding method of the present invention. The predictive encoding circuit 2 inputs a multi-value image signal 1 (n bits, N values, where 2 ^n-1 <N2 ⁿ ) obtained by photoelectrically converting a multi-value image, and converts the currently input image based on S. The signal is predicted and the prediction error signal 3 is sent to the encoding circuit 4. The prediction error encoding circuit 4 compresses and encodes the prediction error signal 3 and outputs it as a prediction error encoded signal 5. The control circuit 6 sends out clock signals, control signals, and synchronization signals to control each circuit. 8 values (0~
FIG. 6 shows an example of the predictive encoding circuit 2 for the multivalued image signal (3 bits per pixel) in 7). To simplify the explanation, in this example, it is assumed that the image signal S used for prediction consists of the four pixels a, b, c, and d shown in FIG. Also, each pixel is represented by 3 bits, and levels 0, 1, ..., 7 are (0, 0, 0), (0,
0,1), ..., (1,1,1). Of course, by expanding this example, it is easy to construct a circuit for S consisting of a large number of pixels and a multivalued image signal having an even larger number of levels. In this predictive encoding circuit 2, as shown in FIG.
The signal is input to the bit shift register 7. Here, l represents the number of pixels per main scanning line. Ranking determination
ROM8 is a, b, c, d4 from shift register 7
Pixels (3 bits for each pixel) are input as address data, and based on that, the level with the highest probability of matching with the next pixel x of a is α ₁ (3 bits), and the level with the next highest probability of matching is α ₂ ( 3 bits), similarly x
α ₃ , α ₄ , α ₅ , α 6 , α ₇ , α 3 , α 4 , α ₅ , α 6 , α 7 ,
Define α ₈ (3 bits each) and data (3 x 8 bits)
Output as . The rank signal selection circuit 9 selects α _i (i
=1 to 8) and x are input, α _ix that matches x is detected, i _x −1 is expressed in 3 bits, and output as e ₁ , e ₂ , and e ₃ . Hereinafter, e _i will be referred to as the i-th bit prediction error signal. In this way, the prediction error signal e _i (i=1 to 3)
, the probability that each e _i is always 0 is higher than the probability that it is 1, and each e _i becomes a signal suitable for one-dimensional run-length encoding. The prediction method of the present invention is hereinafter referred to as prediction method B. Specifically, S is S ₁ = (4,
3, 4, 5) and S ₂ = (2, 7, 6, 1), the distribution of P = (x | S) is unimodal in Figure 3 and bimodal in Figure 4. Let me explain it to you. As shown in Tables 5 and 8, S=S _j (j=1,
α ₁ (i=1 to 8) for S _j is determined by the ranking determination ROM 8 based on 2). As the number i increases, P(α _i | S _j ) (j=1, 2)

【table】

【table】

【table】

【table】

【table】

【table】

[Table] α _i is determined so that . here,
P(α _i |S _j ) is the conditional probability that x=α _i under the condition that the reference image signal S=S _j . When x is expected to occur with exactly the same probability for two or more levels, the higher level is associated with a smaller subscript number α _i . Ranking determined when S=S ₁ and S ₂
As shown in Tables 5 and 8, ROM8 has α _i (i
=1 to 8), and the selection circuit 9 outputs them and x
As shown in Tables 6 and 9, e=(e ₁ , e ₂ ,
_e3 ). For example, when S=S ₁ and x=5, as shown in Table 5, the second largest conditional probability P
Since x matches α ₂ =5 with (α ₂ |S ₁ )=0.20, e=i _x −1=2−1=1 as shown in Table 6.
(0, 0, 1) is selected as the prediction error signal by the selection circuit 9
It is output from In the case of prediction method A _, each bit e _i (i ₌ 1~
3) is 0 or 1, P(e _i | S _j )(i=
1 to 3, j=1, 2), Table 6 shows S=S ₁ , S ₂ for prediction method B of the present invention,
From Table 9, the probability that each bit e _i (i = 1 to 3) of e is 0 or 1 is P (e _i | S _j ) (i = 1 to 3, j
=1,2) can be calculated and the results are shown in Tables 7 and 10. In Tables 7 and 10, each e _i (i=1
~3) is suitable for one-dimensional run-length encoding because the probability that it becomes 0 is always higher than the probability that it becomes 1. This is a result of using prediction method B of the present invention, and as already explained, such a property does not always exist for g _i of prediction method A. Why e _i (i=1 to 3) in prediction method B of the present invention has such a property will be explained below using the case of S=S ₂ as an example. When a, b, c1 = S = S ₂ in Figure 7, x = α _i
becomes. The probability P=(α _i |S ₂ ) (i=1 to 8) is graphically displayed with α _i on the horizontal axis. Graphs a, b, and c are all the same, but the diagonal lines are drawn differently. The meaning of the shaded portion will be explained later. S in Figure 4
Probability of occurrence of x when = S ₂ P (x | S ₂ ) (x =
0 to 7) are graphed with x as the horizontal axis, but Figure 7 a, b, and c are the results of rearranging P(x|S ₂ ) in Figure 4 by moving it to the left in descending order of magnitude. be. P
(x|S ₂ ) had a bimodal distribution, but P(α _i |S ₂ )
The distribution is rearranged from left to right in descending order of magnitude, resulting in a descending distribution to the right. As is clear from the method of creation, no matter what type of distribution P(x|S) is, P(α _i | S) is generally monotonically decreasing with respect to the index i of α _i , and P(α _i | S)
has a downward-sloping distribution. The explanation is given using the case of S=S ₂ as an example, but the following explanation is based only on the fact that P(α _i | S) has a downward-sloping distribution, so it holds true for the general case of S. do. Therefore, the shaded area (x=α ₁ to α ₄ , e=0 _{to 3} , corresponding to e ₁ =0) in FIG.
~7, which corresponds to e ₁ =0), so the probability of e ₁ =0 is higher than the probability of e ₁ =1, as shown in FIG. 7d. Similarly, the shaded area in Fig. 7b (x=α ₁ , α ₂ ,
α ₅ , α ₆ , e=0, 1, 4, 5, corresponding to e ₂ = 0) are the blank parts (x=α ₃ , α ₄ , α ₇ , α ₈ , e=2,
3, 6, 7, equivalent to e ₂ = 1), so
The probability of e ₂ =0 is higher than the probability of e ₂ =1. Furthermore, the shaded area in FIG. 7c (x=α ₁ , α ₃ , α ₅ , α ₇ , e=0,
2, 4, 6 (equivalent to e ₃ = 0) are blank parts (x
= α ₂ , α ₄ , α ₆ , α ₈ , e=1, 3, 5, 7, i.e.
e ₃ = 1), so the probability of e ₃ = 0 is e ₃ =
The probability is higher than 1. As described above, it has been found that according to the prediction method B of the present invention, the probability that each bit e _i (i=1 to 3) of the prediction error signal e is always 0 is higher than the probability that it is 1. d, e, and f in FIG. 7 will be explained later. The method for generating the error signals e ₁ , e ₂ , e ₃ has been explained above, but next, the method for generating the first, second, third mode signals M ₁ ,
Let's explain how M ₂ and M ₃ are generated. Up until now, we have considered the probabilities regarding e ₁ , e ₂ , and e ₃ based only on the reference image signal S, but from now on, we will consider e ₁ in addition to S for e ₂ , and S for e ₃ . Besides e ₁ , e ₂
Let's renormalize and think about the condition. These newly devised conditional probabilities are shown in Tables 11 to 13 when S=S ₁ , and Tables 14 to 16 when S=S ₂ . In these tables, P(e ₁ | S _i ), P(e ₂ |
S _i , e ₁ ) and P(e ₃ |S _i , e ₁ , e ₂ ) (i=1, 2) have the following meanings. P(e ₁ |S _i ): Probability that the prediction error signal of the first bit is e ₁ when the reference image signal S is S _i . P(e ₂ |S _i , e ₁ ): probability that the second bit prediction error signal is e ₂ when the reference image signal S is S _i and the first bit prediction error signal is e ₁ . P(e ₃ | S _i , e ₁ , e ₂ ): When the reference image signal S is S _i and the prediction error signal of the first bit is e ₁ and the prediction error signal of the second bit is e ₂ , the third bit The probability that the prediction error signal of is e ₃ . The above probabilities are P(α _i | S ₁ ) and P in Tables 5 and 8.
It is calculated from (α _i |S ₂ ) as follows. P(e ₁ | S _i ): P(0 | S _i ) = ₄ 〓 ^j=1 P(α _j | S _i ) P(1 | S _i )=1−P(0 | S _i ) P(e ₂ ｜S _i , e ₁ : P(e ₃ | S _i , e ₁ , e ₂ ): The conditional probabilities calculated in this manner are illustrated in FIGS. 7d, e, and f for the case of S=S ₂ . Using Figure 7, P(e ₁ | S ₂ ), P(e ₂ | S ₂ , e ₁ ), P(e ₃ |
Let us intuitively explain S ₁ , e ₁ , e ₂ ). P(e ₁ | S ₂ ): P(0 | S ₂ ) is the probability that x will be one of α ₁ , α ₂ , α ₃ , and α ₄ when S=S ₂ . That is, the ratio of the shaded area to the whole in FIG. 7a. P(1|S ₂ ) is expressed as when S=S ₂ and x is α ₅ , α ₆ ,
Probability of either α ₇ or α ₈ . That is, the seventh
In figure a, the proportion of blank space to the whole. P(e ₂ | S ₂ , e ₁ ): P(0 | S ₂ , 0) is when S=S ₂ and x is one of α ₁ , α ₂ , α ₃ , α ₄ Probability of either α ₁ or α ₂ .
That is, the proportion occupied by the shaded area in the left half of the dotted line in Figure 7a. P(1|S ₂ , 0) means that under the same conditions x is α ₃ ,
Probability of either α ₄ . In other words, the proportion of blank space in the same part. P(0|S ₂ , 1) is the probability that x becomes either α ₅ or α ₆ when S=S ₂ and x is α ₅ , α ₆ , α ₇ , or α ₈ . That is, the proportion occupied by the shaded area in the right half of FIG. 7a bordering on the dotted line. P(1|S ₂ , 1) means that under the same conditions x is α ₇ ,
Probability of either α ₈ . In other words, the proportion of blank space in the same part. P(e ₃ | S ₂ , e ₁ , e ₂ ): P(0 | S ₂ , 0, 0) is S=S ₂ and when x is either α 1 or α ₂ , then x is _{α 1} Probability of becoming . In other words, in Figure 7c, the proportion occupied by the shaded area in the part consisting of α ₁ and α ₂ . P(1|S ₂ , 0, 0) is the probability that x becomes α ₂ under the same conditions. In other words, the proportion of blank space in the same part. P(0|S ₂ ,0,1), P(0|S ₂ ,1,
0) and P(0|S ₂ , 1, 1) are the seventh
In figure c, the proportion occupied by the shaded area in the part consisting of α ₃ and α ₄ , α ₅ and α ₆ , α ₇ and α ₈ is P(1 | S ₂ ,
0,1), P(1|S ₂ ,1,0), P(1|
S ₂ , 1, 1) is the percentage of blank space in each part. The mode signal M _i is the conditional probability P(e ₁ | S), P(e ₂ | S, e ₁ ), which has been explained in detail above.
It is defined as follows using P(e ₃ |S, e ₁ , e ₂ ). M ₁ : 0 if P(O|S) is equal to or greater than the given probability P _p , 1 if smaller M ₂ : Is P(0|S, e ₁ ) equal to the given solution probability P _p ? 0 when it is greater than, 1 when it is less than M ₃ : 0 when P(0|S, e ₁ , e ₂ ) is equal to or greater than the given probability P _p , 1 when it is less Tables 17 and 18 show S A list of mode signals M _i when = S ₁ and S ₂ is listed. These are from Table 11.
P _p based on the conditional probabilities in Tables 13 and 14 to 16
=0.7. The method for determining the mode signal M _i includes the conditional probabilities P(e ₁ | S), P(e ₂ |
There is also a method using P(e ₃ |S), but as will be seen later, this method can achieve more efficient encoding.

【table】

【table】

【table】

【table】

【table】

【table】

【table】

【table】

【table】

[Table] Let us return to the predictive encoding circuit 2 in FIG. 6 and continue the explanation. For 1st, 2nd and 3rd mode signal generation in Figure 6
The first, second and third mode signals M ₁ , M ₂ and M ₃ are created by the ROMs 15, 16 and 17, which are based on the method explained in detail above, and M ₁ is
The reference image signal S=(a, b, c,
d), M ₂ is determined by the ROM 16 using the reference image signal S = (a, b, c, d) and e ₁ , and M ₃ is determined by the ROM 17 using the reference image signal S = (a, b , c, d) and e ₁ , e ₂ . P(e ₁ | S), P(e ₂ | S), P(e ₃ | S)
If we decide to determine M ₁ , M ₂ , M ₃ using
e ₁ and e ₂ become unnecessary input data in the ROMs 11 and 12, and although the predictive encoding circuit 2 has a simpler circuit configuration, the encoding efficiency decreases as will be seen later. Although the case of 4-pixel reference with 8 values has been described above, it is generally easy to extend this to the case of m-pixel reference with N (2 ^n-1 <N2 ⁿ ) values. At this time, in the predictive encoding circuit 2 of FIG. 6, the ROM 8 inputs m n-bit pixels as address data, and
α _i (1iN) consisting of bits is output as N pieces of data. The selection circuit 9 inputs α _i (1iN) and x consisting of n bits and outputs at most n 1-bit prediction error signals e _i . The reason why there are at most n pieces here is as follows. For example, assume that x can take on levels 0, 1, . . . , 6 in a 7-value image signal. Since N=7, n=3, and α ₈ is a level that never occurs as x, that is, 7. x= _α8 =
Since it cannot be 7, it is always e≠(1,1,1)
It is. Therefore, when e ₁ =e ₂ =1, e ₃ is always 0, and there is no need to generate the third bit prediction error signal e ₃ at this time. In this way, when N≠2 ^n, it is not necessary to always generate an n-bit prediction error signal. In general, when the value is N (2 ^n-1 < N2 ⁿ ), each e _i
(i=1 to n), and each outputs a mode signal M _i (i=1 to n). The M ₁ determination ROM determines M ₁ using only S, and the M _i determination ROM (i=2 to n) determines M _i using S and e ₁ to _{e i-1} . Next, a compression encoding circuit that encodes the prediction error signal obtained as described above will be explained. Predictive encoding circuit 2 in FIG.
Outputs e ₁ , e ₂ , e ₃ of the predictive encoding circuit 2 shown in the figure
is added to the compression encoding circuit 4 of FIG. If a one-dimensional run-length encoding circuit is used as the compression encoding circuit 4, e ₁ ,
The first idea is to serially connect e ₂ and e ₃ to form a one-dimensional signal sequence and perform run-length encoding. In FIG. 8, e ₁ , e ₂ , and e ₃ are written from left to right in the order of occurrence. As already explained in detail, the probability that e ₁ , e ₂ , and e ₃ will always be 0 is higher than the probability that they will be 1, so data compression is possible even in this case. However, more efficient encoding can be performed using a mode signal indicating a high probability that the prediction error signal becomes 0 (for example, Japanese Patent Application Laid-open No. 79610/1983, calligraphic communication system). The feature is that the prediction accuracy is high when the reference image signal has a certain pattern and low when it is a certain pattern, and the prediction error signal is divided into a group with a high accuracy rate and a group with a low accuracy rate based on the reference image signal. This method divides the data into two groups and performs encoding appropriate for each group to achieve a higher compression rate. If we consider that the prediction accuracy means that each e _i (i=1 to 3) becomes 0, this can be applied to the present invention.
At this time, in addition to the prediction error signals e ₁ , e ₂ , and e ₃ , the predictive encoding circuit 2 shown in FIG.
It is necessary to output M ₁ , M ₂ , and M ₃ . Figure 6
Output data of ROM15, 16, 17 M ₁ , M ₂ ,
M ₃ (1 bit each) is this mode signal, e ₁ ,
It is added to the encoding circuit 4 along with e ₂ and e ₃ . 6th
The point to note in the diagram is that for the second mode signal generation
The ROM 16 uses e ₁ in addition to the reference image signal, and the third mode signal generation ROM 17 uses e ₁ and e ₂ . This is the essential difference between the present invention and conventional binary image signal encoding devices (for example, Japanese Patent Application Laid-open No. 79610/1983, calligraphic communication system). Of course, in the multilevel image signal encoding device, all mode signals may be determined using only the reference image signal as in the conventional binary image signal encoding device, but as will be explained later, the encoding Efficiency decreases.
When using the mode signal in this way, the compression encoding circuit ₄ in FIG.
Considering that the prediction error signal e _i has a high probability of being 0, a relatively short code is generated even for a long 0 run. For the prediction error signal e _i with M _i =1, a long code is generated for a long 0 run, taking into account that the probability of it being 0 is not so high. If a mode signal is not used, e _i with a high probability of being 0 and e _i with a low probability of being 0 are encoded together, but if a mode signal is used, those with a high probability of being 0 and those with a low probability of being 0 are encoded together. It can be separated and efficiently compressed and encoded. FIG. 9 shows a specific example of the coding order of e ₁ , e ₂ , and e ₃ when using a mode signal. In Figure 9, each e _i and M _i are written from left to right in the order of occurrence, e _i surrounded by a solid line corresponds to M _i =0, and e _i surrounded by a dotted line corresponds to M This corresponds to _i =1. The arrows indicate the encoding order of e _i . The first arrow indicates that the e _i 's surrounded by solid lines are serially connected and encoded in the order of their occurrence, and in the case of e _i's that are generated at the same time, in ascending order of numbers, and the second arrow is surrounded by dotted lines. This shows that e _i are serially connected in the same order and encoded. In this way, the second bit prediction error signal e ₂ comes after e ₁ and the third bit prediction error signal e ₃ comes after e ₁ , e ₂
If we decide to encode after e ₂ , the encoding of e ₂ requires not only S but also e ₁ encoded before e 2,
For encoding e ₃ , not only S but also e ₁ and e ₂ encoded prior to e ₃ can be used. Therefore, the mode signal M ₂ that indicates the high probability that e 2 becomes ₀ is determined using not only S but also e ₁ , and the mode signal M ₃ that indicates the high probability that e ₃ becomes 0 is determined only by S. It is more advantageous to decide using e ₁ and e ₂ . For example, when S=S ₁ , S
If each mode signal M _i is determined only by , Table 19 is obtained. This is determined from Table 7 by the boundary probability P _p =
It was calculated as 0.7. As can be seen by comparing this with Table 17, which uses not only S but also e ₁ and e ₂ to determine the mode signal, there is no difference in M ₁ since both are determined only by S, but M ₂ In Table 19, it is 1 regardless of e ₁ , whereas in Table 17, it is 0 when e ₁ is 0, and 1 when it is 1, and it is determined more precisely by dividing the cases. Similarly, M ₃ is in Table 19.
It is 1 regardless of e ₁ and e ₂ , but in Table 17, it is 1 when e ₁ is 0 and e ₂ is 0, 0 when e ₁ is 0, e ₂ is 1, e ₁ is 1, 1 when e ₂ is 0, e ₁ is 1, e ₂ is 1
The value is 1 when It is better to define each M _i more precisely, so that e _i
Since grouping by M _i is more effective and gives higher coding efficiency, not only S but also e _i
Alternatively, it can be seen that e ₂ should be used to determine the mode signals M ₂ and M ₃ . Table 20 shows an example in which each mode signal M _i is determined only by S when S=S ₂ . This was obtained from Table 10 as the boundary probability P _p =0.7. Tables 18 and 20 as in the case of S=S ₁
Please compare the tables. FIG. 10 shows an example of the compression encoding circuit 4 used in the method of the present invention. In this circuit, as shown in FIG. 9, e _i is coded separately into one corresponding to M _i =1 (encircled by a dotted line) and one corresponding to M _i =0 (enclosed by a solid line).
In addition, in this circuit, the "run per prediction+prediction error pixel" is defined as one run, the run length is set as "the length in which e _i =0 continues", and the run length is encoded. It should be noted that when the encoding procedure is determined as described above, one run generally consists of three types of error signals e ₁ , e ₂ , and e ₃ . Roughly speaking, the circuit in Figure 10 consists of two parts: upper and lower; the upper part is a run encoding circuit consisting of e _i corresponding to M _i =1, while the lower part is a run encoding circuit consisting of e _i corresponding to M _i =0. This is a run encoding circuit consisting of . In FIG. 10, e ₁ , e ₂ , e ₃ , M ₁ , M ₂ , and M ₃ are first set in 3-bit registers 38 and 39. The selection circuits 76 and 77 first select one each of e ₁ and M ₁ , then select one each of e ₂ and M ₂ , and finally select one each of e ₃ and M ₃ .
After e ₁ , e ₂ , e ₃ and M ₁ , M ₂ , M ₃ are selected one by one, the next e ₁ , e ₂ , e ₃ and M ₁ , M ₂ , M ₃ are stored in the 3-bit register 38. , 39, and the same operation is repeated. e _i is inverted by the NOT circuit 78, and when M _i =1 (H level), it is added to the counter 83 via the AND circuit 81, and M _i =0.
(L level), it is inverted by the NOT circuit 80.
It is added to the counter 87 via the AND circuit 82. The counter 83 receives the signal from the AND circuit 81 at H level, that is, M _i =1 (H level), e _i =0 (L
count up when level). The run end detection circuit 86 outputs a pulse signal when e _i becomes H level.
After outputting RCS1 and setting the contents of the counter 83 in the run-length code generator 84, the counter 83
Clear. The value set in the run length code generator 84 indicates the length for which e _i corresponding to M _i =0 remains 0, which is the run length to be coded. The run-length code generator 84 generates a run-length code RLC1 corresponding to the set value, and outputs a pulse signal RCE1 after the generation of RLC1 is completed. The input inhibit circuit 57 is a flip-flop which is set by the RCS1 signal and reset by the RCE1 signal, and applies its output signal IHB1 to the registers 38 and 39 through the OR circuit 52. The IHB1 signal is an H level signal when the run-length code generator 84 is outputting the code RLC1,
When it receives INHB at H level, it temporarily stops inputting e _i and M _i during that time. e _i for e _i for M _i =0
, the counter 87, run length code generator 88, run end detection circuit 90, and input inhibit circuit 58 perform similar operations to detect the run of e _i for M _i =1 and determine the run length. encode. Run length code generator 88 generates relatively short codes for long runs compared to code 84 to provide efficient encoding. Run length code generator 8
Run length code RLC0 generated from 4,88,
Care must be taken regarding the output order of RLC1. Simply convert each run-length code into a run-length code generator 8.
If the encoder outputs the signals in the order of occurrence starting from 4 and 88, the decoder will not be able to decode them. In order to be able to decode it, it is necessary to focus on the signal e _i located at the beginning of each run, and generate run length signals for each run in the order in which the leading code is taken in from the prediction circuit, that is, in the order in which each run occurs. . In FIG. 10, the circuit centered on the portion shown to the right of the run-length code generators 84 and 88 controls the output order of the run-length codes. The action is the 11th
Let's explain in detail using the time chart shown in the figure. In Fig. 11, k written at the top row indicates the order in which the prediction error signal e _i and mode signal M _i written below are input, and their order for convenience in the following explanation. . Since the signal is input intermittently, k is not always updated at regular intervals, and the run-length code generator 8
4,88 are not updated during run-length code generation. The signals other than k in FIG. 11 are shown on the circuit of FIG. 10, but each signal will be explained below. e _i and M _i are the output signals of the selection circuits 76 and 77, and COU1 and COU0 are the output signals of the counters 83 and 87 and indicate the respective count values. RCS
1, RCS0 is a pulse signal output from the run end detection circuits 86 and 90 and indicates run detection. R.L.C.
1, RLC0 is run length code generator 84,8
RCE1 and RCE0 are pulse signals indicating the end of generation of run-length codes RLC1 and RLC0 output from run-length code generators 84 and 88, respectively. IHB1 and IHB0 are outputs of the input inhibiting circuits 57 and 58, and are signals indicating that the run-length code generators 84 and 88 are generating run-length codes. REDM is a signal output from the flip-flop 44 indicating that the contents of the code memory 43 are being read. INHB is the output of the OR circuit 52, and when this signal is at H level, the registers 38 and 39 temporarily stop inputting to e ₁ , e ₂ , e ₃ , M ₁ , M ₂ , and M ₃ . SWCH is the output of the switch signal generation circuit 41, and when this signal is at H level,
RLC1 and RLC0 are applied to a selection circuit 46 and a memory 43, respectively, via a switch circuit 42, and when these signals are at L level, the connections are reversed.
RLCE is the output signal of the selection circuit 40 when SWCH is high.
When SWCH is at L level, it is the same as RCE1, and when SWCH is at L level, it is the same as RCE0. RLCD is the output signal of this encoding circuit. When REDM is at H level, the run length code read from the run length code memory 43 is selected by the selection circuit 46 as RLCD.
When REDM is at L level, the run-length code generated from run-length code generator 84 or 88 is directly selected as RLCD by selection circuit 46 without going through memory 43. Although each signal has been roughly explained above, specific changes in each signal will be explained in accordance with the time chart of FIG. 11. In FIG. 11, when k=5, e _i =1 and the end of the run occurs only when e i =1. At this time, M _i =0, so this run is M _i =
It is for 0. The run length is counted by the counter 87 as COU0=2. When k=5, e _i =1, M _i =0, so AND circuit 9
The output of No. 4 is at H level. Run end detection circuit 9
0 receives this and generates ROS0, counter 87
The contents of COU0=2 are converted into run-length code generator 88
Immediately thereafter, the counter 87 is reset. RCS0 also sets the input prohibition circuit 58.
Following IHB0 to H level, INHB is set to H level to temporarily prohibit registers 38 and 39 from inputting prediction error signals e ₁ , e ₂ , e ₃ and mode signals M ₁ , M ₂ , M ₃ . Run length code generator 88 is COU0
Since the run length code RLC0=C2 corresponding to = ₂ is generated and SWCH is at H level, the switch circuit 42
After writing is completed, RCE0 is generated and the input inhibit circuit 58 is reset. What should be noted here is that the run length code C2 generated for the first time is not immediately output as the output signal RLCD of the present encoding circuit, but is temporarily written into the memory 43. This is based on the already mentioned principle of ``outputting run-length codes in the order in which they occur'' in order to make codes decodable. In the example of FIG. 11, when k=1, e _i =
0, M _i =1, a run for M _i =1 occurs first, when k = 2, this run continues for e _i =0, M _i =1, and when k = 3, e _i =0 , M _i =0 and M _i =
When a run for 0 occurs for the first time and k=4, e _i
=0, M _i =0, this run continues, and when k=5, e _i =1, M _i =0, the run for M _i =0 ends with run length 2, and code C2 is generated. That is, at the time of k=5, the run for M _i =1 is continuing without ending, and although it occurs earlier than the run for M _i =0, a run length code for it has not yet been generated. On the other hand, the run for M _i =0 occurred later than the run for M _i =1, but k
= 5 and ended with length 2, so run length code C2 was generated first. Therefore, if C2 is output as RLCD immediately after the generation ends, that code will be output before the run for M _i =0 that occurred earlier, resulting in a code sequence that cannot be decoded. To avoid this, the switch signal generation circuit 41
, counters 83 and 87 are cleared and COU0=
0, in the initial state where COU1=0,
If the mode signal M _i =1, it detects that a run for M _i =1 has occurred before a run for M _i =0, sets SWCH to H level, and activates the switch circuit 42 to select RLC1. RLC0 to 46
is connected to the memory 43, and RLC0 is written to the memory 43 first. Conversely, if M _i =0 in the initial state, it is detected that a run for M _i =0 has occurred before a run for M _i =1, SWCH is set to L level, and the switch circuit 42 is activated. RLC0 to selection circuit 46,
RLC1 is connected to memory 43, and conversely RLC1 is written to memory 43 first. Let's follow the specific signal changes on the time chart again. At k=5, RLC0=C2 was generated and written to the memory 43, but in the same way, at k=7,9, M _i =
The end of a run of length 1 and length 0 for 0 is detected and the corresponding run length code RLC0 = C3,
C4 is written to memory 43. k=1 to 9
Until then, all e _i for M _i =1 are 0, and the run for M _i =1 that occurred when k=1 continues without ending. k=10, and e _i =
1, M _i =1, the end of the run for M _i =1 is detected for the first time, and the content of the counter 83 COU1 =
3 is set in the run length code generator 84, and the counter 83 is reset immediately thereafter. Also
RCS1 sets the input inhibit circuit 57, sets IHB1 to H level, sets INHB to H level, and registers 38 and 39 output prediction error signals e ₁ , e ₂ , e ₃ mode signals.
Temporarily prohibits input of M ₁ , M ₂ , and M ₃ . The run-length code generator 84 generates a run-length code RLC1=C1 corresponding to COU1=3,
Since SWCH is H, RLC1 is connected to the selection circuit 46 via the switch circuit 42, and since REDM is L, the selection circuit 46 selects it and outputs it as the output code RLCD of the encoding circuit. The code C1 for M _i =1 is the code C1, C2 for M _i =0,
Although generated after C3, the run corresponding to the code C1 starts generation when K=1, and is a run that precedes the runs corresponding to codes C2, C3, and C4. Therefore, based on the principle of "outputting run-length codes in the order in which runs occur," code C1 is first output.
Output as RLCD. After the run-length code generation circuit 84 finishes generating the code C1, it outputs RCE1, and since SWCH is at H level, the selection circuit 40 selects RCE1 and outputs it as RLCE.
RLCE sets flip-flop 44 and REDM
is set to H level, and the selection circuit 46 sets it to H level.
After receiving REDM, select memory 43 and its contents C2,
Read out C3 and C4 and get the output code of this encoding circuit.
Output as RLCD. While REDM is at H level
INHB becomes H level and e ₁ , e ₂ , e ₃ , M ₁ , M ₂ ,
Input of _M3 is temporarily prohibited. When all the contents of the memory 43 are read out and become empty, the memory 43 is
MEMP is generated and MEMP is flip-flop 4
4 is reset, REDM is set to L level, and reading from the memory 43 is stopped. When REDM goes to L level, INHB goes to L level, e ₁ , e ₂ , e ₃ ,
Input of M ₁ , M ₂ , and M ₃ is resumed. The switch signal generation circuit 41 inputs MEMP as a trigger signal, and as shown in Table 21, COU1,
A new SWCH signal is output based on COU0, M _i . Let me explain Table 21 in detail. MEMP
The SWCH signal changes when
Immediately after reading RLC0 in the memory 43 and outputting it as RLCD, secondly, after directly outputting RLC0 as RLCD without going through the memory 43, the memory 43
This is immediately after reading RLC1 in the file and outputting it as RLCD. At the first time, counter 83 is RCS
1, COU1=0, and the counter 87 is cleared at the second time.

[Table] Cleared by RCS0, COU0=0, and in any case, when MEMP occurs, COU1, COU0
Either one is 0. COU1=COU0=0
At this time, there is no run being counted by the counters 83 and 87, so the run length code to be output as RLCD is first determined based on M _i . That is, M _i
If = 0, set SWCH to L level and RLC0 first, if M _i = 1, set SWCH to H level and RLC
The switch circuit 42 is set to output 1 first. The deferred run-length code is stored in memory 4.
Once written to 3, the code to be output first is
After being output as RLCD, it will be extracted and output as RLCD. COU1=0, COU0≠
When it is 0, the counter 87 is counting runs for M _i =0, so it is necessary to first output the code corresponding to the run being counted as RLCD.
Therefore, the switch circuit 42 is set to set SWCH to L level and output RLC0 first.
RLC1 is once written to memory 43, and RLC0
After is output as RLCD without going through memory,
It will be read out from the memory 43 and output as RLCD. When COU1≠0 and COU0=0, the counter 83 is counting runs for M _i =1, so it is first necessary to output the code corresponding to the run being counted as RLCD. therefore
The switch circuit 42 is set to set SWCH to H level and output RLC1 first. RLC0 is once written into the memory 43, RLC1 is outputted as RLCD without going through the memory, and then read out from the memory 43 and outputted as RLCD. This concludes the explanation of Table 21. MEMP occurs at k=11, but
Since COU0=COU1=0 and M _i =0, SWCH becomes L level according to Table 21. e _i at k=11
= 1, so the run for M _i =0 ends at the same time as the run length is 0, run length code C5 is generated as RLC0, and SWCH is at L level, so the switch circuit 42 and the selection circuit 4 do not go through the memory 43.
6 and output as RLCD. When the output of the run-length code C5 is finished, the run-length code generator 88 generates RCE0, and the selection circuit 40
Since SWCH is at L level after receiving RCE0, use this
Output as RLCE. The flip-flop 44 is
It is set by RLCE and outputs H level REDM. The selection circuit 46 receives the H level REDM and selects the memory 43 and tries to read its contents, but since nothing is written in the memory 43, it immediately
MEMP is output. The flip-flop 44 is
It is reset by MEPM and REDM goes to L level. The selection circuit 46 receives the L level REDM,
The reading of the memory 43 is stopped and the switch circuit 4
Select output 2. Registers 38 and 39 are
When REDM becomes L, INHB becomes L, so e ₁ ,
Restart input of e ₂ , e ₃ , M ₁ , M ₂ , and M ₃ . In the end, it is only a moment that REDM reaches H level, and there is no particular note on the time chart. k=
12, the switch signal generation circuit 41 is
Upon receiving MEMP, it outputs an H level SWCH based on COU1=COU0=0 and M _i =1 (see Table 21). Since e _i = 1 at k = 12, the run length ends at 0 at the same time as the rung is generated for M _i = 1, and RLC
Run length code C6 is generated as 1.
Since SWCH is at H level, it is output as RLCD through the switch circuit 42 and the selection circuit 46 without going through the memory 43. When the output of the run-length code C6 is finished, the run-length code generator 84 outputs RCE.
1, and the selection circuit 40 receives RCE1.
Since SWCH is at H level, it is output as RLCE. Flip-flop 44 is set by RLCE and outputs REDM at H level. The selection circuit 46 receives the H level REDM and attempts to read the memory 43, but since nothing is written in the memory 43, MEMP is immediately output. Flip-flop 44 is reset by MEMP and REDM
becomes L level. The selection circuit 46 is at L level.
Upon receiving REDM, reading of the memory 43 is stopped,
The output of the switch circuit 42 is selected. register 3
Since INHB becomes L when REDM becomes L, input of e ₁ , e ₂ , e ₃ , M ₁ , M ₂ , and M ₃ is restarted. After all, REDM reaches H level in an instant, and there is no particular note on the time chart.
At k=13, the switch signal generation circuit 41
Upon receiving MEMP, it outputs an H level SWCH based on COU1=COU0=0 and M _i =1 (see Table 21). At k=13, 14, and 15, e _i =0, so no run-length code is generated, but at k=16, e _i =1, M _i =0, and COU0=1, so a run with run length 1 for M _i =0 is generated. Length code C8 is generated as RLC0, and SWCH is at H level, so RLC0
is temporarily written into the memory 43 via the switch circuit 42. When generation of run-length code C8 is completed, run-length encoder 88 generates RCE0, and selection circuit 40 receives RCE0, but since SWCH is at L level, it is not selected and RLCE is not output. At k=17, e _i =0, so no run-length code is generated, but at k=18, e _i =
1. Since M _i = 1 and COU1 = 2, a run length code C7 with a run length of 2 for M _i = 1 is generated as RLC1, and since SWCH is at H level, RLC1 is sent to the switch circuit 42 and the selection circuit 4 without going through the memory 43.
6 and output as RLCD. When the output of the run-length code C7 is finished, the run-length code generator 84 generates RCE1, and the selection circuit 40
SWCH is at H level after receiving RCE1, so use this
Output as RLCE. The flip-flop 44 is
It is set by RLCE and outputs H level REDM. The selection circuit 46 receives the H level REDM, selects the memory 43, reads out its contents C8, and outputs it as the output code RLCD of the main encoding circuit. When the contents of the memory 43 are completely read out and become empty, the memory 43 generates MEMP, which resets the flip-flop 44 and sets REDM to L level to stop reading the memory 43. At k=19, the switch signal generation circuit 41 receives MEMP,
Based on COU1=0, COU0=1 (see Table 21)
Outputs L level SWCH. This is because the run length counter 87 is currently counting the run for M _i =0 that occurred at k=17, so the code corresponding to the run that is being counted is first outputted as the RLCD. For k=19, 20, 21, e _i =0,
Since M _i =1, no run length code is generated and the counter 83 is counted up. At k=21, e _i =0, M _i =1, COU1=2,
The time chart in Fig. 11 ends with COU0 = 1, but at that time M _i = 0 and M _i = 1
The counters 83 and 87 are counting the run lengths for both, and the actual operation continues, but is not shown in FIG. This concludes the explanation of the encoding device,
Next, the decoding device will be explained. FIG. 12 shows a block diagram of a device showing a concrete example of the decoding method of the present invention. In FIG. 12, the decompression decoding circuit 18 inputs the prediction error encoded signal 45, decompresses it, and outputs it as a prediction error signal 47, and the prediction decoding circuit 19 inputs the prediction error signal 47, decodes it predictively, and decodes it. It is output as an image signal 48. It is assumed that the prediction error encoded signal 45 is generated by the encoding device of the present invention which has already been described in detail. The control circuit 20 receives a clock signal,
Controls each circuit by sending out control signals and synchronization signals.
An example of the predictive decoding circuit 19 for an 8-value (0 to 7) multi-value image signal (3 bits per pixel) is shown in the first example.
Shown in Figure 3. To simplify the explanation, in this example, the image signal S used for prediction is the four pixels a, a, and
Suppose it consists of b, c, and d. In addition, each pixel is expressed with 3 bits and levels 0, 1...
...7 is (0,0,0), (0,0,1),...
Assume that it corresponds to (1, 1, 1). Of course, by expanding this example, it is easy to construct a circuit for S consisting of a large number of pixels and a multivalued image signal having an even larger number of levels. In the predictive decoding circuit 19, the already decoded image signal is 3(l+
2) Bits are set in the shift register 28 as shown in FIG. Here, l represents the number of pixels per main running line. 1st mode signal determination
The ROM 23 receives 4 pixels a, b, c, and d (3 bits for each pixel) as address data, and outputs a mode signal M ₁ (1 bit) based on the address data. Mode signal M ₁ is selected by selection circuit 27 and sent to prediction error signal decoding circuit 18 as mode signal M _i . The decompression decoding circuit 18 receives M ₁ , decompresses and decodes the prediction error signal e ₁ corresponding to M ₁ , and applies it to the prediction decoding circuit 19 . The expansion decoding circuit 18 generates a prediction error signal e _i 47 corresponding to the input mode signal M _i
The predictive decoding circuit 19 performs decompression decoding from the compressed code.
Add to. In the prediction decoding circuit 19, the prediction error signal e _i 47 is added as address data to the second mode signal generation ROM 24 together with the already decoded reference image signals a, b, c, d (3 bits each). The ROM 24 generates a second mode signal M ₂ based on this address data and applies it to the selection circuit 27. The selection circuit 27 selects M ₂ and sends it to the expansion decoding circuit 18 as a mode signal M _i . The decompression decoding circuit 18 receives M ₂ and uses the prediction error signal e ₂ corresponding to M ₂ as e _i to generate the prediction decoding circuit 19.
Add to. In the prediction decoding circuit 19, the prediction error signal e ₂ 47 is added to the ROM 25, and until now the ROM
The prediction error signal e ₁ corresponding to the mode signal M ₁ applied to the 1-bit register 21 is set to the 1-bit register 21 . The prediction error signals e ₁ and e ₂ corresponding to M ₁ and M ₂ are added as address data to the third mode signal generation ROM 25 together with the already decoded image signals a, b, c, and d. The ROM 25 generates a third mode signal M ₃ based on this address data and applies it to the selection circuit 27 . The selection circuit 27 selects M ₃ and sends it to the expansion decoding circuit 18 as a mode signal M _i . Decompression decoding circuit 18 receives M ₃ and M ₃
The prediction error signal e ₃ corresponding to is applied to the prediction decoding circuit 19 as e _i . In the prediction decoding circuit 19, the prediction error signal e ₃ 47 is sent to the level signal selection circuit 5.
0 as a control signal, until now ROM25
The prediction error signal e ₂ corresponding to the mode signal M ₂ applied to the register 21 is set to the register 21, and the prediction error signal e ₁ corresponding to the mode signal M ₁ set to the register 21 is set to the register 22. . And the contents e ₁ and e ₂ of registers 21 and 22 are e ₃
Similarly, it is applied as a control signal to the level signal selection circuit 50. As a result, prediction error signals e ₁ , e ₂ , e ₃ corresponding to mode signals M ₁ , M ₂ , M ₃ are applied to the level signal selection circuit 50 as control signals e=(e ₁ , e ₂ , e ₃ ). The ranking determination ROM 26 inputs the decoded image signals a, b, c, d as address data, and outputs the ranked level signals α ₁ , α ₂ , . . .
Eight α ₈ (3 bits each) are outputted and added to the level signal selection circuit 50 as input data. The level signal selection circuit 50 selects α i, that is, α e+1, from among _{α 1} , _{α 2 ,} . and sets it in the register 28 as the decoded image signal x. Here, e is considered to be a binary number with e ₁ as MSB and e ₃ as LSB. When register 28 receives x, it shifts the stored data by one pixel and prepares for the decoding operation of the next pixel. ROMs 23, 24, 2 for generating first, second, and third mode signals of the predictive decoding circuit 19
5. The ranking determination ROM 26 is the first, second, and third mode signal generation ROM 15, 1 of the predictive encoding circuit 2.
6, 17, is exactly the same as ranking determination ROM9. Next, the decompression/decoding circuit 18 will be explained. The prediction error decoding circuit 18 is roughly divided into two parts, upper and lower, as shown in FIG. The upper part
This is a decoding circuit for the prediction error encoded signal corresponding to M _i =1, and the lower part is a decoding circuit for the prediction error encoded signal corresponding to M _i =0. The role of the decompression decoding circuit 18 is to receive the mode signal M _i from the predictive decoding circuit 19 and output the corresponding prediction error signal e _i to the predictive decoding circuit 19, and receives the mode signal where M _i =0. The upper circuit operates, and when it receives a mode signal of M _i =1, the following circuit operates. buffer memory 2
9, the prediction error coded signal RCLD45 is run-length coded and stored, and it is stored as M _i =
When it is 1, it is read out when there is a request from the run-length decoding circuit 31, and when M _i =0, it is read out when there is a request from the run-length decoding circuit 32. The run length decoding circuit 31 has M _i =1
This circuit decodes the prediction error coded signal RLC1 for the input signal RLC1, and receives the decoding start signal RDS1 from the decoding start signal generation circuit 33 and starts its operation. When the run length decoding circuit 31 starts operating, it reads out the prediction error coded signal RLC1 from the buffer memory 29 via the switch circuit 30, decodes it, sets the obtained run length in the counter 35, and outputs the decoding end signal RDE1. Output. Counter 35 is a countdown enable signal
Counts down when ENB1 is H and contents CON1
When becomes 0, the output of the prediction error signal generation circuit 37 is set to H level (“1”). The counter 35 further counts down, and when the content CON1 becomes -1, the decoding start signal generation circuit 33 outputs a pulse signal.
RDS1 is generated to start the operation of the run length decoding circuit again. The flip-flop 67 is set by inputting the decoding start signal RDS1 via the OR circuit 65, and ORing the decoding end signal RDE1.
It is input via circuit 66 and reset. At this time, the output DECD of the flip-flop 67 indicates that the run-length decoding circuit 31 is in the decoding operation. The delay circuit 68 delays the DECD signal by one clock and outputs the delayed signal. Delay circuit 68
The output of is inverted by NOT circuit 68 and output as countdown enable signal ENB to AND circuit 6
Add to 1,62. ENB, M _i is H level (“1”)
At this time, ENB1 becomes H level and the counter 35 counts down. When ENB is at the H level and M _i is at the L level (“0”), ENB0 goes to the H level and the counter 36 counts down. The circuit at the bottom of FIG. 14 decodes the prediction error coded signal RLC0 for M _i =0. The signals RDS0, RDE0, CON0, ENB0, the run length decoding circuit 32, the counter 36, the decoding start signal generating circuit 34, and the prediction error signal generating circuit 60 are the signals in the circuit for M _i =1.
RDS1, RDE1, CON1, ENB1, run length decoding circuit 31, counter 35, decoding start signal generation circuit 33, prediction error signal generation circuit 37
It works in the same way. Following the time chart of FIG. 15, the prediction error decoding circuit 19 of FIG.
Explain the operation. In Fig. 15, k written on the top row is the mode signal written below it.
Indicates the order in which M _i was input. The prediction error signal e _i corresponding to the mode signal M _i is k=2,
There are times when M _i is output immediately after input, such as when k=1, 3, 6, etc., but there are times when it is output after waiting for a while, as when k=1, 3, 6, etc. The x mark in the e _i column indicates the e _i output waiting time, during which the run length decoder 31 or 32 operates and the run length code of e _i corresponding to the input M _i is decoded. No waiting time
When e _i is output, the run-length code corresponding to e _i has already been decoded. The prediction error decoding circuit 19 starts operating when k=1. At the start of operation, ENB is at H level,
DECD is the content of L level counters 35 and 36
CON1 and CON0 are initialized to 0. At the start of operation, since ENB is at H level, M _i
When = 1, ENB1 becomes H level and the counter 35 counts down, and when M _i = 0,
ENB0 becomes H level and the counter 36 counts down. In Figure 15, when k=1, M _i
=1, so the counter 35 counts down and its content CON1 becomes -1. Since CON1 is -1, the decoding start signal generating circuit 33 issues the signal RDS1 to start the operation of the run length decoding circuit 31. Further, RDS1 sets the flip-flop 67 via the OR circuit 65 and sets the signal DECD to H level. The run-length decoding circuit 31 starts operating, inputs the run-length code C1 as RLC1 from the buffer memory via the switch circuit 30, and decodes it. When the run-length decoding circuit 31 finishes decoding the run-length code C1, it sets the result in the counter 35 and issues a signal RDE1.
The flip-flop 68 is reset via the OR circuit 66, and the signal DECD is brought to L level to notify the end of decoding. The prediction error signal generation circuit 37 receives the decoding result "3" of C1 set in the counter 35 as a signal CON1, generates a signal e _i (1)=0, and outputs the signal e i (1)=0 via the selection circuit 64 as the prediction error signal e _i Output as . Run length decoding circuit 31 is operating
The DECD signal is at H level. And since the ENB signal is at L level one clock later,
The decoding result is set in the counter 35 from one clock after the run-length decoding circuit 31 starts operating until e _i is output based on the decoding result, that is, until the next mode signal M _i is input. countdown is prohibited. In addition,
The clock signal is indicated as CLK at the bottom of FIG. 15, and this decompression/decoding circuit operates in synchronization with CLK. This concludes the explanation when k=1, and then begins the explanation when k=2. In Figure 15, k=
2, M _i = 1, ENB is H level, so ENB1
is at H level, the counter 35 counts down and its content CON1 becomes 2. CON1 is 2
Therefore, the prediction error signal generation circuit 37 generates a signal e _i (1)=0 and outputs this via the selection circuit 64 as the prediction error signal e _i . When k=1, there was a waiting time for the output of e _i during the operation of the run-length decoding circuit 31 after inputting the mode signal M _i (during 3 clocks in FIG. 15), but when k=2, Even if the run length decoding circuit 31 or 32 does not operate, the counter 35
The prediction error signal e _i
can occur immediately and there is no need for waiting time. This concludes the explanation for k=2, and then begins the explanation for k=3. When k=3, M _i =0, ENB is H
Because of the level, ENB2 is at H level, the counter 36 is counted down, and its contents CON0
becomes -1. Since CON0 is -1, the decoding start signal generating circuit 34 generates the signal RDS0 and starts the operation of the run length decoding circuit 32. Further, RDS0 sets the flip-flop 67 via the OR circuit 65 and sets the signal DECD to H level. The run-length decoding circuit 32 starts operating, inputs the run-length code C2 as RLC0 from the buffer memory via the switch circuit 30, and decodes it. When the run-length decoding circuit 32 finishes decoding the run-length code C2, it sets the result in the counter 36, emits the signal RDE0, resets the flip-flop 68 via the OR circuit 66, and sets the signal DECD to L level to notify the end of decoding. . The prediction error signal generation circuit 60 generates a signal when the decoding result "2" of C2 is set in the counter 36.
A received signal e _i (0)=0 is generated as CON0, and this is outputted as a prediction error signal e _i via the selection circuit 64. Run length decoding circuit 32 is operating
The DECD signal is at H level. And since the ENB signal is at L level one clock later,
One clock after the run-length decoding circuit 32 starts operating, the decoding result is set in the counter 36, and based on it, the counter 35 counts down until e _i is output, that is, until the next mode signal M _i is input. is prohibited. Above, k=
This concludes the explanation for step 3. The same operation continues for k=4 to 21, and the run length code C3
, C10 is decoded and a prediction error signal e _i corresponding to each mode signal M _i is generated. In the multilevel image signal encoding device of the present invention, the operation of the compression encoding circuit 4 of FIG. 10 will be explained with reference to the time chart of FIG. It was assumed that it would occur. The operation of the decompression decoding circuit 18 in FIG. 14 has been explained using the time chart in FIG. 15. At that time, the run-length codes C1, C2, .
They are exactly the same as C1, C2, . . . , C8 in the figure. As a result, C1, C2,... shown in FIG.
..., C8 decoding result e _i is shown in FIG _.
This shows that the decompression/decoding circuit 18 is operating correctly. This concludes the explanation of the decompression decoding circuit 18, and also the explanation of the multilevel image signal decoding apparatus of the present invention. Although we have explained the case where both the encoding device and the decoding device are 8-level image signals, N(2 ^n-1
It is easy to extend this to the case of image signals with values <N2 ⁿ ). In the case of N (2 ^n-1 < N2 ⁿ ) values, the prediction error signal e is n of e ₁ , e ₂ , ..., e _o (1 bit each).
The method of connecting e _i and the definition of run are the same as in the case of 8 values. As described in detail above, according to the encoding device and decoding device of the present invention, it is possible to efficiently encode and decode a multilevel image signal using a run-length encoder and a decoder.

[Brief explanation of drawings]

Figure 1 is a diagram showing the positional relationship between a reference pixel and a predicted pixel, Figure 2 is a predictive coding circuit diagram using a conventional prediction method, and Figures 3, 4, and 7 are image signal conditions. FIG. 5 is a block diagram of a device showing a specific example of the encoding method of the present invention, and FIG. 6 is a predictive encoding used in the encoding method of the present invention. Block diagram showing one example of the circuit, No. 8
9 is a diagram explaining the coding order of prediction error signals, and FIG. 10 is a block diagram showing an example of a compression encoding circuit used in the encoding method of the present invention.
Fig. 1 is a time chart of the prediction error encoding circuit of Fig. 10, Fig. 12 is a block diagram of a device showing a concrete example of the decoding method of the present invention, and Fig. 13 is a time chart of the prediction error encoding circuit of Fig. 10. FIG. 14 is a block diagram showing an example of a prediction error decoding circuit used in the decoding method of the present invention. FIG. 15 is a block diagram showing an example of the prediction error decoding circuit used in the decoding method of the present invention. FIG. 2 is a block diagram showing an example of a decoding circuit. In the figure, 1, 48...multivalued image signal, 2...prediction encoding circuit, 3, 47...prediction error signal, 4...compression encoding circuit, 5, 45...encoded prediction error signal,
6, 20...control circuit, 7, 10, 28...3(l+
2) Bit shift register, 8, 26...ROM for ranking determination, 9...rank signal selection circuit, 11...ROM for predicting signal determination, 12, 13, 14...exclusive OR circuit, 15, 23...first mode signal For decision
ROM, 16, 24...For determining second mode signal
ROM, 17, 25...For determining the third mode signal
ROM, 18... Decompression decoding circuit, 19... Prediction decoding circuit, 21, 22... 1 bit register, 27,
40, 46, 76, 77...selection circuit, 31, 32
...Run length decoding circuit, 29...Buffer memory, 35, 36, 83, 87...Counter, 33,
34... Run-length decoding circuit start signal generator, 30, 42... Switch circuit, 37, 60... Prediction error signal generation circuit, 38, 39... 3-bit register, 41... Switch signal generation circuit, 43... Run-length code memo ri, 44, 57, 58, 67...
Flip-flop, 50...Level selection circuit, 5
2, 65, 66...OR circuit, 61, 62, 81,
82, 93, 94...AND circuit, 63, 69, 7
8,79,80...NOT circuit, 68...Delay circuit, 86,90...Run end detection circuit, 84,88
...run-length code generator.

Claims (1)

[Claims] 1. Detecting the order in which the actual signal value of the next input image signal x matches the predicted value based on the already input image signal S, and detecting the order corresponding to the order. The image signal x is predictively encoded by generating a plurality of prediction error signals, and each prediction error signal is 0.
A mode signal indicating a high probability of is generated based on S and a compression-encoded prediction error signal, and each prediction error signal is compressed and encoded after being grouped based on the corresponding mode signal. A mode signal is generated based on the image signal encoding method, the image signal S that has already been expanded and predictively decoded, and the expansion and decoded prediction error signal, and the prediction error signal corresponding to the mode signal is expanded and decoded from the compression code, and S and the image signal x based on multiple prediction error signals
1. A multi-value image signal encoding and decoding method comprising: a multi-value image signal decoding method that performs predictive decoding. 2. Means for arranging N signal values for predicting the next input image signal x based on the already input image signal S of N (2 ^n-1 <N2 ⁿ ) values in order of prediction accuracy; means for detecting the order in which the actual signal value of the signal x matches among the arranged signal values; and generating at most n prediction error signals e _i (1in) corresponding to the order. means for predictively encoding _{said image} signal , 2in, means for generating based on S and i-1 prediction error signals e _j (1ji-1), and each prediction error signal e _i (1in)
and the corresponding mode signal M _i (1in)
1. A multivalued image signal encoding device comprising means for compressing and encoding after grouping based on. 3 N (2 ^n-1 <
Based on the image signal S of N2 ⁿ ) value, the mode signal M ₁ ,
means for decoding and decoding a prediction error signal e ₁ corresponding to the mode signal M ₁ from the compressed code, and when _i is 2 or more and at most n, the mode signal M means for expanding and decoding a prediction error signal e _i generated based on the signal e _j (1ji-1) and corresponding to the mode signal M _i from a compressed code;
and means for predictively decoding an N-valued image signal x based on at most n prediction error signals e _i (1 inch).