JP2001094793A - Electronic sort contorl method in digital copying machine - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce a first copy processing time in the case of electronic sort copying state with a simple configuration and simple control because complicated time division control can be avoided through the use of one coder. SOLUTION: Image data are transferred respectively to a 1st line memory 20 or a page memory 22 according to a DDMA 1. The image data are transferred respectively from the 1st line memory 20 or the page memory 22 to a rotation processing circuit 24 according to a DDMA 2. Output image data from the rotation processing circuit 24 are transferred to a 2nd line memory 38 according to an SDMA 1. In the case of a first copy, an SDMA 2 gives the image data from the 2nd line memory 38 to a print engine 48 and an SDMA 3 gives the image data to a QM coder 42. In the case of 2nd and succeeding copies, the coded image data according to a DDMA 3 are read from a code memory 44 and decoded by the QM coder 42 and written in the 2nd line memory according to the SDMA 3.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an electronic sort control method for a digital copying apparatus, and more particularly, to a so-called electronic sort function for temporarily encoding image data, storing it in a memory, decoding the encoded data, and copying and outputting the encoded data. And a method for controlling a digital copying apparatus having

[0002]

2. Description of the Related Art In an electronic sorting function of a digital copying apparatus, generally, read image information is stored in a memory, image data held in the memory is compressed, and then stored in the memory again. Further, the compressed data held in the memory is expanded to form a copy image.
In this method, the copy output cannot be started unless the decoding of at least one page of data is completed, so that there is a problem that the time until the first copy is completed (first copy time) becomes long.

In order to solve this problem, Japanese Patent Laid-Open Publication No.
As described in U.S. Pat. No. 37,744, [H04N 1 / 21,1 / 413], by controlling the encoding means, the code storage means and the decoding means, the encoding process of the image data of the original being read can be performed. It has been proposed to perform decoding of image data that has been encoded and written in the code storage means in parallel.

[0004]

However, for the above-described parallel processing, it is necessary that the encoding means and the decoding means can be controlled independently. For example, as the encoding / decoding means, the encoding / decoding channel is l
An inexpensive dedicated processor IC with only channels (for example,
M65762 QM DECODE manufactured by Mitsubishi Electric Corporation
When RLSI) is used, it is necessary to switch between the encoding process and the decoding process in a time-division manner, which complicates the control.

In order to avoid such time-sharing control, the above-mentioned IC may be used exclusively for encoding and decoding, respectively. In this case, not only is the cost increased, but also the area of the substrate is reduced. Leads to an increase.

If a dedicated processor IC having two encoding / decoding channels (for example, IP00C401 high-speed lossless image compression / expansion LSI manufactured by Sumitomo Metal Co., Ltd.) is used, a code as described above can be obtained. There is no need for time-division switching between decoding and decoding, and control is facilitated. However, such an IC is more expensive than the above-described one-channel IC, and there is still a problem of cost.

SUMMARY OF THE INVENTION It is, therefore, a primary object of the present invention to provide a digital copying apparatus capable of speeding up copying using an electronic sorting function without a problem of cost.

[0008]

According to the present invention, there is provided an original reading means for electrically reading an original and outputting image data, a line memory for storing image data line by line, and encoding image data written in the line memory. Encoding means for encoding, code memory for storing image data encoded by the encoding means, decoding means for decoding encoded image data stored in the code memory and writing the same in a line memory, and line memory An electronic sort control method in a digital copying apparatus having a print engine for executing printing in accordance with image data stored in an image processing apparatus, wherein a single coder serves both as an encoding unit and a decoding unit, and a first copy is executed from a line memory. By providing image data to the print engine and coder, Digital copying, in which the second and subsequent copies are printed in accordance with the decoded image data by giving the coded image data from the code memory to the coder. 6 is an electronic sort control method in the apparatus.

[0009]

A line memory for storing several lines of image data (bitmap data) to be printed is prepared, and for the first copy, the image data read by the document reading means is sequentially stored in the line memory. , The encoding by the coder and the printing by the print engine are performed simultaneously (in real time). At this time, the encoding line
Do not overtake the write line to the line memory
Also, control is performed so that the write line to the line memory does not pass the encoding line and the print line.

The encoding time of one line by the coder is determined by the synchronization signal PRINT-H in the print engine.
Use such a coder that is less than one cycle time of the SYNC signal. This ensures that the print line does not overtake the encoding line.

The coded image data is stored in a code memory which can be read and written at a high speed and is composed of a semiconductor memory such as a DRAM. In the printing of the second copy and thereafter, the printing is executed by decoding the encoded image data stored in the code memory on the line memory. At this time, the decoding line is
It is controlled not to overtake the print line.

Also, by using a coder in which the decoding time of one line is less than one period of the synchronization signal PRINT-HSYNC signal in the print engine, it is ensured that the print line does not overtake the decoding line.

[0013]

According to the present invention, since it is not necessary to activate encoding and decoding at the same time, it is not necessary to use the two-channel coder described above, and even if one coder is used. Since complicated time division control can be avoided,
With a simple configuration and control, the first copy processing time at the time of electronic sort copy can be reduced. further,
If hardware overtaking control is used, the load on the control software for that purpose is greatly reduced.

The above objects, other objects, features and advantages of the present invention will become more apparent from the following detailed description of embodiments with reference to the drawings.

[0015]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A digital copying apparatus 10 according to an embodiment of the present invention shown in FIG. 1 includes a solid-state imaging device such as a CCD and an optical system, and scans a document (not shown) to convert a document image. It includes a scanner 12 for reading. Scanner 12
That is, the analog image signal output from the CCD is input to the image processing circuit 14. As is well known, the image processing circuit 14 includes an A / D converter (not shown), converts an input image signal into image data, and further performs shading correction and binarization on the image data. And outputs bitmap data. Note that the scanner 12 outputs a synchronization signal CCD-HSYNC,
The signal is supplied to the image processing circuit 14 and to the DDMAC circuit 16. Accordingly, the image processing circuit 14 outputs image data in synchronization with the synchronizing signal CCD-HSYNC, and the DDMAC circuit 16 outputs the image data in synchronism with the synchronizing signal.
It controls the DMA transfer of the RAM 18.

The DDMAC circuit 16 controls the writing of data to the DRAM 18 and the reading of data therefrom, that is, the control when data transfer is performed by the DMA (Direct Memory Access) method, and can control three DMA channels. .

The bit map data from the image processing circuit 14 is input to a first line memory 20 or a page memory 22 formed in a part of the DRAM 18. The first line memory 20 has an area capable of storing, for example, 64 lines of bitmap data.
Under the control of the C circuit 16, it receives bitmap data from the image processing circuit 14. The page memory 22 has an area capable of storing bitmap data for one page, and performs a rotation process (for example, 90 degrees or 27 degrees) on image data.
(0 °) is required, the bitmap data is received from the image processing circuit 14 under the control of the DDMAC circuit 16.

The first line memory 20 and the page memory 22 have the same DR as a later-described code memory 44.
It is formed in AM16. The transfer of image data from the image processing circuit 14 to the DRAM 18 is controlled by the DDMA 1.

The rotation processing circuit 24 is a circuit for performing a rotation process on the bitmap data read from the first line memory 20 or the page memory 22 in accordance with the DDMA2, and is specifically shown in FIG. It is. That is, the rotation processing circuit 24 includes two buffer groups 26 that receive the bitmap data W_DATA from the DRAM 16.
Each of the buffer groups 26 and 28 includes 16 (16 words) buffers A0-A15 and B0-B15, each of which is 16 bits wide. The bitmap data written to and read from each of the buffers A0 to A15 of the buffer group 26 is supplied to the first rearrangement circuit 30. Similarly, the bitmap data from each of the buffers B0 to B15 of the buffer group 28 is supplied to the second rearrangement circuit 32. The outputs of the two rearrangement circuits 30 and 32 are selectively output by the selector 34 and output as read data R_DATA.

The rotation processing circuit 24 is, for example, an RO
The control circuit 36 includes an M decoder, and the control circuit 36 supplies write signals WE_A0-WE_A15 and W to each of the buffers A0-A15 and B0-B15.
E_B0-WE_B15 are supplied, and a selection signal S is supplied to the selector 34. Control circuit 36
Further includes a request signal REQ for a DMA transfer described later.
_DDMA2 and REQ_SDMA1, and an acknowledge signal ACK for the DMA request.
_DDMA2 and ACK_SDMA1 are received. The control circuit 36 outputs the above-mentioned write signal and selection signal at a predetermined timing in response to the DMA request signal and the acknowledge signal.

That is, when a rotation process of 90 degrees or 270 degrees is required, the rotation processing circuit 24 controls the writing and reading of data in the two buffer groups 26 and 28, thereby controlling the image on the page memory 22. The image data is output as if the data were scanned in the direction shown in FIG.

Returning to FIG. 1, the read data R_DATA from the rotation processing circuit 24 is given to the second line memory 38 under the control of the SDMAC circuit 40 (SDMA1). As the second line memory 38, for example, a single-board SRAM having a width of 65536 (64 KW) × 16 bits is used, and the main scanning direction is composed of 512 words. Image data for a line can be stored. Also, one block is configured as 16 lines,
As shown in FIGS. 3 and 6, the second line memory 38 stores a total of eight blocks of image data.

The SDMAC circuit 40 has a synchronization signal PRINT-HSY from a print engine 48 (described later).
The SRAM, that is, the second line memory 38 is synchronized with the NC.
Is controlled. That is, the SDMAC circuit 4
0 controls data writing to the SRAM 38 and data reading from the SRAM 38 by the DMA method, and can control three DMA channels.

The bitmap data (image data) stored in the second line memory 38 is in accordance with SDMA3.
The QM coder 42 (this may be, for example, the one-channel encoding / decoding chip described above, which may be “M65762” manufactured by Mitsubishi Electric Corporation) and is encoded there. This QM coder 42 also has a DDMA3
And decodes the decoded data (bitmap data) into the second line memory 38 according to SDMA3, and stores the bitmap data stored in the second line memory 38 according to SDMA3. , SDMA2, a print video I / F circuit 46, ie, a print engine 48.
Given to.

The print video I / F circuit 46 receives the video map data in a bit-parallel manner in accordance with SDMA2, converts the data into a parallel-serial format, and supplies it to the print engine 48 as bit-serial data.

The digital copying apparatus 10 having such a configuration
In the case of the electronic sort copy in the first copy, the image data is transferred according to the data flow indicated by the solid line in FIG. 1, and in the second and subsequent copies, the image data is transferred according to the data flow indicated by the dotted line in FIG. Will be transferred.

First, the operation in the case of the first copy will be described. The image data from the scanner 12 is subjected to predetermined digital signal processing by the image processing circuit 14, and when the image rotation processing is not necessary, that is, when the image is rotated by 0 degrees, the image data is stored in the first line memory 20 according to the DDMA1. Stored as value bitmap data. D
Since the MAC circuit 16 receives the synchronization signal CCD-HSYNC output from the scanner 12, the bitmap data is synchronized with the synchronization signal CCD-HSYNC and the first
The data is input to the line memory 20 line by line.

The image data stored in the first line memory 20 is a DDM controlled by the DDMAC circuit 16.
By A2, it is sent to the rotation processing circuit 24 every two lines in synchronization with the synchronization signal CCD-HSYNC. Then, the rotation processing circuit 24 performs a 0-degree rotation process. That is, the rearrangement circuit 30 or 32 included in the rotation processing circuit 24 realizes 0-degree rotation by outputting the input image data as it is. Rotation processing circuit 24
As shown in FIG. 3, the output image data from
The data is transferred to the line memory 38. The data stored in the second line memory 38 for each line in synchronization with the synchronization signal CCD-HSYNC is simultaneously encoded by the QM coder 42 in accordance with SDMA3.

At this time, by automatically passing each other by hardware, the encoding process by the QM coder 42 (specifically, SDMA3 controlled by the SDMAC circuit 40) is performed by the second line memory. 38 (specifically, SDMA1 controlled by the SDMAC circuit 40) is prevented from overtaking, and writing to the second line memory 38 (SDMA1) overtakes encoding (SDMA3). To prevent. That is, the second line memory 38 is divided into eight blocks of 16 lines as shown in FIG. 3 and FIG. 6 in consideration of a later-described rotation of 90 degrees or 270 degrees. Are used as pointer addresses to these eight blocks, and overtaking control is realized by the pointer addresses.

When image data of, for example, six blocks is stored in the second line memory 38, the SDMA 2 is started and the image data is transferred to the print video I / F unit 46. At this time, in order to prevent the above-mentioned SDMA1 from overtaking SDMA2, the above-mentioned block transfer control method is used.
Automatically controlled by hardware.

Further, the synchronization signal CCD-HYSNC cycle output from the scanner 12 and the print engine 48
By controlling the period of the synchronization signal PRINT_HSYNC output from the SDMA2 to be the same, the SDMA2 is controlled not to overtake SDMAl.

Further, the clock frequency to be supplied to the QM coder 42 is determined so that the encoding processing time of one line by the QM coder 42 is sufficiently shorter than the synchronization signal PRINNT-HSYNC. As a result, SDMA2 becomes SD
Prevent overtaking MA1.

The bitmap data (in the form of an image) transferred to the print video I / F circuit 46 is subjected to parallel-serial conversion, and is passed to a print engine 48 for printing.

When rotation processing is necessary, and when rotation processing is performed by 90 degrees, image data from the scanner 12, that is, the image processing circuit 14, is synchronized with the synchronization signal CCD-HSYNC and line by line in the page memory 22. Is input to
The binary bitmap data for one page stored in the page memory 22 is stored in the page memory 4 by the DDMA 2.
The upper portion is read out by scanning as shown in FIG. 4A, and the bit map data read out from the page memory 22 is transferred to the rotation processing circuit 24.

As described above with reference to FIG. 2, the rotation processing circuit 24 has two buffer groups 26 and 28 each having a 16-bit width × 16 words. As shown in FIG. 5, the bitmap data is rearranged, and the rearranged bitmap data is sequentially stored in the second line memory 38 by SDMA1 as shown in FIG.

The bitmap data stored in the second line memory 38 is transferred to the QM coder 42 according to SDMA3.
Encoded by At this time, coding (SDM) is automatically performed by hardware
A3) is a write to the second line memory 38 (SDM
A1) is prevented, and writing (SDMA1) to the second line memory 38 is performed by coding (SD
MA3) is prevented from overtaking.

When the image data for, for example, six blocks is stored in the second line memory 38, the SDMA 2 is started and the image data is transferred to the print video I / F circuit 46. At this time, the hardware is automatically controlled by the above-described block transfer control method so that SDMA1 does not overtake SDMA2. QM coder 4
2, the encoding processing time of one line by the synchronization signal PRl
By determining the clock frequency supplied to the QM coder 42 so as to be sufficiently shorter than NT-HSYNC, it is possible to prevent SDMA2 from overtaking SDMA1.

The bitmap data (in the form of an image) transferred to the print video I / F circuit 46 is subjected to parallel / serial conversion, and is passed to a print engine 48 for printing.

When the rotation process is necessary and the image is rotated by 270 degrees, the page memory 2 is rotated as shown in FIG.
2 is different from that in the case of 90 degrees, and the subsequent processing is the same as in the case of 90 degrees rotation.

The above is the method of processing the first copy (first copy) during the sort copy.

Next, in the case of the copy of the second copy or later, the compressed image data stored in the code memory 44 is transferred to the QM coder 4
2, the data is sequentially decoded in the second line memory 38.
At this time, the code memory 44 is controlled by DDMA3, and the image side, that is, the second line memory 38 is controlled by SDMA3.

When image data of, for example, six blocks is stored in the second line memory 38, SDMA2 is started and the image data is transferred to the print video I / F circuit 46. At this time, the hardware is automatically controlled by the above-described pointer designation method so that SDMA3 does not overtake SDMA2. Further, the decoding processing time of one line by the QM coder 42 is the same as that of the synchronization signal PRINT-H.
The QM coder 42 is designed to be sufficiently shorter than SYNC.
By determining the supply clock frequency to the SDM
A2 is prevented from overtaking SDMA3.

The bitmap data (in the form of an image) transferred to the print video I / F circuit 46 is subjected to parallel-serial conversion, and is passed to a print engine 48 for printing.

As described above, in this embodiment, in the case of the first copy (first copy) using the electronic sort function, the bit map data is written to the second line memory 38 and the QM coder 42 Encoding,
After the predetermined line of bitmap data is stored in the second line memory 38, printing is performed according to the bitmap data. Then, in the second and subsequent copies, printing is executed by decoding the codes stored in the code memory 44 by the QM coder 42. That is, in this embodiment, the QM coder 42 is used in the encoding process when copying the first copy, and the QM coder 42 is used in the decoding process when copying the second and subsequent copies. Without control, the processing time of the first copy can be shortened by using only one one-channel encoding / decoding processor.

Further, by automatically overtaking control of DDMA and / or SDMA by hardware, the load on control software is greatly reduced.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an example of a digital copying apparatus to which the present invention can be applied.

FIG. 2 is a block diagram showing a specific configuration of a rotation processing circuit in the embodiment of FIG. 1;

FIG. 3 is an illustrative view showing a method of storing data in a second line memory at the time of 0-degree rotation in the embodiment of FIG. 1;

FIG. 4 is an illustrative view two-dimensionally showing a scanning order (an address generation order) on a page memory in the case of performing a rotation process of 90 degrees or 270 degrees in the embodiment of FIG. 1;

FIG. 5 is an illustrative view showing a processing method of a rearrangement circuit unit in the rotation processing circuit of FIG. 2;

FIG. 6 is an illustrative view showing a method of storing data in a second line memory at the time of rotating 90 degrees or 270 degrees in the embodiment of FIG. 1;

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 10 ... Digital copying apparatus 12 ... Scanner 14 ... Image processing circuit 16 ... DDMAC circuit 18 ... DRAM 20 ... First line memory 22 ... Page memory 24 ... Rotation processing circuit 38 ... Second line memory 40 ... SDMAC circuit 42 ... QM coder 44 ... code memory 46 ... print video I / F circuit 48 ... print engine

Claims (4)

[Claims] An original reading means for electrically reading an original and outputting image data; a line memory for storing the image data line by line; an encoding means for encoding image data written in the line memory; A code memory for storing the image data encoded by the encoding means, a decoding means for decoding the encoded image data stored in the code memory and writing the decoded image data to the line memory;
And an electronic sort control method in a digital copying apparatus including a print engine that executes printing in accordance with image data stored in the line memory, wherein the encoding means and the decoding means are shared by one coder, a) In the first copy, the image data is supplied from the line memory to the print engine and the coder, so that the image data is printed and encoded simultaneously. (b) In the second copy and thereafter, the code memory is sent from the code memory to the coder. An electronic sort control method in a digital copying apparatus, wherein printing is performed in accordance with decoded image data by providing encoded image data. 2. The method according to claim 1, wherein the line memory is divided into blocks for each predetermined line, and upper bits of an address of the line memory are used as a pointer address of each block.
In the step (a), the writing of the image data into the line memory and the encoding process do not pass each other, and in the step (b), the decoding process is performed from the line memory to the print engine. 2. The method according to claim 1, wherein reading of the image data is not overtaken. 3. In the step (a), image data is read from the line memory to the print engine by setting an encoding processing time of one line of the coder to less than one cycle of a synchronization signal of the print engine. 3. An electronic sort control method in a digital copying apparatus according to claim 1, wherein said control means does not overtake said encoding processing. 4. A step of reading image data from said line memory to said print engine in said step (b) by setting a decoding processing time of one line of said coder to less than one cycle of a synchronization signal of said print engine. 4. An electronic sort control method in a digital copying apparatus according to claim 1, wherein said control means does not overtake said decoding processing.