JP2004145700A - Data transfer mechanism - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a data transfer mechanism capable of quickly transferring data without passing through a CPU. <P>SOLUTION: The data transfer mechanism is provided with a memory controller 2 for converting a read command from the CPU 1 to one memory A into a write command to the other memory B and converting a write command to one memory A into a read command to the other memory B, an address counter 3 having a function for generating addresses different from the addresses of one memory A as addresses of the other memory B and an address selector having a function for transmitting the addresses generated by the address counter 3 to the other memory B. The data transfer mechanism is also provided with a memory selector 5 having a function for decoding an address signal transmitted from the CPU 1 and simultaneously transmitting select signals for asserting or deasserting respective memories A, B to the two memories A, B and a data bus controller 6 having a function for interrupting the transmission of data signals between the CPU 1 and the two memories A, B. <P>COPYRIGHT: (C)2004,JPO

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a data transfer mechanism that enables high-speed data transfer between two memories.
[0002]
[Prior art]
FIG. 10 is a block diagram showing a conventional data transfer mechanism.
[0003]
This data transfer mechanism includes a CPU for giving an instruction regarding data transfer between two memories, a memory A as a data transfer source, and a memory B as a transfer destination.
[0004]
An address bus and a data bus are connected between the CPU and the memory A and between the CPU and the memory B. An address signal is transmitted via the address bus, and a data signal is transmitted via the data bus. It is configured to be.
[0005]
Further, between the CPU and the memory A and between the CPU and the memory B, a read command and a write command are given from the CPU to the memory A and the memory B.
[0006]
When transferring data from the memory A to the memory B, the CPU first gives an address and a read command (read command) to the memory A in a read cycle, and transfers the data of the corresponding address of the memory A to the data. The data is taken into a register in the CPU via the bus.
[0007]
Subsequently, in a write cycle, an address, data fetched into the register, and a write command (write command) are given to the memory B, and the data is written to a corresponding address of the memory B.
[0008]
That is, in terms of operation, a read operation for the memory A and a write operation for the memory B are required.
[0009]
If each operation is composed of three cycles of address output (cycle 1), command output (cycle 2), and output stop of each command (securing an interval: cycle 3), 1 cycle A total of six cycles were required for one data transfer.
[0010]
[Patent Document 1]
JP-A-6-131292
[Patent Document 2]
JP-A-7-141287
[0011]
[Problems to be solved by the invention]
As described above, when the data transfer between the two memories A and B requires six cycles related to the read operation and the write operation, the data transfer speed naturally becomes slow, and this has been pointed out as a problem.
[0012]
Therefore, an object of the present invention is to provide a data transfer mechanism capable of transferring data at high speed without passing through a CPU.
[0013]
[Means for Solving the Problems]
To achieve the above object, the data transfer mechanism of the present invention converts a read command into a write command to the other memory when the CPU issues a read command to one of the memories. The write command is given to the other memory, and when the write command is given to the one memory, the write command is converted into a read command to the other memory, and the write command is sent to the other memory. A memory controller having a function of giving the read command, and when a write command to the one memory is given from the memory controller, an arbitrary address independent of the address of the one memory is written to the other memory. An address counter having a function of generating the address as a memory address, and when a read command is given from the CPU to the one memory, The address of the address signal transmitted from the CPU to the one memory is replaced with the address generated in the address counter and transmitted to the other memory, and the CPU issues a write command to the one memory. The address selector having the function of transmitting the address of the address signal transmitted from the CPU to the one memory to the other memory, and the CPU from the CPU to the one memory and the other memory. A memory selector having a function of decoding an address signal to be transmitted and transmitting a select signal for asserting or deasserting each memory to the two memories simultaneously, and a read command to the other memory are given. In this case, the three CPUs and the two memories communicate with each other. On the bus, which is the ability, characterized in that it comprises a data bus controller having a function to cut off the electrical transmission of data signals between said CPU said two memories.
[0014]
According to the data transfer mechanism of the present invention, a read command and an address are given to one memory as a transfer source, and at the same time, a write command is given to the other memory as a transfer destination via a memory controller, and an address counter and an address are given. By controlling so as to give an address via the selector, the data read from the corresponding address of one memory of the transfer source can be directly transferred to the corresponding address of the other memory of the transfer destination without passing through the CPU. Can be controlled to be written in
[0015]
According to the data transfer mechanism of the present invention, when the high-speed transfer mode is selected, the data bus controller cuts off the transmission of the data signal between the CPU and the two memories, whereby The bus between the other memory and the other memory can be in a floating state, so that the data read from the corresponding address of the other memory can be directly transferred to the corresponding memory of the one memory without passing through the CPU. It is also possible to control so as to write to the address, and it is possible to realize bidirectional high-speed data transfer between the two memories.
[0016]
Further, when a read command is given to one memory from the CPU, the data transfer mechanism of the present invention converts the read command into a write command to the other memory and converts the read command into a write command to the other memory. When the write command is given to the one memory, the write command is converted into a read command to the other memory, and the read command is sent to the other memory. And a memory controller having a function of giving, when a write command to the one memory is given from the memory controller, an arbitrary address independent of the address of the one memory as an address of the other memory. An address counter having a function of generating the data; and a read command from the CPU to the one memory; When the address of the address signal transmitted to the one memory is replaced with the address generated in the address counter and transmitted to the other memory, a write command is given from the CPU to the one memory. An address selector having a function of transmitting an address of an address signal transmitted from the CPU to the one memory to the other memory, and an address selector having a function of transmitting the address signal from the CPU to the one memory and the other memory. And a memory selector having a function of simultaneously transmitting a select signal for asserting or deasserting each memory to the two memories and a read command to the other memory. Can be mutually transmitted between the CPU and the three memories. On the scan, characterized in that it comprises a data bus controller having a function to cut off the electrical transmission of data signals between said CPU said two memories.
[0017]
According to the data transfer mechanism of the present invention, data transfer can be performed according to one of the normal transfer mode and the high-speed transfer mode selected by the user.
[0018]
BEST MODE FOR CARRYING OUT THE INVENTION
FIG. 1 is a block diagram showing an information transmission circuit of the data transfer mechanism of the present invention.
[0019]
The data transfer mechanism shown in this figure has two memories (memory A and memory B) and a CPU 1 for giving an instruction regarding data transfer between the memories A and B.
[0020]
In the data transfer mechanism of the present embodiment, the user can select one of a normal transfer mode in which data is transferred at a normal speed and a high-speed transfer mode in which data is transferred at a speed higher than the normal transfer mode. The CPU 1 is configured to control data transfer in accordance with one of the modes selected by the user.
[0021]
An address bus and a data bus are connected between the CPU 1 and the memory A and between the CPU 1 and the memory B. An address signal is transmitted via the address bus, and a data signal is transmitted via the data bus. At the same time, a read command and a write command are provided from the CPU 1 to between the memories A and B.
[0022]
The data transfer mechanism of the present embodiment includes a memory controller 2, an address counter 3, an address selector 4, a memory selector 5, and a data bus controller 6.
[0023]
When the high-speed transfer mode is selected, the memory controller 2 converts the read command into a write command to the memory B when a read command is given from the CPU 1 to the memory A. When the write command is given to the memory B, and when the write command is given to the memory A, the write command is converted into a read command to the memory B, and the read command is sent to the memory B. When the normal transfer mode is selected, a write command or a read command for the memory B, which is provided from the CPU 1, is provided to the memory B as it is.
[0024]
When the high-speed transfer mode is selected, when a write command to the memory A is given from the memory controller 2, the address counter 3 stores an arbitrary address independent of the address of the memory A into the memory A. It is configured to generate as the address of B. Even if the generated address is the same as the address of the memory A, there is no problem because it is not generated depending on the address of the memory A.
[0025]
That is, according to the address counter 3 in the data transfer mechanism of the present embodiment, an address (initial value of the address) different from the address (initial value of the address) transmitted from the CPU 1 is given to the memory B as the transfer destination. Value), data can be transferred to any address of the memories A and B.
[0026]
Although various count-up conditions can be considered, high-speed data transfer can also be achieved by configuring the count-up by asserting a write command to the memory B during high-speed transfer.
[0027]
Further, by adjusting the count-up condition of the address counter 3, complicated data such as transferring data from an arbitrary area of the memory as the data transfer source to an arbitrary rectangular area of the memory as the transfer destination can be obtained. Transfer is also possible.
[0028]
When the high-speed transfer mode is selected, when the CPU 1 issues a read command to the memory A, the address selector 4 reads the address of the address signal transmitted from the CPU 1 to the memory A. The address is replaced with the address generated by the address counter 3 and transmitted to the memory B. When the high-speed transfer mode is selected, when a write command is given from the CPU 1 to the memory A, and When the normal transfer mode is selected, the address of the address signal transmitted from the CPU 1 to the memory A is transmitted to the memory B.
[0029]
The memory selector 5 decodes an address signal transmitted from the CPU 1 to the memories A and B, and when a high-speed transfer mode is selected, outputs a select signal for asserting or de-asserting each memory. The configuration is such that when the normal transfer mode is selected, the select signal for the memory A or the memory B given from the CPU 1 is directly supplied to the memory A or the memory B when the normal transfer mode is selected. Have been.
[0030]
Then, when the high-speed transfer mode is selected and the read command is given to the memory B, the data bus controller 6 mutually communicates between the CPU 1 and the two memories. The transmission of the data signal between the CPU 1 and the two memories on the bus enabled to be transmitted is cut off.
[0031]
Next, a description will be given, as a first example, of an operation when data is transferred from the memory A to the memory B in the high-speed transfer mode in the data transfer mechanism of the present embodiment described above (see FIGS. 2 to 4). .
[0032]
First embodiment:
First, the CPU 1 outputs an address 1 via an address bus. At this time, the memory selector 5 decodes the output address 1 to generate select signals (memory A select signal and memory B select signal) for each memory, and asserts the select signal for each memory (see above). Cycle 1).
[0033]
Subsequently, the CPU 1 asserts a data read signal (RD signal) to the memory A (read command) and causes the memory A to output data.
[0034]
At this time, the memory controller 2 converts the read command into a write command to the memory B, and asserts a write signal (WT signal) to the memory B (write command). Subsequently, the address counter 3 generates an arbitrary address 2 as an address of the memory B, and the address selector 4 outputs the address 2 generated by the address counter 3 to the memory B, and outputs the address A to the memory A. Is input (the above is cycle 2).
[0035]
As described above, the operation of reading data from the memory A and the operation of writing data to the memory B are executed in synchronization with each other, and when the data transfer is completed, the read signal is deasserted from the CPU 1 to the memory A. At the same time, the memory controller 2 deasserts a write signal to the memory B.
[0036]
Further, the CPU 1 stops the output of the address 2 and also stops the generation of the address 2 of the memory B and the output of the address 2 in the address counter 3 and the address selector 4.
[0037]
Then, the memory selector 5 deasserts the memory A select signal and the memory B select signal, and stops outputting data from the memory A (the above is cycle 3).
[0038]
As described above, according to the data transfer mechanism of the present embodiment, the read command and the address (address 1) are given to one of the memories as the transfer source, and the other memory as the transfer destination is also transmitted to the other memory via the memory controller 2. Control to give an address (address 2) via the address counter 3 and the address selector 4 so that the data read from the corresponding address 1 of one of the memories as the transfer source can be transferred to the CPU 1 , It is possible to control to write directly to the corresponding address 2 of the other memory as the transfer destination without going through.
[0039]
That is, in the data transfer mechanism of the present embodiment, the conventional data transfer mechanism (the same is true in the normal transfer mode in the data transfer mechanism of the present embodiment) requires six cycles of memory access for data transfer. On the other hand, data transfer can be completed in three cycles, which is half of the above, and high-speed data transfer is realized. Moreover, the data transfer mechanism of the present embodiment can perform data transfer by arbitrarily setting the data transfer destination address (address 2) without imposing a burden on the CPU 1.
[0040]
Further, in the data transfer mechanism of the present embodiment, when the user selects the normal transfer mode, transfer requiring six cycles of memory access is possible as in the conventional case. The operation in that case will be described as a second example of the present embodiment (see FIGS. 5 to 7). In FIG. 5, a thick solid line indicates a read operation on the memory A, and a bold line indicates a write operation on the memory B.
[0041]
Second embodiment:
First, the CPU 1 outputs an address 1 via an address bus in order to start a read operation on the memory A. At this time, the memory selector 5 decodes the output address 1 to generate a memory A select signal, and asserts the memory A select signal (the above is cycle 1).
[0042]
Subsequently, the CPU 1 asserts a data read signal to the memory A (read command) and causes the memory A to output data. At this time, the CPU 1 loads data into the internal register (the above is cycle 2).
[0043]
When the data loading is completed, the CPU 1 deasserts a read signal from the CPU 1 to the memory A, and the CPU 1 stops outputting the address 1.
[0044]
Then, the memory selector 5 deasserts the memory A select signal and stops outputting data from the memory A (the above is cycle 3).
[0045]
Subsequently, the CPU 1 outputs an address 2 via an address bus in order to start a write operation on the memory B. At this time, the memory selector 5 decodes the output address 2 to generate a memory B select signal, and asserts the memory B select signal.
[0046]
Further, the CPU 1 outputs the data temporarily stored in the internal register (the above is the cycle 4).
[0047]
Subsequently, the CPU 1 asserts a data write signal to the memory B (the above is the cycle 5).
[0048]
Then, when the writing of the data is completed, the CPU 1 deasserts the write signal, and further stops the output of the address 2 and the output of the data.
[0049]
Further, the memory selector 5 deasserts the memory B select signal (the above is the cycle 6).
[0050]
As described above, the data transfer mechanism of the present embodiment has a configuration capable of data transfer in the high-speed transfer mode, and can also perform data transfer in the normal transfer mode.
[0051]
Further, the data transfer mechanism of the present embodiment includes the data bus controller 6 so that data transfer from the memory B to the memory A in the high-speed transfer mode can be performed.
[0052]
That is, when the high-speed transfer mode is selected by the user, when a read command is given to the memory B, the data bus controller 6 causes the CPU 1 and the two memories to communicate with each other. By interrupting the transmission of the data signal between the CPU 1 and the two memories on the bus that can be transmitted, the bus between the memories A and B is floated.
[0053]
This makes it possible to control the data read from the corresponding address in the memory B to be directly written to the corresponding address in the memory A without going through the CPU 1.
[0054]
Hereinafter, an operation when data is transferred from the memory B to the memory A in the high-speed transfer mode will be described as a third embodiment (see FIG. 8).
[0055]
Third embodiment:
First, the CPU 1 outputs an address via an address bus. At this time, the memory selector 5 decodes the output address, generates select signals (memory A select signal, memory B select signal) for each memory, and asserts the select signal for each memory (the above is the cycle cycle). 1).
[0056]
Subsequently, the CPU 1 asserts a data write signal to the memory A (write command).
[0057]
The memory controller 2 converts the write command into a read command to the memory B, and asserts a read signal to the memory B (read command). Subsequently, the address selector 4 outputs the address output from the CPU 1 to the memory B as it is.
[0058]
At this time, as described above, in the data bus controller 6, a data signal between the CPU 1 and the two memories on a bus which is mutually transmittable between the CPU 1 and the two memories. , The bus between the memory A and the memory B is floated, and the data output from the address of the memory B is input to the address of the memory A (the above-described cycle cycle). 2).
[0059]
In this manner, the operation of reading data from the memory B and the operation of writing data to the memory A are executed in synchronization with each other, and when the data transfer is completed, the read signal is deasserted from the CPU 1 to the memory B. At the same time, the memory controller 2 deasserts a write signal from the memory A.
[0060]
The CPU 1 stops outputting the address.
[0061]
Then, the memory selector 5 deasserts the memory A select signal and the memory B select signal, and stops outputting data from the memory B (the above is cycle 3).
[0062]
As described above, according to the data transfer mechanism of the present embodiment, the data read from the corresponding address of the memory B is directly written to the corresponding address of the memory A without passing through the CPU 1, thereby enabling the CPU 1 Since the burden can be reduced, high-speed data transfer becomes possible.
[0063]
That is, the data transfer mechanism of the present embodiment not only enables one-way high-speed data transfer between the memories A and B, but also enables high-speed bidirectional data transfer.
[0064]
Hereinafter, an operation when data is transferred from the memory B to the memory A in the normal transfer mode will be described as a fourth embodiment (see FIG. 9). In the drawing, a thick solid line indicates a read operation for the memory A, and a thick broken line indicates a write operation for the memory B.
[0065]
Fourth embodiment:
The CPU 1 outputs an address 1 via an address bus to start a read operation on the memory B. At this time, the memory selector 5 decodes the output address to generate a memory B select signal, and asserts the memory B select signal (the above is cycle 1).
[0066]
Subsequently, the CPU 1 asserts a data read signal to the memory B (read command), and outputs data from the memory B (the above is cycle 2).
[0067]
At this time, the CPU 1 loads data into the internal register. When the loading is completed, the CPU 1 deasserts a read signal from the CPU 1 to the memory B, and the CPU 1 stops outputting the address 1.
[0068]
Then, the memory selector 5 deasserts the memory B select signal and stops outputting data from the memory B (the above is cycle 3).
[0069]
Subsequently, the CPU 1 outputs an address 2 via an address bus to start a write operation on the memory A. At this time, the memory selector 5 decodes the output address 2 to generate a memory A select signal, and asserts the memory A select signal. Further, the CPU 1 outputs the data temporarily stored in the internal register (the above is the cycle 4).
[0070]
Subsequently, the CPU 1 asserts a data write signal to the memory A (the above is the cycle 5).
[0071]
When the transfer of the data from the internal register of the CPU 1 to the memory A is completed, the write signal is deasserted, and the CPU 1 stops outputting the address 2 and outputting the data.
[0072]
Further, the memory selector 5 deasserts the memory A select signal (the above is the cycle 6).
[0073]
As described above, in the data transfer mechanism of the present embodiment, data can be transferred in both directions between the two memories even in the normal transfer mode.
[0074]
Note that the present invention is not limited to the above-described embodiment, and various changes can be made as necessary.
[0075]
For example, when high-speed data transfer is performed between two memories in only one direction, the data bus controller 6 can be omitted.
[0076]
Further, it is also possible that only the data transfer in the high-speed transfer mode is performed without making the normal transfer mode and the high-speed transfer mode selectable. In this case, the memory controller 2, the address counter 3, and the address Each of the selector 4 and the memory selector 5 may be configured to perform only control (determination) in the high-speed transfer mode.
[0077]
【The invention's effect】
As described above, according to the present invention, a read command and an address are given to one memory as a transfer source, and at the same time, a write command is given to the other memory as a transfer destination via a memory controller, and an address counter and By controlling to give an address via the address selector 4, the data read from the corresponding address of one of the memories as the transfer source can be directly transferred to the other memory as the transfer destination without passing through the CPU 1. It is possible to control so as to write to the corresponding address, and the transfer mode can be configured so that the user can select one of the normal transfer mode and the high-speed transfer mode.
[0078]
And, not only when the normal transfer mode is selected, but also when the high-speed transfer mode is selected, by providing the data bus controller 6, the data read from the corresponding address of the other memory can be read. It is also possible to control so as to write directly to the corresponding address of the one memory without going through the CPU 1, thereby realizing bidirectional high-speed data transfer between the two memories.
[Brief description of the drawings]
FIG. 1 is a block diagram showing an information transmission circuit of a data transfer mechanism of the present invention.
FIG. 2 is a block diagram showing a data transmission circuit in the first embodiment (high-speed AtoB) by a bold line;
FIG. 3 is a flowchart of data transfer control in the first embodiment.
FIG. 4 is a timing chart of data transfer control in the first embodiment.
FIG. 5 is a block diagram showing a data transmission circuit in a second embodiment (usually AtoB) by a bold line;
FIG. 6 is a flowchart of data transfer control in a second embodiment.
FIG. 7 is a timing chart of data transfer control in the second embodiment.
FIG. 8 is a block diagram showing a data transmission circuit in a third embodiment (high-speed BtoA) by a thick line;
FIG. 9 is a block diagram showing a data transmission circuit in a fourth embodiment (normal BtoA) by a bold line;
FIG. 10 is a block diagram showing an information transmission circuit of a conventional data transfer mechanism.
[Explanation of symbols]
A memory (one memory)
B memory (the other memory)
1 CPU
2 Memory controller
3 Address counter
4 Address selector
5 Memory selector
6 Data bus controller

Claims (2)

An address signal output from the CPU is bus-connected to the two memories so as to be able to transmit the data signal, and a data signal is bus-connected so that the data signal can be mutually transmitted between the CPU and the three memories. A data transfer mechanism configured to perform control related to data transfer,
When a read command is given from the CPU to one of the memories, the read command is converted into a write command to the other memory, and the write command is given to the other memory. When a write command is given to the memory, a memory controller having a function of converting the write command into a read command to the other memory and giving the read command to the other memory,
When a write command to the one memory is given from the memory controller, an address counter having a function of generating an arbitrary address independent of the address of the one memory as an address of the other memory. ,
When the CPU issues a read command to the one memory, the address of the address signal transmitted from the CPU to the one memory is replaced with an address generated in the address counter, and A function of transmitting an address of an address signal transmitted from the CPU to the one memory to the other memory when a write command is given from the CPU to the one memory. An address selector having
A memory selector having a function of decoding an address signal transmitted from the CPU to the one memory and the other memory and transmitting a select signal for asserting or deasserting each memory to the two memories simultaneously. When,
When a read command is given to the other memory, the bus between the CPU and the two memories on a bus that can mutually transmit data between the CPU and the two memories. A data bus controller having a function of interrupting transmission of data signals,
A data transfer mechanism comprising: An address signal output from the CPU is bus-connected to the two memories so as to be able to transmit the data signal, and a data signal is bus-connected so that the data signal can be mutually transmitted between the CPU and the three memories. A data transfer mechanism configured to perform control related to data transfer,
The user can select one of a normal transfer mode in which data is transferred at a normal speed and a high-speed transfer mode in which data is transferred at a speed higher than the normal transfer mode, and the CPU is adapted to each mode. It is configured to perform control,
When the high-speed transfer mode is selected, when a read command is given from the CPU to one of the memories, the CPU converts the read command into a write command to the other memory and transfers the read command to the other memory. When the write command is given to the one memory, the write command is converted into a read command to the other memory, and the read command is sent to the other memory. A memory controller having a function of directly giving a write command or a read command to the other memory given from the CPU to the other memory when the normal transfer mode is selected;
In the case where the high-speed transfer mode is selected, when a write command to the one memory is given from the memory controller, an arbitrary address independent of the address of the one memory is set as the address of the other memory. An address counter having a function of generating;
When the high-speed transfer mode is selected, when a read command is given from the CPU to the one memory, an address of an address signal transmitted from the CPU to the one memory is generated in the address counter. To the other memory and send it to the other memory,
When the high-speed transfer mode is selected, when the CPU issues a write command to the one memory, and when the normal transfer mode is selected, the CPU transfers the one memory to the one memory. An address selector having a function of transmitting the address of the transmitted address signal to the other memory;
An address signal transmitted from the CPU to the one memory and the other memory is decoded, and when a high-speed transfer mode is selected, a select signal for asserting or deasserting each memory is transmitted to the two memories. And the function of simultaneously transmitting a select signal for the one memory or the other memory provided from the CPU to the one memory or the other memory when the normal transfer mode is selected. A memory selector,
When the high-speed transfer mode is selected, and when a read command is given to the other memory, the CPU and the three memories on the bus that are mutually capable of transmitting power are connected to each other. A data bus controller having a function of interrupting transmission of data signals between the CPU and the two memories.

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