JP4526664B2 - Bus bridge circuit - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a bus bridge circuit for connecting one bus to another bus.
[0002]
[Prior art]
A conventional bus bridge circuit 1 is shown in FIG. The bus bridge circuit 1 connects the bus A and the bus B by mutually converting the protocol of the bus A and the protocol of the bus B. One or more master devices (not shown) are connected to the bus A, and each master device is connected to the bus B by the bus bridge circuit 1 by one or more slave devices (not shown). (Not shown) can be accessed.
[0003]
Bus activation signal DSEL, write signal WRITE, clock signal CLK, wait signal WAIT, address signal BA, and data signal BD are transmitted by bus A, and address strobe signal ASTB, read enable signal RDE, and write enable signal are transmitted by bus B. WRE, address / data signal ADB, and clock signal CLK are transmitted.
[0004]
The bus bridge circuit 1 includes a control circuit 11 and a bus multiplexer (hereinafter “bus Mux”) 12.
[0005]
The control circuit 11 receives a bus activation signal DSEL and a write signal WRITE from the bus A, outputs a wait signal WAIT to the bus A in synchronization with the clock signal CLK, and an address strobe signal ASTB to the bus B. The read enable signal RDE and the write enable signal WRE are output, and the address transfer request signal ADR_OUT, the ADB data output request signal ADB_OE, and the BD data output request signal BD_OE are output to the bus Mux12.
[0006]
The bus Mux 12 multiplexes the address signal BA of the bus A and the data signal BD based on the address transfer request signal ADR_OUT, the ADB data output request signal ADB_OE, and the BD data output request signal BD_OE output from the control circuit 1. The address / data signal ADB is output to B, the data signal is extracted from the address / data signal ADB of the bus B, and the data signal BD is output to the bus A.
[0007]
FIG. 13 is a timing chart showing the operation of the conventional bus bridge circuit 1. In FIG. 13, the middle timing chart shows the operation when the master device connected to the bus A reads data from one of the plurality of slave devices connected to the bus B. The timing chart shows the operation when the master device connected to the bus A writes data to one of the plurality of slave devices connected to the bus B. The upper timing chart is common to the data read operation and the data write operation.
[0008]
The master device connected to the bus A accesses the slave device connected to the bus B in synchronization with the falling edge of the first clock signal CLK after the bus activation signal DSEL is asserted (H level). (Data read operation and data write operation) are started.
[0009]
[Problems to be solved by the invention]
However, according to the conventional bus bridge circuit 1, the bus B is started after the bus start signal DSEL is asserted, and there is a delay of one clock in the data transfer between the master device and the slave device. There was a risk of it occurring.
[0010]
The present invention has been made in view of the above problems, and its purpose is to connect one bus and another bus, and connect from one device connected to the other bus to another bus. It is an object of the present invention to provide a bus bridge circuit capable of speeding up access to a device that is used.
[0011]
[Means for Solving the Problems]
In order to solve the above problem, according to a first aspect of the present invention, a first bus and a second bus are connected, output from a first device connected to the first bus, and connected to a second bus. An address for identifying one or more second devices being transmitted is transmitted from the first bus to the second bus, output from the first device, and from one or more second devices depending on the address Data to be written to the selected one or more second devices is transmitted from the first bus to the second bus, and one or more second devices selected from the one or more second devices by the address. A bus bridge circuit is provided for transmitting data output from the two devices and read into the first device from the second bus to the first bus. The bus bridge circuit receives the bus activation signal output from the first device, and then transmits the address output from the first device from the first bus to the second bus to transmit one or more second or more second signals. A first access mode in which one or more second devices are selected from the devices and data writing / data reading is performed between the first device and the selected one or more second devices; Before receiving a bus activation signal output from one device, an access mode switching signal is generated, and an address output by the first device is transmitted from the first bus to the second bus in accordance with the access mode switching signal. After selecting one or two or more second devices from the above second devices and receiving a bus activation signal output from the first device, the first device and one or more preselected first devices are selected. Data between two devices Performing writing / data reading is characterized by having a second access mode, at least two access modes.
[0012]
According to such a configuration, it is possible to easily switch between the first access mode and the second access mode in accordance with the access mode switching signal. In the second access mode, since the second device to be accessed is already selected when data writing or data reading from the first device to the second device is started, the data writing operation or the data reading operation is speeded up. Is realized. On the other hand, in the first access mode, since the address is transmitted to the second bus only after the first device starts to access the second device, unnecessary circuit operation does not occur and power saving is achieved. Contribute to.
[0013]
According to the second aspect of the present invention, the bus bridge circuit compares a register capable of setting a predetermined address or address range, an address set in the register, and an address output from the first device. And an address comparison circuit that outputs an access mode switching signal when both addresses match. By setting the address of the second slave that requires high-speed access in the register, the mode is switched to the second access mode in which high-speed access is possible only when accessing the second slave, thereby realizing further power saving. To do.
[0014]
According to the third aspect of the present invention, the bus bridge circuit receives the bus start signal and counts the number of receptions by receiving a register in which the first value and the second value can be set, and the count value is determined from the initial value. And a counter that outputs an access mode switching signal a number of times corresponding to the second value while reaching the first value. By adjusting the first value and the second value, it is possible to achieve both speeding up of access from the first device to the second device and reduction in power consumption.
[0015]
According to a fourth aspect of the present invention, a bus bridge circuit receives a bus start signal by receiving a register in which a first value, a second value, a third value, and a fourth value can be set, and a reception cycle. A period detection circuit that detects, compares the reception period with the first value, and outputs a count-up signal or a count-down signal according to the comparison result; and a step according to the second value when the count-up signal is input When the countdown signal is input, the counter that decreases the internal data in steps corresponding to the third value is compared with the internal data of the counter and the third value, and the access mode switching signal is set according to the comparison result. And a comparator circuit for outputting. By adjusting the first to fourth values, it is possible to finely set the switching timing between the first access mode and the second access mode. After setting the first to fourth values, the mode is automatically switched according to the cycle of the bus activation signal.
[0016]
According to a fifth aspect of the present invention, a bus bridge circuit receives a bus start signal by receiving a register which can set a first value, a second value, a third value and a fourth value, and a reception cycle. Detecting, comparing the reception period with the first value, and outputting the first shift signal or the second shift signal according to the comparison result; when the first shift signal is input, all bits of the internal data are A shift register that shifts in one direction in steps according to the second value and shifts all bits of the internal data in the other direction in steps corresponding to the third value when the second shift signal is input, and internal data And a selector that outputs a value of the selected predetermined bit as an access mode switching signal. Even in such a configuration, it is possible to finely set the switching timing between the first access mode and the second access mode by adjusting the first to fourth values. After setting the first to fourth values, the mode is automatically switched according to the cycle of the bus activation signal.
[0017]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, preferred embodiments of a bus bridge circuit according to the present invention will be described in detail with reference to the accompanying drawings. In the following description and the attached drawings, constituent elements having substantially the same function and configuration are denoted by the same reference numerals, and redundant description is omitted.
[0018]
[First Embodiment]
FIG. 1 shows a bus bridge circuit 101 according to a first embodiment of the present invention. The bus bridge circuit 101 connects the bus A and the bus B by mutually converting the protocol of the bus A as the first bus and the protocol of the bus B as the second bus. One or more master devices (not shown) as first devices are connected to the bus A, and each master device is connected to the bus B by the bus bridge circuit 101. It becomes possible to access a slave device (not shown) as the second device.
[0019]
Bus activation signal DSEL, write signal WRITE, clock signal CLK, wait signal WAIT, address signal BA, and data signal BD are transmitted by bus A, and address strobe signal ASTB, read enable signal RDE, and write enable signal are transmitted by bus B. WRE, address / data signal ADB, and clock signal CLK are transmitted.
[0020]
The bus / bridge circuit 101 includes a control circuit 111, a bus Mux 12, an address comparison circuit 112, and a register 113.
[0021]
The control circuit 111 receives the bus activation signal DSEL and the write signal WRITE from the bus A, receives the access mode switching signal QUICK from the address comparison circuit 112, and waits for the bus A to the wait signal WAIT in synchronization with the clock signal CLK. , The address strobe signal ASTB, the read enable signal RDE, and the write enable signal WRE are output to the bus B, the address transfer request signal ADR_OUT, the ADB data output request signal ADB_OE, and the bus Mux12 A BD data output request signal BD_OE is output.
[0022]
The bus Mux12 multiplexes the address signal BA of the bus A and the data signal BD based on the address transfer request signal ADR_OUT, the ADB data output request signal ADB_OE, and the BD data output request signal BD_OE output from the control circuit 111, and The address / data signal ADB is output to B, the data signal is extracted from the address / data signal ADB of the bus B, and the data signal BD is output to the bus A.
[0023]
The address comparison circuit 112 receives the address signal BA of the bus A and the address comparison signal AC output from the register 113, compares these values, and outputs the result as an access mode switching signal QUICK. As shown in FIG. 2, the address comparison circuit 112 includes, for example, a number of ExNOR (Exclusive NOR) gates 114-1 to 114- corresponding to the bit width (16-bit width in this case) of the address signal BA and the address comparison signal AC. 16 and one AND gate 115. Each ExNOR gate 114-1 to 114-16 detects a match / mismatch of each bit of the address signal BA and the address comparison signal AC, and supplies an H level signal to the AND gate 115 in the case of a match. The AND gate 115 asserts the access mode switching signal QUICK (H level) when all of the ExNOR gates 114-1 to 114-16 output H level signals.
[0024]
In FIGS. 1 and 2, signals having a plurality of bit widths are indicated by bold lines, and the bit widths are indicated by bold lines. Here, the address signal BA, the data signal BD, and the address / data signal ADB have a 16-bit width, and the address comparison signal AC has a 16-bit width or a bit width that is an integer multiple thereof.
[0025]
The register 113 stores an address for identifying one or more slave devices that require high-speed access among one or more slave devices connected to the bus B. The stored address is supplied to the address comparison circuit 112 as an address comparison signal AC. Note that the address comparison signal AC is not limited to the address itself to identify one slave device, but may be an address having a certain width for simultaneously identifying one or more slave devices. The address comparison circuit 112 compares the address comparison signal AC and the address signal BA, and if both values match (that is, the slave device identified by the address signal BA is a slave device for which high speed access is required). If there is, the access mode switching signal QUICK is asserted.
[0026]
Next, the operation of the bus bridge circuit 101 according to the first embodiment will be described with reference to the timing chart shown in FIG. In FIG. 3, the middle timing chart shows the operation when the master device connected to the bus A reads data from one of the plurality of slave devices connected to the bus B. The timing chart shows the operation when the master device connected to the bus A writes data to one of the plurality of slave devices connected to the bus B. The upper timing chart is common to the data read operation and the write operation.
[0027]
When the access mode switching signal QUICK input to the control circuit 111 is deasserted (L level), the bus bridge circuit 101 performs substantially the same operation as the conventional bus bridge circuit 1 as follows.
[0028]
First, a data read operation from the slave device connected to the bus B by the master device connected to the bus A will be described (first read cycle).
[0029]
When the bus activation signal DSEL is asserted and the first read cycle starts (arrow a in FIG. 3), the control circuit 111 asserts the wait signal WAIT (H level) and puts the bus A into the wait state. The control circuit 111 asserts (H level) the address strobe signal ASTB for one cycle of the clock signal CLK and asserts (H level) the address transfer request signal ADR_OUT.
[0030]
The bus Mux12 receives the asserted address transfer request signal ADR_OUT and outputs the address signal BA of the bus A to the bus B as the address / data signal ADB. One slave device is selected from among one or more slave devices connected to the bus B based on the address information included in the address / data signal ADB transmitted to the bus B.
[0031]
In synchronization with the falling edge of the next clock signal CLK, the control circuit 111 asserts (H level) the read enable signal RDE for one cycle of the clock signal CLK, and deasserts the address transfer request signal ADR_OUT (L level). Then, the BD data output request signal BD_OE is asserted (H level) for one cycle of the clock signal CLK.
[0032]
The bus Mux12 ends the transmission of the address signal BA from the bus A to the bus B when the address transfer request signal ADR_OUT is deasserted (L level). For this reason, the address / data signal ADB of the bus B is once in a high impedance state.
[0033]
The slave device selected by the address information included in the address / data signal ADB outputs the held data to the bus B as the address / data signal ADB based on the address strobe signal ASTB and the read enable signal RDE. The bus Mux12 receives the asserted BD data output request signal BD_OE and outputs the address / data signal ADB of the bus B to the bus A as the data signal BD.
[0034]
Then, the control circuit 111 deasserts the wait signal WAIT (L level) and notifies the master device that the first read cycle has ended (arrow b in FIG. 3).
[0035]
Next, a data write operation to the slave device connected to the bus B by the master device connected to the bus A will be described (first write cycle).
[0036]
When the bus activation signal DSEL is asserted and the first write cycle starts (arrow a in FIG. 3), the control circuit 111 asserts the wait signal WAIT to place the bus A in the wait state. The control circuit 111 asserts the address strobe signal ASTB for one cycle of the clock signal CLK and asserts the address transfer request signal ADR_OUT. The bus Mux12 receives the asserted address transfer request signal ADR_OUT and outputs the address signal BA of the bus A to the bus B as the address / data signal ADB.
[0037]
One slave device among one or more slave devices connected to the bus B is selected by address information included in the address / data signal ADB transmitted to the bus B.
[0038]
In synchronization with the falling edge of the next clock signal CLK, the control circuit 111 asserts (H level) the write enable signal WRE for one cycle of the clock signal CLK and deasserts the address transfer request signal ADR_OUT (L level). Then, the ADB data output request signal ADB_OE is asserted (H level) for one cycle of the clock signal CLK.
[0039]
The bus Mux12 receives the asserted ADB data output request signal ADB_OE and outputs the data signal BD of the bus A to the bus B as the address / data signal ADB.
[0040]
The slave device selected by the address information included in the address / data signal ADB takes in the data included in the address / data signal ADB based on the address strobe signal ASTB and the write enable signal WRE.
[0041]
Then, the control circuit 111 deasserts the wait signal WAIT (L level) and notifies the master device that the first write cycle has ended (arrow b in FIG. 3).
[0042]
The above is the data read operation and data write operation of the bus bridge circuit 101 when the access mode switching signal QUICK input to the control circuit 111 is deasserted (L level). On the other hand, the operation of the bus bridge circuit 101 when the access mode switching signal QUICK is asserted (H level) will be described.
[0043]
When the access mode switching signal QUICK input to the control circuit 111 is asserted, before the start of access from the master device connected to the bus A to the slave device connected to the bus B, as follows, The address information is notified to the bus B.
[0044]
When the bus activation signal DSEL is deasserted and the access mode switching signal QUICK is asserted in a so-called idle state where the bus bridge circuit 101 is not performing any data read operation or data write operation, the control circuit 111 The transfer request signal ADR_OUT and the address strobe signal ASTB are asserted (arrow c in FIG. 3). In response to this, the bus Mux 12 outputs the address signal BA of the bus A to the bus B as the address / data signal ADB. Therefore, when the bus activation signal DSEL is asserted and the data reading operation or data writing operation is shifted from the idle state, one slave device is selected from one or more slave devices already connected to the bus B. Thus, the subsequent data read operation and data write operation are executed quickly. Hereinafter, the operation of the bus bridge circuit 101 will be described in detail by dividing it into a data write operation and a data read operation.
[0045]
First, the data read operation from the slave device connected to the bus B by the master device connected to the bus A will be described (second read cycle).
[0046]
When the bus activation signal DSEL is asserted and the second read cycle starts (arrow d in FIG. 3), the control circuit 111 asserts the wait signal WAIT (H level) and puts the bus A into the wait state. The control circuit 111 asserts (H level) the read enable signal RDE for one cycle of the clock signal CLK and deasserts the address transfer request signal ADR_OUT (L level) in synchronization with the falling edge of the clock signal CLK. Then, the BD data output request signal BD_OE is asserted (H level) for one cycle of the clock signal CLK.
[0047]
The bus Mux12 ends the transmission of the address signal BA from the bus A to the bus B when the address transfer request signal ADR_OUT is deasserted (L level). For this reason, the address / data signal ADB of the bus B is once in a high impedance state.
[0048]
The slave device preselected by the address information included in the address / data signal ADB outputs the held data to the bus B as the address / data signal ADB based on the address strobe signal ASTB and the read enable signal RDE. To do. The bus Mux12 receives the asserted BD data output request signal BD_OE and outputs the address / data signal ADB of the bus B to the bus A as the data signal BD.
[0049]
Then, the control circuit 111 deasserts the wait signal WAIT (L level) to notify the master device that the second read cycle has ended, and the bus bridge circuit 101 returns to the idle state.
[0050]
Next, the data write operation to the slave device connected to the bus B by the master device connected to the bus A will be described (second write cycle).
[0051]
When the bus activation signal DSEL is asserted and the second write cycle starts (arrow d in FIG. 3), the control circuit 111 asserts the wait signal WAIT to place the bus A in the wait state. The control circuit 111 asserts (H level) the write enable signal WRE for one cycle of the clock signal CLK and deasserts (L level) the address transfer request signal ADR_OUT in synchronization with the falling edge of the clock signal CLK. Then, the ADB data output request signal ADB_OE is asserted (H level) for one cycle of the clock signal CLK.
[0052]
The bus Mux12 receives the asserted ADB data output request signal ADB_OE and outputs the data signal BD of the bus A to the bus B as the address / data signal ADB.
[0053]
The slave device selected in advance by the address information included in the address / data signal ADB takes in the data included in the address / data signal ADB based on the address strobe signal ASTB and the write enable signal WRE.
[0054]
Then, the control circuit 111 deasserts the wait signal WAIT (L level) to notify the master device that the second write cycle has ended, and the bus bridge circuit 101 returns to the idle state.
[0055]
As described above, according to the bus bridge circuit 101 according to the first embodiment, when the access mode switching signal QUICK input to the control circuit 111 is asserted, the master connected to the bus A The address information is notified to the bus B before the access to the slave device connected to the bus B from the device is started. Therefore, the start delay of the bus B which has been a problem in the conventional bus bridge circuit 1 is eliminated, and the access from the master device to the slave device is speeded up.
[0056]
On the other hand, when the access mode switching signal QUICK is deasserted, the address information is not notified to the bus B before the access to the bus B is started. Accordingly, the address signal that operates to notify the address information from the bus A to the bus B while speeding up the access from the bus A to the bus B by appropriately switching the assertion / deassertion of the access mode switching signal QUICK. The power consumption of the driver circuit and receiver circuit for the BA or address / data signal ADB can be minimized.
[0057]
Furthermore, according to the bus bridge circuit 101 according to the first embodiment, when a plurality of slave devices are connected to the bus B, a slave device that requires high-speed access is set in the register 113. It becomes possible to select by value. Therefore, a bus system that achieves both high-speed access and power saving will be constructed.
[0058]
[Second Embodiment]
FIG. 4 shows a bus bridge circuit 201 according to the second embodiment of the present invention. The bus bridge circuit 201 connects the bus A and the bus B by mutually converting the protocol of the bus A and the protocol of the bus B, like the bus bridge circuit 101 according to the first embodiment. One or more master devices (not shown) are connected to the bus A, and each master device is connected to the bus B by the bus bridge circuit 201. (Not shown) can be accessed.
[0059]
The bus bridge circuit 201 includes a control circuit 111, a bus Mux 12, an n / m counter 212, and a register 213.
[0060]
The n / m counter 212 receives the bus activation signal DSEL of the bus A, the clock signal CLK, and the first signal m and the second signal n output from the register 213, and switches the access mode based on these signals. The signal QUICK is output.
[0061]
The register 213 can set at least two values, and outputs the respective values to the n / m counter 212 as the first signal m and the second signal n.
[0062]
Next, the operation of the bus bridge circuit 201 according to the second embodiment will be described with reference to FIG. FIG. 5 shows a continuous data write operation from the bus A to the bus B of the bus bridge circuit 201. The operation of the bus bridge circuit 201 differs from the operation of the bus bridge circuit 101 according to the first embodiment only in the generation of the access mode switching signal QUICK. Therefore, here, the operation relating to the generation of the access mode switching signal QUICK will be mainly described.
[0063]
The n / m counter 212 counts the number of accesses from the bus A to the bus B using the bus activation signal DSEL. As shown in FIG. 5, for example, when “8” is input from the register 213 as the first signal m and “5” is input as the second signal, the n / m counter 212 indicates that the bus activation signal DSEL is 8 During the assertion, the access mode switching signal QUICK is asserted (H level) for 5 (n) times and deasserted (L level) for 3 (mn) times. The cycle (m) and the assert / deassert ratio (n / (mn)) of the access mode switching signal QUICK can be changed by adjusting the value set in the register 213.
[0064]
FIG. 5 shows a case where the access mode switching signal QUICK is continuously asserted / deasserted. However, the present invention is not limited to this, and the access mode switching is performed at an appropriate interval while the bus activation signal DSEL is asserted m times. The signal QUICK may be intermittently asserted / deasserted n times.
[0065]
Further, the access mode switching signal QUICK can be fixed to assert or fixed to deassert by a combination of the first signal m and the second signal n.
[0066]
As described above, according to the bus bridge circuit 201 according to the second embodiment of the present invention, high-speed access to the bus B and power consumption regardless of the address of the slave device connected to the bus B. It is possible to adjust the ratio of normal access with a small amount. Since it is not necessary to consider the address of the slave device, for example, the bus bridge circuit 201 is preferably employed in a system in which a slave device is added to or deleted from the bus B.
[0067]
[Third Embodiment]
FIG. 6 shows a bus bridge circuit 301 according to a third embodiment of the present invention. Similarly to the bus bridge circuits 101 and 201 according to the first and second embodiments, the bus bridge circuit 301 connects the bus A and the bus B by mutually converting the protocol of the bus A and the protocol of the bus B. Is. One or more master devices (not shown) are connected to the bus A, and each master device is connected to the bus B by one or more slave devices (not shown) by the bus bridge circuit 301. (Not shown) can be accessed.
[0068]
The bus bridge circuit 301 includes a control circuit 111, a bus Mux 12, a comparison circuit 312, an up / down counter 313, a period detection circuit 314, and a register 315.
[0069]
The comparison circuit 312 receives the counter output signal Q output from the up / down counter 313 and the comparison signal k output from the register 315, compares these values, and outputs the result as the access mode switching signal QUICK. . The comparison circuit 312 can be configured by a circuit similar to the comparison circuit 112 provided in the bus bridge circuit 101 according to the first embodiment, for example. That is, the comparison circuit 312 includes a number of ExNOR gates corresponding to the bit width (here, 3 bits width) of the counter output signal Q and the comparison signal k, and an AND gate. Each ExNOR gate detects a match / mismatch between each bit of the counter output signal Q and the comparison signal k, and supplies an H level signal to the AND gate if they match. The AND gate asserts (H level) the access mode switching signal QUICK when all of the ExNOR gates output a signal of H level.
[0070]
The up / down counter 313 receives internal data based on the count up signal U and count down signal D output from the cycle detection circuit 314 and the count up amount adjustment signal ni and count down amount adjustment signal nd output from the register 315. Count up or count down. The internal data is supplied to the comparison circuit 312 as a counter output signal Q in synchronization with the clock signal CLK. The up / down counter 313 does not count up above the maximum value of internal data (here “7”), but counts down below the minimum value (here “0”). Never happen.
[0071]
The cycle detection circuit 314 compares the cycle reference signal w output from the register 315 with the bus activation signal DSEL. If the cycle of the bus activation signal DSEL is smaller than the cycle reference signal w, the count up signal U is asserted and the count down signal D is deasserted. Conversely, if the cycle of the bus activation signal DSEL is larger than the cycle reference signal w, the count up signal U is deasserted and the count down signal D is asserted. When the cycle of the bus activation signal DSEL coincides with the cycle reference signal w, both the count up signal U and the count down signal D are deasserted.
[0072]
The register 315 can set at least four values. The period detection circuit 314 is used as a period reference signal w, a count-up amount adjustment signal ni, a count-down amount adjustment signal nd, and a comparison signal k. The data is output to the counter 313 and the comparison circuit 312.
[0073]
Next, the operation of the bus bridge circuit 301 according to the third embodiment will be described with reference to FIGS. 7 and 8 show the continuous data write operation from the bus A to the bus B in the bus bridge circuit 301, and FIG. 8 shows a timing chart continued from FIG. The operation of the bus bridge circuit 301 differs from the operation of the bus bridge circuits 101 and 201 according to the first and second embodiments only in the generation of the access mode switching signal QUICK. Therefore, here, the operation relating to the generation of the access mode switching signal QUICK will be mainly described. In the following, an example will be described in which the period reference signal w = 4, the count-up amount adjustment signal ni = 1, the count-down amount adjustment signal nd = 1, and the comparison signal k = 4.
[0074]
If the cycle of the bus activation signal DSEL is equal to or less than the cycle reference signal w = 4, the cycle detection circuit 314 asserts the count up signal U and deasserts the count down signal D. On the other hand, if the cycle of the bus activation signal DSEL is larger than the cycle reference signal w = 4, the count up signal U is deasserted and the count down signal D is asserted.
[0075]
The up / down counter 313 counts up the internal data when the count up signal U is asserted, and counts down the internal data when the count down signal D is asserted. The count-up amount / count-down amount is set to “1” according to the count-up amount adjustment signal ni = 1 output from the register 315 and the count-down amount adjustment signal nd = 1.
[0076]
When the period of the bus activation signal DSEL is 5, since the period reference signal w is larger than 4, the period detection circuit 314 asserts the countdown signal D (arrow a in FIG. 7). In response to the asserted countdown signal D, the up / down counter 313 attempts to decrement the internal data by “1” (arrow b in FIG. 7). However, since the internal data at this time is “0”, the up / down counter 313 holds “0” of the internal data, and supplies this internal data to the comparison circuit 312 as the counter output signal Q. The comparison circuit 312 deasserts the access mode switching signal QUICK and supplies it to the control circuit 111 because the counter output signal Q = 0 is smaller than the comparison signal k = 4.
[0077]
Next, when the cycle of the bus activation signal DSEL changes to 3, since the cycle reference signal w is less than 4, the cycle detection circuit 314 asserts the count-up signal U (arrow c in FIG. 7). In response to the asserted count-up signal U, the up / down counter 313 increases the internal data by “1” and supplies it as a counter output signal Q = 1 to the comparison circuit 312 (arrow d in FIG. 7). The comparison circuit 312 deasserts the access mode switching signal QUICK and supplies it to the control circuit 111 because the counter output signal Q = 1 is smaller than the comparison signal k = 4.
[0078]
Thereafter, the value of the counter output signal Q gradually increases while the cycle of the bus activation signal DSEL is equal to or less than the cycle reference signal w = 4. When the counter output signal Q = 4 (FIG. 7, arrows e and f), the comparison circuit 312 detects that the counter output signal Q = 4 is equal to or greater than the comparison signal k = 4, and switches the access mode. Assert the signal QUICK. The access mode switching signal QUICK maintains an asserted state while the value of the counter output signal Q is “4” or more. Note that the value of the counter output signal Q does not increase beyond the maximum value (here, “7”) (FIG. 7, arrows g and h).
[0079]
When the cycle of the bus activation signal DSEL becomes “5”, the cycle detection circuit 314 asserts the countdown signal D because the cycle is larger than the cycle reference signal w = 4 (FIG. 7, arrow i). In response to the asserted countdown signal D, the up / down counter 313 decreases the internal data by “1” and supplies it to the comparison circuit 312 as the counter output signal Q = 6 (FIG. 7, arrow j).
[0080]
Thereafter, as shown in FIG. 8, the value of the counter output signal Q increases / decreases in accordance with the change in the cycle of the bus activation signal DSEL, and as a result, the access mode switching signal QUICK is asserted / deasserted.
[0081]
As described above, according to the bus bridge circuit 301 according to the third embodiment, when the access frequency from the bus A to the bus B is high (when the cycle of the bus activation signal DSEL is small), the counter output signal Q And the access mode switching signal QUICK is asserted, and high speed access from the bus A to the bus B becomes possible. On the other hand, when the access frequency from the bus A to the bus B is low (when the cycle of the bus activation signal DSEL is large), the value of the counter output signal Q is decreased and the access mode switching signal QUICK is deasserted. At this time, the access from the bus A to the bus B is in a normal access mode substantially the same as that of the conventional bus bridge circuit 1. That is, the bus bridge circuit 301 automatically switches from the normal access mode to the high-speed access mode when the access frequency from the bus A to the bus B is high, and automatically switches from the high-speed access mode when the access frequency is low. Switch to normal access mode. Therefore, even in a system in which there are many access patterns from bus A to bus B, high-speed access from bus A to bus B is easily realized, and an increase in power consumption due to high-speed access is minimized. It becomes possible to suppress to.
[0082]
In addition, the bus bridge circuit 301 includes a register 315 so that the values of the period reference signal w, the count-up amount adjustment signal ni, the count-down amount adjustment signal nd, and the comparison signal k can be arbitrarily set. Therefore, the following effects can be obtained.
[0083]
Since the value of the cycle reference signal w is adjustable, it is easy to set conditions for mode transition between the high-speed access mode and the normal access mode (power saving mode) for access from the bus A to the bus B. Therefore, even if the access patterns from the bus A to the bus B are diversified, both high-speed access and power saving are guaranteed for all access patterns.
[0084]
Since the values of the count-up amount adjustment signal ni and the count-down amount adjustment signal nd are individually adjustable, the time required for shifting from the normal access mode to the high-speed access mode and the high-speed access in the access from the bus A to the bus B It is possible to set the time required for shifting from the mode to the normal access mode independently. Therefore, it is easy to control the switching timing of special access modes, for example, “When the access frequency is high, quickly shift to the high-speed access mode, but do not immediately shift to the normal access mode even if the access frequency decreases.” It is.
[0085]
If both the count-up amount adjustment signal ni and the count-down amount adjustment signal nd are set to “0”, the up / down counter 313 does not count up and count down the internal data, and the cycle of the bus activation signal DSEL Regardless, the access mode switching signal QUICK is fixed to the asserted state or the deasserted state. That is, with respect to access from the bus A to the bus B, the high-speed access mode can be fixed, or the normal access mode can be fixed with emphasis on power consumption reduction.
[0086]
Since the value of the comparison signal k is adjustable, it is possible to control the switching timing of the access mode more finely by combining this with the adjustment of the values of the count-up amount adjustment signal ni and the count-down amount adjustment signal nd.
[0087]
[Fourth Embodiment]
FIG. 9 shows a bus bridge circuit 401 according to a fourth embodiment of the present invention. Similar to the bus bridge circuits 101, 201, and 301 according to the first, second, and third embodiments, the bus bridge circuit 401 mutually converts the protocol of the bus A and the protocol of the bus B to convert the bus A and the bus B is connected. One or more master devices (not shown) are connected to the bus A, and each master device is connected to the bus B by the bus bridge circuit 401. (Not shown) can be accessed.
[0088]
The bus bridge circuit 401 includes a control circuit 111, a bus Mux 12, a selector 412, an R / L shifter 413, a period detection circuit 414, and a register 415.
[0089]
The selector 412 includes a shifter output signal S having a predetermined bit width (here, 8-bit width) output from the R / L shifter 413 and a bit selection signal bs having a predetermined bit width (here, 8-bit width) output from the register 415. Is selected, one bit is selected from the plurality of bits of the shifter output signal S by the bit selection signal bs, and the value of the selected bit is output as the access mode switching signal QUICK.
[0090]
The R / L shifter 413 is constituted by a shift register having a plurality of bits (in this case, 8 bits), and the left shift signal L, the right shift signal R output from the period detection circuit 414, and the register 415 Based on the output right shift amount adjustment signal nr and left shift amount adjustment signal nl, the internal data is shifted right (shift in the least significant bit direction) or left shift (shift in the most significant bit direction). “0” is set to the most significant bit vacated by the right shift operation, and “1” is set to the least significant bit vacated by the left shift operation. The R / L shifter 413 supplies the internal data to the selector 412 as a shifter output signal S in synchronization with the clock signal CLK. If neither the left shift signal L nor the right shift signal R is asserted, the shift operation is not performed and the internal data is retained.
[0091]
The cycle detection circuit 414 compares the cycle reference signal w output from the register 415 with the bus activation signal DSEL. If the cycle of the bus activation signal DSEL is smaller than the cycle reference signal w, the left shift signal L is asserted and the right shift signal R is deasserted. Conversely, if the cycle of the bus activation signal DSEL is larger than the cycle reference signal w, the left shift signal L is deasserted and the right shift signal R is asserted. When the cycle of the bus activation signal DSEL coincides with the cycle reference signal w, both the left shift signal L and the right shift signal R are deasserted.
[0092]
The register 415 can set at least four values. The period detection circuits 414, R are set with the respective values as the period reference signal w, the right shift amount adjustment signal nr, the left shift amount adjustment signal nl, and the bit selection signal bs. Output to the / L shifter 413 and the selector 412.
[0093]
Next, the operation of the bus bridge circuit 401 according to the fourth embodiment will be described with reference to FIGS. 10 and 11 show the continuous data write operation from the bus A to the bus B in the bus bridge circuit 401, and FIG. 11 shows a timing chart continued from FIG. The operation of the bus bridge circuit 401 differs from the operation of the bus bridge circuits 101, 201, 301 according to the first, second, and third embodiments only in the generation of the access mode switching signal QUICK. Therefore, here, the operation relating to the generation of the access mode switching signal QUICK will be mainly described. In the following, an example will be described in which the period reference signal w = 4, the right shift amount adjustment signal nr = 1, the left shift amount adjustment adjustment signal nl = 1, and the bit selection signal bs = 4.
[0094]
The period detection circuit 414 asserts the left shift signal L and deasserts the right shift signal R if the period of the bus activation signal DSEL is equal to or less than the period reference signal w = 4. On the other hand, if the cycle of the bus activation signal DSEL is larger than the cycle reference signal w = 4, the left shift signal L is deasserted and the right shift signal R is asserted.
[0095]
The R / L shifter 413 shifts the internal data to the left when the left shift signal L is asserted, and shifts the internal data to the right when the right shift signal R is asserted. The left shift amount / right shift amount are set to “1” in accordance with the left shift amount adjustment signal nl = 1 and the right shift amount adjustment signal nr = 1 output from the register 415, respectively.
[0096]
When the period of the bus activation signal DSEL is 5, since the period reference signal w is greater than 4, the period detection circuit 414 asserts the right shift signal R (arrow a in FIG. 10). In response to the asserted right shift signal R, the R / L shifter 413 shifts the internal data “00000000” to the right and sets “0” in the empty most significant bit (arrow b in FIG. 10). By this shift operation, the internal data of the R / L shifter 413 becomes “00000000”, and the shifter output signal S of “0H” (hexadecimal number display) is input to the selector 412. Based on the bit selection signal bs = 4, the selector 412 supplies the value of the fourth bit from the least significant bit of the shifter output signal S, that is, “0” to the control circuit 111 as the access mode switching signal QUICK. Therefore, the deasserted access mode switching signal QUICK is input to the control circuit 111.
[0097]
Next, when the cycle of the bus activation signal DSEL changes to 3, since this cycle is smaller than the cycle reference signal w = 4, the cycle detection circuit 414 asserts the left shift signal L (arrow c in FIG. 10). In response to the asserted left shift signal L, the R / L shifter 413 shifts the internal data “00000000” to the left and sets “1” in the vacant least significant bit (arrow d in FIG. 10). By this shift operation, the internal data of the R / L shifter 413 becomes “00000001”, and the shifter output signal S of “1H” (in hexadecimal notation) is input to the selector 412. Based on the bit selection signal bs = 4, the selector 412 supplies the value of the fourth bit from the least significant bit of the shifter output signal S, that is, “0” to the control circuit 111 as the access mode switching signal QUICK. Therefore, the deasserted access mode switching signal QUICK is input to the control circuit 111.
[0098]
Thereafter, the value of the shifter output signal S gradually increases while the cycle of the bus activation signal DSEL is equal to or less than the cycle reference signal w = 4. When the value of the shifter output signal S becomes “FH” (FIG. 10, arrows e and f), the selector 412 indicates that the fourth bit from the least significant bit of the shifter output signal S has become “1”. In response, the access mode switching signal QUICK is asserted. While the value of the shifter output signal S is “FH” or more, since the fourth bit from the least significant bit of the shifter output signal S is “1”, the access mode switching signal QUICK maintains the asserted state. Note that the value of the shifter output signal S does not increase beyond the maximum value (here, “7FH”) (FIG. 10, arrows g and h).
[0099]
When the cycle of the bus activation signal DSEL becomes “5”, the cycle detection circuit 414 asserts the right shift signal R because the cycle is larger than the cycle reference signal w = 4 (FIG. 10, arrow i). In response to the asserted right shift signal R, the R / L shifter 413 shifts the internal data “01111111” to the right, and sets “0” in the empty most significant bit. Then, the shifter output signal S of “3FH” is input to the selector 412 (FIG. 10, arrow j).
[0100]
Thereafter, as shown in FIG. 11, the value of the shifter output signal S increases / decreases in accordance with the change in the cycle of the bus activation signal DSEL, and as a result, the access mode switching signal QUICK is asserted / deasserted.
[0101]
As described above, according to the bus bridge circuit 401 according to the fourth embodiment, when the access frequency from the bus A to the bus B is high (when the cycle of the bus activation signal DSEL is small), the shifter output signal S And the access mode switching signal QUICK is asserted, and high-speed access from the bus A to the bus B becomes possible. On the other hand, when the access frequency from the bus A to the bus B is low (when the cycle of the bus activation signal DSEL is large), the value of the shifter output signal S is decreased and the access mode switching signal QUICK is deasserted. The access from the bus A to the bus B at this time is in the normal access mode substantially the same as that of the conventional bus / bridge circuit 1. That is, the bus bridge circuit 401 automatically switches from the normal access mode to the high speed when the access frequency from the bus A to the bus B is high, like the bus bridge circuit 301 according to the third embodiment described above. When the access mode is switched and the access frequency is low, the high-speed access mode is automatically switched to the normal access mode. Therefore, even in a system in which there are many access patterns from bus A to bus B, high-speed access from bus A to bus B is easily realized, and an increase in power consumption due to high-speed access is minimized. It becomes possible to suppress to.
[0102]
In addition, the bus bridge circuit 401 includes a register 415 and can arbitrarily set each value of the period reference signal w, the right shift amount adjustment signal nr, the left shift amount adjustment signal nl, and the bit selection signal bs. The following effects can be obtained.
[0103]
Since the value of the cycle reference signal w is adjustable, it is easy to set conditions for mode transition between the high-speed access mode and the normal access mode (power saving mode) for access from the bus A to the bus B. Therefore, even if the access patterns from the bus A to the bus B are diversified, both high-speed access and power saving are guaranteed for all access patterns.
[0104]
Since the values of the right shift amount adjustment signal nr and the left shift amount adjustment signal nl are individually adjustable, in the access from the bus A to the bus B, the time required to shift from the normal access mode to the high speed access mode and the high speed It is possible to independently set the time until the transition from the access mode to the normal access mode. Therefore, it is easy to control the switching timing of special access modes, for example, “When the access frequency is high, quickly shift to the high-speed access mode, but do not immediately shift to the normal access mode even if the access frequency decreases.” It is.
[0105]
If the values of the right shift amount adjustment signal nr and the left shift amount adjustment signal nl are both set to “0”, the R / L shifter 413 stops the internal data shift operation, and the cycle of the bus activation signal DSEL is set. Regardless, the access mode switching signal QUICK is fixed to the asserted state or the deasserted state. That is, with respect to access from the bus A to the bus B, the high-speed access mode can be fixed, or the normal access mode can be fixed with emphasis on power consumption reduction.
[0106]
Since the value of the bit selection signal bs is adjustable, it is possible to control the access mode switching timing more finely by combining this with the adjustment of the values of the right shift amount adjustment signal nr and the left shift amount adjustment signal nl. Become.
[0107]
Further, since the bus bridge circuit 401 employs an R / L shifter 413 and a selector 412 each composed of a shift register as means for generating the access mode switching signal QUICK, the bus / bridge circuit 401 is compared with the up / down counter 313 and the comparison. Compared with the bus bridge circuit 301 according to the third embodiment that employs the circuit 312, the frequency of the clock signal CLK can be increased to a higher level.
[0108]
The preferred embodiments of the present invention have been described with reference to the accompanying drawings, but the present invention is not limited to such embodiments. It will be obvious to those skilled in the art that various changes or modifications can be conceived within the scope of the technical idea described in the claims, and these are naturally within the technical scope of the present invention. It is understood that it belongs.
[0109]
The bus bridge circuit 101 according to the first embodiment includes an address comparison circuit 112 and asserts / deasserts the access mode switching signal QUICK based on the address signal BA. It is also possible to directly use the value of the register as the access mode switching signal QUICK. Further, the access mode switching signal QUICK may be fixed to an asserted state or a deasserted state. Further, the access mode switching signal QUICK can be supplied from the outside.
[0110]
The bus bridge circuits 101, 201, 301, and 401 according to the first, second, third, and fourth embodiments include registers 113, 213, 315, and 415, respectively, and values of various signals such as an address comparison signal AC. Although it is possible to adjust arbitrarily, the circuit may be simplified by fixing all or a part of these values or as external inputs.
[0111]
The bus bridge circuits 301 and 401 according to the third and fourth embodiments include cycle detection circuits 314 and 414 for determining the access frequency of the bus B from the bus A, and detect the cycle of the bus activation signal DSEL. However, in addition to this, the deassertion time (or assertion time) of the bus activation signal DSEL may be used as a criterion for determining the access frequency.
[0112]
The functions of the bus bridge circuit 101 according to the first embodiment are combined with the functions of the bus bridge circuits 301 and 401 according to the third and fourth embodiments to connect a plurality of buses connected to the bus B. The count-up amount adjustment signal ni, the count-down amount adjustment signal nd, the right shift amount adjustment signal nr, and the left shift amount adjustment signal nl are individually set for each of one or more slave devices selected from the slave devices. It is also possible to do.
[0113]
【The invention's effect】
As described above, according to the bus bridge circuit of the present invention, high-speed access from a device connected to one bus to a device connected to another bus while minimizing power consumption. Is possible.
[Brief description of the drawings]
FIG. 1 is a block diagram showing a configuration of a bus bridge circuit according to a first embodiment of the present invention.
2 is a circuit diagram showing a configuration of an address comparison circuit provided in the bus bridge circuit of FIG. 1;
FIG. 3 is a timing chart showing an operation of the bus bridge circuit of FIG. 1;
FIG. 4 is a block diagram showing a configuration of a bus bridge circuit according to a second embodiment of the present invention.
5 is a timing chart showing the operation of the bus bridge circuit of FIG. 4;
FIG. 6 is a block diagram showing a configuration of a bus bridge circuit according to a third embodiment of the present invention.
7 is a timing chart (part 1) showing the operation of the bus bridge circuit of FIG. 6; FIG.
8 is a timing chart (part 2) illustrating the operation of the bus bridge circuit of FIG. 6;
FIG. 9 is a block diagram showing a configuration of a bus bridge circuit according to a fourth embodiment of the present invention.
FIG. 10 is a timing chart (part 1) illustrating the operation of the bus bridge circuit of FIG. 9;
FIG. 11 is a timing chart (part 2) illustrating the operation of the bus bridge circuit of FIG. 9;
FIG. 12 is a block diagram showing a configuration of a conventional bus bridge circuit.
13 is a timing chart showing the operation of the bus bridge circuit of FIG.
[Explanation of symbols]
1: Bus bridge circuit
11: Control circuit
12: Bus Mux
101: Bus bridge circuit
111: Control circuit
112: Address comparison circuit
113: Register
201: Bus bridge circuit
212: n / m counter
213: Register
301: Bus bridge circuit
312: Comparison circuit
313: Up / down counter
314: Period detection circuit
315: Register
401: Bus bridge circuit
412: Selector
413: R / L shifter
414: Period detection circuit
415: Register
AC: Address comparison signal
ADB: Address / data signal
ADB_OE: ADB data output request signal
ADR_OUT: Address transfer request signal
ASTB: Address strobe signal
BA: Address signal
BD: Data signal
BD_OE: BD data output request signal
bs: Bit selection signal
CLK: Clock signal
D: Countdown signal
DSEL: Bus start signal
k: Comparison signal
L: Left shift signal
m: 1st signal
n: Second signal
nd: Countdown amount adjustment signal
ni: Count-up amount adjustment signal
nl: Left shift amount adjustment signal
nr: right shift amount adjustment signal
Q: Counter output signal
QUICK: Access mode switching signal
R: Right shift signal
RDE: Read enable signal
S: Shifter output signal
U: Count up signal
w: Period reference signal
WAIT: Wait signal
WRE: Write enable signal
WRITE: Write signal

Claims (5)

Connect the first bus and the second bus,
An address for identifying one or more second devices output from the first device connected to the first bus and connected to the second bus is assigned from the first bus to the second bus. To
Data output from the first device and written to one or more second devices selected from the one or more second devices by the address is transferred from the first bus to the second bus. Transmit,
Data output from one or more second devices selected from the one or more second devices according to the address and read into the first device is transferred from the second bus to the first bus. Transmit,
Bus bridge circuit:
Comprising an access mode switching signal output means for selectively outputting an asserted access mode switching signal when a predetermined condition is satisfied;
When the access mode switching signal is deasserted, the address output from the first device is transmitted from the first bus to the second bus after receiving the bus activation signal output from the first device. Then, one or more second devices are selected from the one or more second devices, and data writing / writing between the first device and the selected one or more second devices is performed. A first access mode for reading data;
When the access mode switching signal is asserted, the address output from the first device is transmitted from the first bus to the second bus according to the access mode switching signal to transmit the one or more second or more After selecting one or more second devices from the two devices and receiving a bus activation signal output from the first device, the first device and the one or more second devices previously selected A second access mode for writing / reading data to / from two devices;
A bus bridge circuit characterized by having at least two access modes. A register capable of setting a predetermined address;
When the address or address range set in the register is compared with the address output from the first device and both addresses match , the asserted access mode switching signal is determined to satisfy the predetermined condition. An address comparison circuit to output;
2. The bus bridge circuit according to claim 1, further comprising: as an access mode switching signal output means . A register capable of setting a first value and a second value;
The bus activation signal is received, the number of times of reception is counted, and while the count value reaches the first value from the initial value , the predetermined condition is satisfied, and the access that has been asserted the number of times according to the second value A counter that outputs a mode switching signal;
2. The bus bridge circuit according to claim 1, further comprising: as an access mode switching signal output means . A register capable of setting a first value, a second value, a third value, and a fourth value;
A period detection circuit that receives the bus activation signal, detects a reception period, compares the reception period with the first value, and outputs a count-up signal or a count-down signal according to the comparison result;
A counter that increases internal data in a step according to the second value when the count-up signal is input, and decreases the internal data in a step according to the third value when the count-down signal is input;
A comparison circuit that compares the internal data of the counter with the fourth value, and outputs the access mode switching signal that is asserted when the predetermined condition is satisfied when the internal data is equal to or greater than the fourth value ;
2. The bus bridge circuit according to claim 1, further comprising: as an access mode switching signal output means . A register capable of setting a first value, a second value, a third value, and a fourth value;
A period detection circuit that receives the bus activation signal, detects a reception period, compares the reception period with the first value, and outputs a first shift signal or a second shift signal according to the comparison result;
When the first shift signal is input, all bits of the internal data are shifted in one direction in steps corresponding to the second value, and when the second shift signal is input, all the bits of the internal data are A shift register that shifts in the other direction in steps according to the third value;
A selector that selects a predetermined bit of the internal data according to the fourth value and outputs a value of the selected predetermined bit as the access mode switching signal;
2. The bus bridge circuit according to claim 1, further comprising: as an access mode switching signal output means .

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