JP2009093283A - Multichip system and semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a multichip system having a small transfer delay, and a semiconductor device constituting the above multichip system. <P>SOLUTION: An address ID decision section 3 immediately decides a data destination address at the time point that an address ID included in the header part of a received data DAT_1 is received, and when it is not being addressed to itself, a transmission control section 4 transfers the received data DAT_1 simultaneously with the reception of the received data DAT_1 in the reception data buffer 1. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a multichip system in which a plurality of semiconductor devices (semiconductor chips) form a network and communicate with each other, and a semiconductor device constituting the multichip system.

There is known a multi-chip system configured such that a plurality of semiconductor devices (semiconductor chips) form a network and communicate with each other to realize a specific function (for example, see Patent Document 1). ). In such a multi-chip system, there is a system in which a plurality of semiconductor devices are connected in a ring shape and data is transferred only in one direction (for example, clockwise). For example, if the multi-chip system is composed of three chips, chip A, chip B, and chip C, data is transferred in order of chip A to chip B, chip B to chip C, chip C to chip A, and so on. Here, even when data is simply transmitted from chip A to chip C, data cannot be transmitted directly from chip A to chip C, and data is transferred via chip B.
Japanese Unexamined Patent Publication No. 6-332852

  FIG. 6 shows data transmission / reception timing in each chip when data is transmitted from chip A to chip C as described above. Chip A transmits packet data of a predetermined size. The chip B receives this packet data, and when receiving the entire packet data, analyzes the control information such as the destination and starts the transfer to the chip C. Chip C receives the packet data thus transferred from chip B. Therefore, as is apparent from FIG. 6, the data transmission from the chip A to the chip C causes a transfer delay corresponding to at least the size of the packet data to be transmitted. This transfer delay causes a problem that the throughput of data transmission between chips is reduced, and consequently the performance of the multichip system is deteriorated.

  In order to speed up data transmission from chip A to chip C, the ring network is configured to be capable of bidirectional communication (that is, clockwise or counterclockwise), and data is directly transmitted from chip A to chip C. However, there is a drawback that the number of signal lines necessary and the number of terminals of the chip for connecting to the signal lines are doubled and the configuration becomes complicated as compared with the case of communication in only one direction.

  The present invention has been made in view of the above points, and an object thereof is to provide a multichip system with a small transfer delay and a semiconductor device constituting the multichip system.

  The present invention has been made in order to solve the above-described problem. The first, second, and third semiconductor devices form a network, and the data transmitted by the first semiconductor device is transmitted to the second semiconductor device. In a multi-chip system in which a device selectively acquires or transfers to a third semiconductor device according to its destination, the first semiconductor device transmits destination data by placing destination information in a data header portion. A control unit, wherein the second semiconductor device receives and temporarily stores data transmitted from the first semiconductor device, and stores the destination information when the destination information is stored in the buffer. A destination determination unit that reads the data from the buffer and determines a data destination; and when the destination determination unit determines that the data destination is not itself, Characterized in that it comprises a transmission control unit for transferring data to the third semiconductor device is read out sequentially from the buffer from that point.

  Further, according to the present invention, in the above multichip system, the second semiconductor device receives and acquires the data from the buffer when the destination determination unit determines that the destination of the data is itself A control unit is provided.

  According to another aspect of the present invention, in the semiconductor device, a buffer that receives and temporarily stores data in which the destination information is arranged in the header portion, and reads the destination information from the buffer when the destination information is stored in the buffer. If the destination determination unit determines that the data destination is not itself by the destination determination unit, the data being received by the buffer is read from the buffer sequentially from that point and the other A transmission control unit for transferring to the semiconductor device

  According to the present invention, when the destination information of the header part is received, the destination determination unit immediately determines the destination of the data. If it is not addressed to itself, the transmission control unit proceeds with the data reception by the buffer at the same time. Therefore, the transfer delay associated with the data transfer is at most about the time required to receive the destination information in the header portion. Therefore, the transfer delay can be reduced as compared with the conventional case.

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.
FIG. 1 is a diagram showing an overall configuration of a multichip system according to an embodiment of the present invention. In this multi-chip system, three chips (semiconductor devices) of chip A, chip B, and chip C are connected in a ring shape to form a network, and these three chips communicate with each other. It is configured to realize a specific function. In the communication between the chips, data transmission is performed only in one direction from chip A to chip B, chip B to chip C, and chip C to chip A. In the present embodiment, hereinafter, chip A first transmits data to chip B or chip C, chip B receives this data, and chip B is not addressed to itself (chip B). The description will be made assuming that the data is transferred to the chip C and the chip B obtains the data when addressed to the chip C. The contents of the “specific function” of the multi-chip realized by mutual communication between the chips are arbitrary, and the present invention is not limited to the function.

  FIG. 2 is a block diagram schematically showing a functional configuration of each semiconductor device constituting the multichip system of FIG. Chip A, chip B, and chip C all have the configuration of this block diagram in common. In FIG. 2, the semiconductor device includes a reception data buffer 1, a reception control unit 2, a destination ID determination unit 3, a transmission control unit 4, a transmission data buffer 5, a clock generation unit 6, a CPU 7, and an internal memory. 8 and.

First, the function of each unit when this semiconductor device operates as the chip A that transmits data first will be described.
The CPU 7 generates data DAT_2 ′ to be transmitted and stores it in the internal memory 8, reads this data DAT_2 ′ from the internal memory 8, and writes it in the transmission data buffer 5. The clock generation unit 6 generates an internal clock CLK_2 that is used as a time reference for the operation of each unit of the semiconductor device and supplies the internal clock CLK_2 to the CPU 7 and the transmission control unit 4. The transmission control unit 4 reads the data DAT_2 ′ from the transmission data buffer 5 at a predetermined timing synchronized with the internal clock CLK_2, and adds the header part H to the head of the data DAT_2 ′ to generate transmission data DAT_2.

  The data structure of the transmission data DAT_2 is shown in FIG. The transmission data DAT_2 is packet data having a predetermined size, and the header portion H includes control information, a destination ID, and a transmission source ID. The control information represents the type of data to be transmitted and is information for controlling communication between chips. For example, the data destination is a single chip, the destination is all chips in a multi-chip system, the multi-chip system is initialized, or there is no other transmission data, and data is freely transmitted Whether or not it is possible is distinguished by this control information. The destination ID is information for designating an ID for identifying a chip that is a data destination. The transmission source ID is information that specifies an ID for identifying a chip that is a data transmission source. Here, as the header portion H of the transmission data DAT_2, the ID of chip A is set as the transmission source ID, the ID of chip B or chip C is set as the destination ID, and the data destination is a single chip in the control information. It is assumed that information indicating that it exists is set. Note that the data DAT_2 'read from the transmission data buffer 5 is arranged in the "data" part after the header part H in the data structure of FIG.

  The transmission control unit 4 transmits the generated transmission data DAT_2, the transmission clock CLK_2 (= internal clock CLK_2), and the transmission enable signal ENBL_2 set to the high level to the chip B in synchronization with the internal clock CLK_2. . Note that separate signal lines are used for transmitting these signals (transmission data DAT_2, transmission clock CLK_2, transmission enable signal ENBL_2).

  In this way, transmission data including the destination ID in the header portion is transmitted from the semiconductor device (chip A) to the other semiconductor device (chip B).

  Next, functions of each unit when the semiconductor device operates as a chip B that transfers or acquires data according to the destination of received data will be described.

  Reception data DAT_1, reception enable signal ENBL1, and reception clock CLK_1 are input to reception data buffer 1. The reception data DAT_1 is transmission data DAT_2 transmitted from the chip A, the reception enable signal ENBL_1 is a high-level transmission enable signal ENBL_2 transmitted from the chip A, and the reception clock CLK_1 is transmitted from the chip A. The transmission clock CLK_2. The reception data buffer 1 receives the high level reception enable signal ENBL_1, and sequentially receives and stores the reception data DAT_1 from the header portion H in synchronization with the reception clock CLK_1.

  The reception control unit 2 sequentially reads the reception data DAT_1 stored in the reception data buffer 1 simultaneously with the data storage in the reception data buffer 1, and among the read data, the destination ID included in the header part H It passes to ID judgment part 3. Here, since storage of data in the reception data buffer 1 and reading of data by the reception control unit 2 are performed simultaneously, the destination ID is stored in the reception data buffer 1 at the same time, in other words, received. Before the data DAT_1 is received to the end and stored in the reception data buffer 1 is completed, it is passed to the destination ID determination unit 3.

  The destination ID determination unit 3 identifies the destination ID and determines the semiconductor device that is the destination of the received data DAT_1. As a result, when the destination is not itself (chip B), the destination ID determination unit 3 instructs the transmission control unit 4 to transfer the reception data DAT_1. When the destination is itself, the destination ID determination unit 3 receives the data. The control unit 2 is instructed to acquire the reception data DAT_1. Here, it is assumed that the determination of the destination is performed immediately when the destination ID is passed, and the transfer instruction to the transmission control unit 4 is also performed immediately thereafter. Therefore, at the time when the transfer instruction is given to the transmission control unit 4, the received data DAT_1 is still stored in the received data buffer 1 only halfway.

  When the transmission control unit 4 receives the received data transfer instruction from the destination ID determination unit 3, the transmission control unit 4 sequentially reads the received data DAT — 1 stored in the received data buffer 1 simultaneously with the data storage in the received data buffer 1, In synchronization with the internal clock CLK_2, the read data is transferred to the chip C as transfer data DAT_1. The data structure of the transfer data DAT_1 is the same as that shown in FIG. Further, when transferring the transfer data DAT_1, the transmission control unit 4 also transmits the transmission clock CLK_2 and the transmission enable signal ENBL_2 to the chip C as in the case of the chip A described above.

  Here, as described above, at the time when the transmission control unit 4 receives the transfer instruction, the reception data DAT_1 is still stored in the reception data buffer 1 only halfway, but the transmission control unit 4 receives the data immediately from that point. Reading is started from the received data DAT_1 stored in the data buffer 1, and transfer is started. At the same time, the reception data DAT_1 is continuously stored in the reception data buffer 1, and the transmission control unit 4 sequentially reads and advances the transfer. Therefore, since the transfer is started before the reception data DAT_1 is completely received to the end, the transfer delay when the chip B performs the data transfer can be reduced.

Next, the operation of the semiconductor device as the chip B will be described along the flowchart shown in FIG.
First, the reception data buffer 1 starts storing the reception data DAT_1 (step S1). At the same time, the reception control unit 2 reads the reception data DAT_1 from the portion stored in the reception data buffer 1 and passes the destination ID to the destination ID determination unit 3 when the destination ID of the header part H is read. The destination ID determination unit 3 determines the destination of the reception data DAT_1 based on the destination ID (step S2), and when the destination is not itself, instructs the transmission control unit 4 to transfer the reception data DAT_1 (step S3). In response to this transfer instruction, the transmission control unit 4 starts to transfer the received data DAT_1 (step S4). At this time, the remaining portion of the reception data DAT_1 is continuously stored in the reception data buffer 1, and the storage and transfer of the reception data DAT_1 proceed simultaneously until the storage of the last portion of the data is completed. Go (step S5). In this way, data transfer from chip A to chip C is executed by chip B.

  If the destination is oneself in step S2, the destination ID determination unit 3 instructs the reception control unit 2 to acquire the reception data DAT_1. In response to this instruction, the reception control unit 2 writes the data portion DAT_1 'excluding the header portion H of the reception data DAT_1 read from the reception data buffer 1 into the internal memory 8 (steps S6 and S7). At this time, since the reception data DAT_1 reaches the destination chip B, the transmission data does not exist and each chip can freely transmit data. It instructs the control information indicating that to be transmitted. The transmission control unit 4 sets information indicating that the transmission information can be freely transmitted without any other transmission data in the control information, and transmits the data shown in FIG. 3 (b) including only this control information to other chips. To do.

Next, FIG. 5 shows data transmission / reception timing in each chip when data is transmitted from chip A to chip C in the multichip system of the present embodiment.
As described above, the chip A transmits the data including the destination ID in the header part H to the chip B. When the chip B receives the destination ID and determines that the data destination is the chip C, the chip A immediately Start data transfer to C. Since the chip C receives the packet data transferred in this way from the chip B, as is clear from FIG. 5, the time required for receiving the destination ID at most for data transmission from the chip A to the chip C is as follows. Only the transfer delay occurs. The magnitude of this transfer delay is much smaller than that in the prior art shown in FIG. Therefore, according to the multichip system of the present embodiment, it is possible to improve the throughput of data transmission between chips.

As described above, the embodiment of the present invention has been described in detail with reference to the drawings. However, the specific configuration is not limited to the above, and various design changes and the like can be made without departing from the scope of the present invention. It is possible to
For example, in the above embodiment, the multi-chip system is composed of three semiconductor devices, but the number of semiconductor devices is arbitrary, and it goes without saying that the present invention is not limited to this.
Further, the data structure of the data transmitted first by the chip A may be a system in which the header portion H and the data portion are transmitted through different signal lines as shown in FIG. Also in this case, since the destination ID can be determined before the reception of the data part is completed, the same effect as that of the above-described embodiment can be obtained.

1 is a diagram illustrating an overall configuration of a multichip system according to an embodiment of the present invention. FIG. 2 is a block diagram schematically showing a functional configuration of individual semiconductor devices constituting the multichip system of FIG. 1. It is a figure which shows the data structure of the data transmitted. 6 is a flowchart illustrating an operation in which a semiconductor device transfers or acquires data according to a destination of received data. It is a figure which shows the transmission / reception timing of the data in each chip | tip in the case of transmitting data from the chip | tip A to the chip | tip C in the multichip system of this invention. It is a figure which shows the transmission / reception timing of the data in each chip | tip in the case of transmitting data from the chip | tip A to the chip | tip C in the conventional multichip system.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 1 ... Reception data buffer 2 ... Reception control part 3 ... Destination ID determination part 4 ... Transmission control part 5 ... Transmission data buffer 6 ... Clock generation part 7 ... CPU 8 ... Internal memory

Claims (3)

The first, second, and third semiconductor devices form a network, and the second semiconductor device selectively acquires the data transmitted by the first semiconductor device according to the destination or the third semiconductor device. In multi-chip system transferring to
The first semiconductor device includes:
A transmission control unit that arranges destination information in the header part of the data and transmits the data,
The second semiconductor device includes:
A buffer for receiving and temporarily storing data transmitted from the first semiconductor device;
A destination determination unit that reads the destination information from the buffer and determines the destination of the data when the destination information is stored in the buffer;
A transmission control unit configured to sequentially read the data being received by the buffer from the buffer and transfer the data to the third semiconductor device when the destination determination unit determines that the data destination is not itself; A multi-chip system comprising:   The said 2nd semiconductor device is provided with the reception control part which reads and acquires the data from the said buffer, when the destination of data determines with the destination determination part that it is self. The described multi-chip system. A buffer for receiving and temporarily storing data in which the destination information is arranged in the header part;
A destination determination unit that reads the destination information from the buffer and determines the destination of the data when the destination information is stored in the buffer;
A transmission control unit that, when the destination determination unit determines that the destination of data is not itself, the buffer that is being received by the buffer sequentially reads the data from the buffer from that point and transfers the data to another semiconductor device; A semiconductor device comprising:

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